Shuo Liu | a5487ba | 2024-03-18 00:42:42 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | |
| 3 | #include <acpi/acpigen_pci.h> |
| 4 | #include <assert.h> |
| 5 | #include <console/console.h> |
| 6 | #include <device/pci.h> |
| 7 | #include <intelblocks/acpi.h> |
| 8 | #include <post.h> |
| 9 | #include <soc/acpi.h> |
| 10 | #include <soc/chip_common.h> |
| 11 | #include <soc/numa.h> |
| 12 | #include <soc/soc_util.h> |
| 13 | #include <soc/util.h> |
| 14 | #include <stdlib.h> |
| 15 | |
| 16 | static const UDS_PCIROOT_RES *domain_to_pciroot_res(const struct device *dev) |
| 17 | { |
| 18 | assert(dev->path.type == DEVICE_PATH_DOMAIN); |
| 19 | const union xeon_domain_path dn = { |
| 20 | .domain_path = dev->path.domain.domain |
| 21 | }; |
| 22 | |
| 23 | const IIO_UDS *hob = get_iio_uds(); |
| 24 | assert(hob != NULL); |
| 25 | |
| 26 | const UDS_STACK_RES *sr = &hob->PlatformData.IIO_resource[dn.socket].StackRes[dn.stack]; |
| 27 | for (unsigned int index = 0; index < sr->PciRootBridgeNum; index++) { |
| 28 | if (sr->PciRoot[index].BusBase == dev->downstream->secondary) |
| 29 | return &sr->PciRoot[index]; |
| 30 | } |
| 31 | |
| 32 | return NULL; |
| 33 | } |
| 34 | |
| 35 | static void iio_pci_domain_read_resources(struct device *dev) |
| 36 | { |
| 37 | int index = 0; |
Shuo Liu | a5487ba | 2024-03-18 00:42:42 +0800 | [diff] [blame] | 38 | const UDS_PCIROOT_RES *pr = domain_to_pciroot_res(dev); |
| 39 | |
| 40 | /* Initialize the system-wide I/O space constraints. */ |
Shuo Liu | 6c708d8 | 2024-04-29 18:16:30 +0800 | [diff] [blame^] | 41 | if (pr->IoBase <= pr->IoLimit) |
| 42 | domain_io_window_from_to(dev, index++, |
| 43 | pr->IoBase, pr->IoLimit + 1); |
Shuo Liu | a5487ba | 2024-03-18 00:42:42 +0800 | [diff] [blame] | 44 | |
| 45 | /* The 0 - 0xfff IO range is not reported by the HOB but still gets decoded */ |
| 46 | if (is_domain0(dev)) { |
Shuo Liu | 6c708d8 | 2024-04-29 18:16:30 +0800 | [diff] [blame^] | 47 | struct resource *res = new_resource(dev, index++); |
Shuo Liu | a5487ba | 2024-03-18 00:42:42 +0800 | [diff] [blame] | 48 | res->base = 0; |
| 49 | res->limit = 0xfff; |
| 50 | res->size = 0x1000; |
| 51 | res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; |
| 52 | } |
| 53 | |
| 54 | /* Initialize the system-wide memory resources constraints. */ |
Shuo Liu | 6c708d8 | 2024-04-29 18:16:30 +0800 | [diff] [blame^] | 55 | if (pr->Mmio32Base <= pr->Mmio32Limit) |
| 56 | domain_mem_window_from_to(dev, index++, |
| 57 | pr->Mmio32Base, pr->Mmio32Limit + 1); |
Shuo Liu | a5487ba | 2024-03-18 00:42:42 +0800 | [diff] [blame] | 58 | |
| 59 | /* Initialize the system-wide memory resources constraints. */ |
Shuo Liu | 6c708d8 | 2024-04-29 18:16:30 +0800 | [diff] [blame^] | 60 | if (pr->Mmio64Base <= pr->Mmio64Limit) |
| 61 | domain_mem_window_from_to(dev, index++, |
| 62 | pr->Mmio64Base, pr->Mmio64Limit + 1); |
Shuo Liu | a5487ba | 2024-03-18 00:42:42 +0800 | [diff] [blame] | 63 | } |
| 64 | |
| 65 | static struct device_operations iio_pcie_domain_ops = { |
| 66 | .read_resources = iio_pci_domain_read_resources, |
| 67 | .set_resources = pci_domain_set_resources, |
| 68 | .scan_bus = pci_host_bridge_scan_bus, |
| 69 | #if CONFIG(HAVE_ACPI_TABLES) |
| 70 | .acpi_name = soc_acpi_name, |
| 71 | .write_acpi_tables = northbridge_write_acpi_tables, |
| 72 | .acpi_fill_ssdt = pci_domain_fill_ssdt, |
| 73 | #endif |
| 74 | }; |
| 75 | |
| 76 | void create_xeonsp_domains(const union xeon_domain_path dp, struct bus *bus, |
| 77 | const xSTACK_RES *sr, const size_t pci_segment_group) |
| 78 | { |
| 79 | for (unsigned int index = 0; index < sr->PciRootBridgeNum; index++) { |
| 80 | const UDS_PCIROOT_RES *pr = &sr->PciRoot[index]; |
| 81 | create_domain(dp, bus, |
| 82 | pr->BusBase, |
| 83 | pr->BusLimit, |
| 84 | pciroot_res_to_domain_type(sr, pr), |
| 85 | &iio_pcie_domain_ops, |
| 86 | pci_segment_group); |
| 87 | } |
| 88 | } |