Matt DeVillier | 45b1da3 | 2022-09-07 17:21:01 -0500 | [diff] [blame] | 1 | chip soc/intel/cannonlake |
| 2 | |
| 3 | # GPE configuration |
| 4 | # Note that GPE events called out in ASL code rely on this |
| 5 | # route. i.e. If this route changes then the affected GPE |
| 6 | # offset bits also need to be changed. |
| 7 | # DW1 is used by: |
| 8 | # - GPP_C1 - PCIE_14_WLAN_WAKE_ODL |
| 9 | # - GPP_C21 - H1_PCH_INT_ODL |
| 10 | register "gpe0_dw0" = "PMC_GPP_A" |
| 11 | register "gpe0_dw1" = "PMC_GPP_C" |
| 12 | register "gpe0_dw2" = "PMC_GPP_D" |
| 13 | |
| 14 | # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f |
| 15 | register "gen1_dec" = "0x00fc0801" |
| 16 | register "gen2_dec" = "0x000c0201" |
| 17 | # EC memory map range is 0x900-0x9ff |
| 18 | register "gen3_dec" = "0x00fc0901" |
| 19 | |
| 20 | # FSP configuration |
| 21 | register "SkipExtGfxScan" = "1" |
| 22 | register "SataSalpSupport" = "1" |
| 23 | register "SataPortsEnable[1]" = "1" |
| 24 | register "SataPortsDevSlp[1]" = "1" |
| 25 | # Configure devslp pad reset to PLT_RST |
| 26 | register "SataPortsDevSlpResetConfig[1]" = "SataDevSlpPlatformReset" |
| 27 | register "satapwroptimize" = "1" |
| 28 | # Enable System Agent dynamic frequency |
| 29 | register "SaGv" = "SaGv_Enabled" |
| 30 | # Enable S0ix |
| 31 | register "s0ix_enable" = "1" |
| 32 | # Enable DPTF |
| 33 | register "dptf_enable" = "1" |
| 34 | register "power_limits_config" = "{ |
| 35 | .tdp_pl1_override = 15, |
| 36 | .tdp_pl2_override = 64, |
| 37 | }" |
| 38 | register "Device4Enable" = "1" |
| 39 | # Enable eDP device |
| 40 | register "DdiPortEdp" = "1" |
| 41 | # Enable HPD for DDI ports B/C |
| 42 | register "DdiPortBHpd" = "1" |
| 43 | register "DdiPortCHpd" = "1" |
| 44 | register "tcc_offset" = "10" # TCC of 90C |
| 45 | # Unlock GPIO pads |
| 46 | register "PchUnlockGpioPads" = "1" |
| 47 | # SD card WP pin configuration |
| 48 | register "ScsSdCardWpPinEnabled" = "0" |
| 49 | |
| 50 | # NOTE: if any variant wants to override this value, use the same format |
| 51 | # as register "common_soc_config.pch_thermal_trip" = "value", instead of |
| 52 | # putting it under register "common_soc_config" in overridetree.cb file. |
| 53 | register "common_soc_config.pch_thermal_trip" = "77" |
| 54 | |
| 55 | # Select CPU PL2/PL4 config |
| 56 | register "cpu_pl2_4_cfg" = "baseline" |
| 57 | |
| 58 | # VR Settings Configuration for 4 Domains |
| 59 | #+----------------+-------+-------+-------+-------+ |
| 60 | #| Domain/Setting | SA | IA | GTUS | GTS | |
| 61 | #+----------------+-------+-------+-------+-------+ |
| 62 | #| Psi1Threshold | 20A | 20A | 20A | 20A | |
| 63 | #| Psi2Threshold | 5A | 5A | 5A | 5A | |
| 64 | #| Psi3Threshold | 1A | 1A | 1A | 1A | |
| 65 | #| Psi3Enable | 1 | 1 | 1 | 1 | |
| 66 | #| Psi4Enable | 1 | 1 | 1 | 1 | |
| 67 | #| ImonSlope | 0 | 0 | 0 | 0 | |
| 68 | #| ImonOffset | 0 | 0 | 0 | 0 | |
| 69 | #| IccMax | 6A | 70A | 31A | 31A | |
| 70 | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | |
| 71 | #| AcLoadline | 10.3 | 1.8 | 3.1 | 3.1 | |
| 72 | #| DcLoadline | 10.3 | 1.8 | 3.1 | 3.1 | |
| 73 | #+----------------+-------+-------+-------+-------+ |
| 74 | register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ |
| 75 | .vr_config_enable = 1, |
| 76 | .psi1threshold = VR_CFG_AMP(20), |
| 77 | .psi2threshold = VR_CFG_AMP(5), |
| 78 | .psi3threshold = VR_CFG_AMP(1), |
| 79 | .psi3enable = 1, |
| 80 | .psi4enable = 1, |
| 81 | .imon_slope = 0x0, |
| 82 | .imon_offset = 0x0, |
| 83 | .icc_max = 0, |
| 84 | .voltage_limit = 1520, |
| 85 | .ac_loadline = 1030, |
| 86 | .dc_loadline = 1030, |
| 87 | }" |
| 88 | |
| 89 | register "domain_vr_config[VR_IA_CORE]" = "{ |
| 90 | .vr_config_enable = 1, |
| 91 | .psi1threshold = VR_CFG_AMP(20), |
| 92 | .psi2threshold = VR_CFG_AMP(5), |
| 93 | .psi3threshold = VR_CFG_AMP(1), |
| 94 | .psi3enable = 1, |
| 95 | .psi4enable = 1, |
| 96 | .imon_slope = 0x0, |
| 97 | .imon_offset = 0x0, |
| 98 | .icc_max = 0, |
| 99 | .voltage_limit = 1520, |
| 100 | .ac_loadline = 180, |
| 101 | .dc_loadline = 180, |
| 102 | }" |
| 103 | |
| 104 | register "domain_vr_config[VR_GT_UNSLICED]" = "{ |
| 105 | .vr_config_enable = 1, |
| 106 | .psi1threshold = VR_CFG_AMP(20), |
| 107 | .psi2threshold = VR_CFG_AMP(5), |
| 108 | .psi3threshold = VR_CFG_AMP(1), |
| 109 | .psi3enable = 1, |
| 110 | .psi4enable = 1, |
| 111 | .imon_slope = 0x0, |
| 112 | .imon_offset = 0x0, |
| 113 | .icc_max = 0, |
| 114 | .voltage_limit = 1520, |
| 115 | .ac_loadline = 310, |
| 116 | .dc_loadline = 310, |
| 117 | }" |
| 118 | |
| 119 | register "domain_vr_config[VR_GT_SLICED]" = "{ |
| 120 | .vr_config_enable = 1, |
| 121 | .psi1threshold = VR_CFG_AMP(20), |
| 122 | .psi2threshold = VR_CFG_AMP(5), |
| 123 | .psi3threshold = VR_CFG_AMP(1), |
| 124 | .psi3enable = 1, |
| 125 | .psi4enable = 1, |
| 126 | .imon_slope = 0x0, |
| 127 | .imon_offset = 0x0, |
| 128 | .icc_max = 0, |
| 129 | .voltage_limit = 1520, |
| 130 | .ac_loadline = 310, |
| 131 | .dc_loadline = 310, |
| 132 | }" |
| 133 | |
| 134 | register "PchPmSlpS3MinAssert" = "2" # 50ms |
| 135 | register "PchPmSlpS4MinAssert" = "1" # 1s |
| 136 | register "PchPmSlpSusMinAssert" = "1" # 500ms |
| 137 | register "PchPmSlpAMinAssert" = "3" # 98ms |
| 138 | |
| 139 | # NOTE: Duration programmed in the below register should never be smaller than the |
| 140 | # stretch duration programmed in the following registers - |
| 141 | # - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert) |
| 142 | # - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert) |
| 143 | # - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert) |
| 144 | # - PM_CFG.SLP_LAN_MIN_ASST_WDTH |
| 145 | register "PchPmPwrCycDur" = "1" # 1s |
| 146 | |
| 147 | # Enable Audio DSP oscillator qualification for S0ix |
| 148 | register "cppmvric2_adsposcdis" = "1" |
| 149 | |
| 150 | register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 0 |
| 151 | register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 1 |
| 152 | register "usb2_ports[2]" = "USB2_PORT_SHORT(OC3)" # Type-A Port 0 |
| 153 | register "usb2_ports[3]" = "USB2_PORT_LONG(OC3)" # Type-A Port 1 |
| 154 | register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # WWAN |
| 155 | register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)" # Camera |
| 156 | register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # BT |
| 157 | |
| 158 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 0 |
| 159 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 1 |
| 160 | register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 0 |
| 161 | register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 1 |
| 162 | register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN |
| 163 | |
| 164 | # Enable Root port 9(x4) for NVMe. |
| 165 | register "PcieRpEnable[8]" = "1" |
| 166 | register "PcieRpLtrEnable[8]" = "1" |
| 167 | # RP 9 uses CLK SRC 1 |
| 168 | register "PcieClkSrcUsage[1]" = "8" |
| 169 | # ClkReq-to-ClkSrc mapping for CLK SRC 1 |
| 170 | register "PcieClkSrcClkReq[1]" = "1" |
| 171 | |
| 172 | # PCIe port 14 for M.2 E-key WLAN |
| 173 | register "PcieRpEnable[13]" = "1" |
| 174 | register "PcieRpLtrEnable[13]" = "1" |
| 175 | # RP 14 uses CLK SRC 3 |
| 176 | register "PcieClkSrcUsage[3]" = "13" |
| 177 | register "PcieClkSrcClkReq[3]" = "3" |
| 178 | |
| 179 | #Enable I2S Audio, SSP0, SSP1 and DMIC0, default DMIC1 N/A (by variants override) |
| 180 | register "PchHdaDspEnable" = "1" |
| 181 | register "PchHdaAudioLinkSsp0" = "1" |
| 182 | register "PchHdaAudioLinkSsp1" = "1" |
| 183 | register "PchHdaAudioLinkDmic0" = "1" |
| 184 | register "PchHdaAudioLinkDmic1" = "0" |
| 185 | |
| 186 | # GPIO PM programming |
| 187 | register "gpio_override_pm" = "1" |
| 188 | |
| 189 | # GPIO community PM configuration |
| 190 | # Disable dynamic clock gating; with bits 0-5 set in these registers, |
| 191 | # some short interrupt pulses were missed (esp. cr50 irq) |
| 192 | register "gpio_pm[COMM_0]" = "0" |
| 193 | register "gpio_pm[COMM_1]" = "0" |
| 194 | register "gpio_pm[COMM_2]" = "0" |
| 195 | register "gpio_pm[COMM_3]" = "0" |
| 196 | register "gpio_pm[COMM_4]" = "0" |
| 197 | |
Arthur Heymans | 69cd729 | 2022-11-07 13:52:11 +0100 | [diff] [blame] | 198 | device cpu_cluster 0 on end |
Matt DeVillier | 45b1da3 | 2022-09-07 17:21:01 -0500 | [diff] [blame] | 199 | |
| 200 | device domain 0 on |
| 201 | device pci 00.0 on end # Host Bridge |
| 202 | device pci 02.0 on end # Integrated Graphics Device |
| 203 | device pci 04.0 off end # SA Thermal device |
| 204 | device pci 05.0 off end # SA IPU |
| 205 | device pci 12.0 on end # Thermal Subsystem |
| 206 | device pci 12.5 off end # UFS SCS |
| 207 | device pci 12.6 off end # GSPI #2 |
| 208 | device pci 14.0 on |
| 209 | chip drivers/usb/acpi |
| 210 | register "desc" = ""Root Hub"" |
| 211 | register "type" = "UPC_TYPE_HUB" |
| 212 | device usb 0.0 on |
| 213 | chip drivers/usb/acpi |
| 214 | register "desc" = ""Left Type-C Port"" |
| 215 | register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| 216 | register "group" = "ACPI_PLD_GROUP(1, 1)" |
| 217 | device usb 2.0 on end |
| 218 | end |
| 219 | chip drivers/usb/acpi |
| 220 | register "desc" = ""Right Type-C Port 1"" |
| 221 | register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| 222 | register "group" = "ACPI_PLD_GROUP(2, 1)" |
| 223 | device usb 2.1 on end |
| 224 | end |
| 225 | chip drivers/usb/acpi |
| 226 | register "desc" = ""Left Type-A Port"" |
| 227 | register "type" = "UPC_TYPE_A" |
| 228 | register "group" = "ACPI_PLD_GROUP(1, 2)" |
| 229 | device usb 2.2 on end |
| 230 | end |
| 231 | chip drivers/usb/acpi |
| 232 | register "desc" = ""Right Type-A Port 1"" |
| 233 | register "type" = "UPC_TYPE_A" |
| 234 | register "group" = "ACPI_PLD_GROUP(2, 2)" |
| 235 | device usb 2.3 on end |
| 236 | end |
| 237 | chip drivers/usb/acpi |
| 238 | register "desc" = ""WWAN"" |
| 239 | register "type" = "UPC_TYPE_INTERNAL" |
| 240 | device usb 2.5 on end |
| 241 | end |
| 242 | chip drivers/usb/acpi |
| 243 | register "desc" = ""Camera"" |
| 244 | register "type" = "UPC_TYPE_INTERNAL" |
| 245 | device usb 2.6 on end |
| 246 | end |
| 247 | chip drivers/usb/acpi |
| 248 | register "desc" = ""Bluetooth"" |
| 249 | register "type" = "UPC_TYPE_INTERNAL" |
| 250 | register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C14)" |
| 251 | device usb 2.9 on end |
| 252 | end |
| 253 | chip drivers/usb/acpi |
| 254 | register "desc" = ""Left Type-C Port"" |
| 255 | register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| 256 | register "group" = "ACPI_PLD_GROUP(1, 1)" |
| 257 | device usb 3.0 on end |
| 258 | end |
| 259 | chip drivers/usb/acpi |
| 260 | register "desc" = ""Right Type-C Port 1"" |
| 261 | register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| 262 | register "group" = "ACPI_PLD_GROUP(2, 1)" |
| 263 | device usb 3.1 on end |
| 264 | end |
| 265 | chip drivers/usb/acpi |
| 266 | register "desc" = ""Left Type-A Port"" |
| 267 | register "type" = "UPC_TYPE_USB3_A" |
| 268 | register "group" = "ACPI_PLD_GROUP(1, 2)" |
| 269 | device usb 3.2 on end |
| 270 | end |
| 271 | chip drivers/usb/acpi |
| 272 | register "desc" = ""Right Type-A Port 1"" |
| 273 | register "type" = "UPC_TYPE_USB3_A" |
| 274 | register "group" = "ACPI_PLD_GROUP(2, 2)" |
| 275 | device usb 3.3 on end |
| 276 | end |
| 277 | chip drivers/usb/acpi |
| 278 | register "desc" = ""WWAN"" |
| 279 | register "type" = "UPC_TYPE_INTERNAL" |
| 280 | device usb 3.4 on end |
| 281 | end |
| 282 | end |
| 283 | end |
| 284 | end # USB xHCI |
| 285 | device pci 14.1 off end # USB xDCI (OTG) |
| 286 | device pci 14.3 on |
| 287 | chip drivers/wifi/generic |
| 288 | register "wake" = "GPE0_PME_B0" |
| 289 | device generic 0 on end |
| 290 | end |
| 291 | end # CNVi wifi |
| 292 | device pci 14.5 on end # SDCard |
| 293 | device pci 15.0 on end # I2C #0 |
| 294 | device pci 15.1 on end # I2C #1 |
| 295 | device pci 15.2 on end # I2C #2 |
| 296 | device pci 15.3 on end # I2C #3 |
| 297 | device pci 16.0 on end # Management Engine Interface 1 |
| 298 | device pci 16.1 off end # Management Engine Interface 2 |
| 299 | device pci 16.2 off end # Management Engine IDE-R |
| 300 | device pci 16.3 off end # Management Engine KT Redirection |
| 301 | device pci 16.4 off end # Management Engine Interface 3 |
| 302 | device pci 16.5 off end # Management Engine Interface 4 |
| 303 | device pci 17.0 on end # SATA |
| 304 | device pci 19.0 on end # I2C #4 |
| 305 | device pci 19.1 off end # I2C #5 |
| 306 | device pci 19.2 off end # UART #2 |
| 307 | device pci 1a.0 off end # eMMC |
| 308 | device pci 1c.0 off end # PCI Express Port 1 (USB) |
| 309 | device pci 1c.1 off end # PCI Express Port 2 (USB) |
| 310 | device pci 1c.2 off end # PCI Express Port 3 (USB) |
| 311 | device pci 1c.3 off end # PCI Express Port 4 (USB) |
| 312 | device pci 1c.4 off end # PCI Express Port 5 (USB) |
| 313 | device pci 1c.5 off end # PCI Express Port 6 |
| 314 | device pci 1c.6 off end # PCI Express Port 7 |
| 315 | device pci 1c.7 off end # PCI Express Port 8 |
| 316 | device pci 1d.0 on # PCI Express Port 9 (X4 NVME) |
| 317 | register "PcieRpSlotImplemented[8]" = "1" |
| 318 | end |
| 319 | device pci 1d.1 off end # PCI Express Port 10 |
| 320 | device pci 1d.2 off end # PCI Express Port 11 |
| 321 | device pci 1d.3 off end # PCI Express Port 12 |
| 322 | device pci 1d.4 off end # PCI Express port 13 |
| 323 | device pci 1d.5 on |
| 324 | chip drivers/wifi/generic |
| 325 | register "wake" = "GPE0_DW1_01" |
Matt DeVillier | 6c705e7 | 2023-11-01 15:52:03 -0500 | [diff] [blame^] | 326 | device generic 0 on end |
Matt DeVillier | 45b1da3 | 2022-09-07 17:21:01 -0500 | [diff] [blame] | 327 | end |
| 328 | register "PcieRpSlotImplemented[13]" = "1" |
| 329 | end # PCI Express Port 14 (x4) |
| 330 | device pci 1e.0 on end # UART #0 |
| 331 | device pci 1e.1 off end # UART #1 |
| 332 | device pci 1e.2 on |
| 333 | chip drivers/spi/acpi |
| 334 | register "hid" = "ACPI_DT_NAMESPACE_HID" |
| 335 | register "compat_string" = ""google,cr50"" |
| 336 | register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C21_IRQ)" |
| 337 | device spi 0 on end |
| 338 | end |
| 339 | end # GSPI #0 |
| 340 | device pci 1e.3 on end # GSPI #1 |
| 341 | device pci 1f.0 on |
| 342 | chip ec/google/chromeec |
| 343 | device pnp 0c09.0 on end |
| 344 | end |
| 345 | end # eSPI Interface |
| 346 | device pci 1f.1 on end # P2SB |
| 347 | device pci 1f.2 hidden end # Power Management Controller |
Matt DeVillier | 1d87638 | 2023-01-17 12:25:45 -0600 | [diff] [blame] | 348 | device pci 1f.3 on |
| 349 | chip drivers/sof |
| 350 | register "jack_tplg" = "rt5682" |
| 351 | device generic 0 on end |
| 352 | end |
| 353 | end # Intel HDA |
Matt DeVillier | 45b1da3 | 2022-09-07 17:21:01 -0500 | [diff] [blame] | 354 | device pci 1f.4 on end # SMBus |
| 355 | device pci 1f.5 on end # PCH SPI |
| 356 | device pci 1f.6 off end # GbE |
| 357 | end |
| 358 | end |