Angel Pons | f23ae0b | 2020-04-02 23:48:12 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Stefan Reinauer | c7757f2 | 2009-04-30 10:14:22 +0000 | [diff] [blame] | 2 | |
Stefan Reinauer | 00a889c | 2008-10-29 04:48:44 +0000 | [diff] [blame] | 3 | #include <console/console.h> |
| 4 | #include <device/device.h> |
Stefan Reinauer | 00a889c | 2008-10-29 04:48:44 +0000 | [diff] [blame] | 5 | #include <cpu/cpu.h> |
Stefan Reinauer | 00a889c | 2008-10-29 04:48:44 +0000 | [diff] [blame] | 6 | #include <cpu/x86/msr.h> |
Stefan Reinauer | 2a27b20 | 2010-12-11 22:14:44 +0000 | [diff] [blame] | 7 | #include <cpu/intel/speedstep.h> |
Stefan Reinauer | 00a889c | 2008-10-29 04:48:44 +0000 | [diff] [blame] | 8 | #include <cpu/x86/cache.h> |
Uwe Hermann | aac8f66 | 2010-09-29 09:54:16 +0000 | [diff] [blame] | 9 | #include <cpu/x86/name.h> |
Stefan Reinauer | 45cc550 | 2009-03-06 19:54:15 +0000 | [diff] [blame] | 10 | |
Stefan Reinauer | 4da810b | 2009-07-21 21:41:42 +0000 | [diff] [blame] | 11 | #define HIGHEST_CLEVEL 3 |
Stefan Reinauer | 45cc550 | 2009-03-06 19:54:15 +0000 | [diff] [blame] | 12 | static void configure_c_states(void) |
| 13 | { |
| 14 | msr_t msr; |
| 15 | |
Elyes HAOUAS | 4e6b790 | 2018-10-02 08:44:47 +0200 | [diff] [blame] | 16 | msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL); |
Stefan Reinauer | 45cc550 | 2009-03-06 19:54:15 +0000 | [diff] [blame] | 17 | msr.lo |= (1 << 15); // config lock until next reset |
| 18 | msr.lo |= (1 << 14); // Deeper Sleep |
Paul Menzel | 7129ccb | 2017-02-27 01:01:55 +0100 | [diff] [blame] | 19 | msr.lo |= (1 << 10); // Enable I/O MWAIT redirection for C-States |
| 20 | msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk |
| 21 | msr.lo |= (1 << 3); // dynamic L2 |
Stefan Reinauer | 45cc550 | 2009-03-06 19:54:15 +0000 | [diff] [blame] | 22 | |
Elyes HAOUAS | 2765a89 | 2016-09-01 19:44:56 +0200 | [diff] [blame] | 23 | /* Number of supported C-States */ |
Stefan Reinauer | 4da810b | 2009-07-21 21:41:42 +0000 | [diff] [blame] | 24 | msr.lo &= ~7; |
| 25 | msr.lo |= HIGHEST_CLEVEL; // support at most C3 |
| 26 | |
Elyes HAOUAS | 4e6b790 | 2018-10-02 08:44:47 +0200 | [diff] [blame] | 27 | wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); |
Stefan Reinauer | 45cc550 | 2009-03-06 19:54:15 +0000 | [diff] [blame] | 28 | |
Paul Menzel | 7129ccb | 2017-02-27 01:01:55 +0100 | [diff] [blame] | 29 | /* Set Processor MWAIT IO BASE (P_BLK) */ |
Stefan Reinauer | 45cc550 | 2009-03-06 19:54:15 +0000 | [diff] [blame] | 30 | msr.hi = 0; |
Lee Leahy | cdc5048 | 2017-03-15 18:26:18 -0700 | [diff] [blame] | 31 | msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) |
| 32 | << 16); |
Patrick Georgi | 644e83b | 2013-02-09 15:35:30 +0100 | [diff] [blame] | 33 | wrmsr(MSR_PMG_IO_BASE_ADDR, msr); |
Stefan Reinauer | 45cc550 | 2009-03-06 19:54:15 +0000 | [diff] [blame] | 34 | |
Stefan Reinauer | 4da810b | 2009-07-21 21:41:42 +0000 | [diff] [blame] | 35 | /* Set C_LVL controls and IO Capture Address */ |
Stefan Reinauer | 45cc550 | 2009-03-06 19:54:15 +0000 | [diff] [blame] | 36 | msr.hi = 0; |
Lee Leahy | cdc5048 | 2017-03-15 18:26:18 -0700 | [diff] [blame] | 37 | // -2 because LVL0+1 aren't counted |
| 38 | msr.lo = (PMB0_BASE + 4) | ((HIGHEST_CLEVEL - 2) << 16); |
Patrick Georgi | 644e83b | 2013-02-09 15:35:30 +0100 | [diff] [blame] | 39 | wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr); |
Stefan Reinauer | 45cc550 | 2009-03-06 19:54:15 +0000 | [diff] [blame] | 40 | } |
| 41 | |
Sven Schnelle | edac28c | 2012-06-19 18:00:01 +0200 | [diff] [blame] | 42 | #define IA32_PECI_CTL 0x5a0 |
| 43 | |
Stefan Reinauer | 45cc550 | 2009-03-06 19:54:15 +0000 | [diff] [blame] | 44 | static void configure_misc(void) |
| 45 | { |
| 46 | msr_t msr; |
| 47 | |
| 48 | msr = rdmsr(IA32_MISC_ENABLE); |
Lee Leahy | 7b5f12b9 | 2017-03-15 17:16:59 -0700 | [diff] [blame] | 49 | msr.lo |= (1 << 3); /* TM1 enable */ |
Stefan Reinauer | 45cc550 | 2009-03-06 19:54:15 +0000 | [diff] [blame] | 50 | msr.lo |= (1 << 13); /* TM2 enable */ |
| 51 | msr.lo |= (1 << 17); /* Bidirectional PROCHOT# */ |
| 52 | |
| 53 | msr.lo |= (1 << 10); /* FERR# multiplexing */ |
| 54 | |
| 55 | // TODO: Only if IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1 |
| 56 | msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ |
| 57 | |
| 58 | /* Enable C2E */ |
| 59 | msr.lo |= (1 << 26); |
| 60 | |
| 61 | /* Enable C4E */ |
| 62 | /* TODO This should only be done on mobile CPUs, see cpuid 5 */ |
| 63 | msr.hi |= (1 << (32 - 32)); // C4E |
| 64 | msr.hi |= (1 << (33 - 32)); // Hard C4E |
| 65 | |
| 66 | /* Enable EMTTM. */ |
| 67 | /* NOTE: We leave the EMTTM_CR_TABLE0-5 at their default values */ |
| 68 | msr.hi |= (1 << (36 - 32)); |
| 69 | |
| 70 | wrmsr(IA32_MISC_ENABLE, msr); |
| 71 | |
| 72 | msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */ |
| 73 | wrmsr(IA32_MISC_ENABLE, msr); |
Patrick Georgi | ac624a6 | 2011-08-09 08:52:14 +0200 | [diff] [blame] | 74 | |
| 75 | // set maximum CPU speed |
Elyes HAOUAS | 242ea84 | 2017-11-23 21:23:44 +0100 | [diff] [blame] | 76 | msr = rdmsr(IA32_PERF_STATUS); |
Lee Leahy | 9d62e7e | 2017-03-15 17:40:50 -0700 | [diff] [blame] | 77 | int busratio_max = (msr.hi >> (40-32)) & 0x1f; |
Patrick Georgi | ac624a6 | 2011-08-09 08:52:14 +0200 | [diff] [blame] | 78 | |
| 79 | msr = rdmsr(IA32_PLATFORM_ID); |
Lee Leahy | 9d62e7e | 2017-03-15 17:40:50 -0700 | [diff] [blame] | 80 | int vid_max = msr.lo & 0x3f; |
Patrick Georgi | ac624a6 | 2011-08-09 08:52:14 +0200 | [diff] [blame] | 81 | |
| 82 | msr.lo &= ~0xffff; |
| 83 | msr.lo |= busratio_max << 8; |
| 84 | msr.lo |= vid_max; |
| 85 | |
| 86 | wrmsr(IA32_PERF_CTL, msr); |
Sven Schnelle | edac28c | 2012-06-19 18:00:01 +0200 | [diff] [blame] | 87 | |
| 88 | /* Enable PECI */ |
| 89 | msr = rdmsr(IA32_PECI_CTL); |
| 90 | msr.lo |= 1; |
| 91 | wrmsr(IA32_PECI_CTL, msr); |
Stefan Reinauer | 45cc550 | 2009-03-06 19:54:15 +0000 | [diff] [blame] | 92 | } |
| 93 | |
| 94 | #define PIC_SENS_CFG 0x1aa |
| 95 | static void configure_pic_thermal_sensors(void) |
| 96 | { |
| 97 | msr_t msr; |
| 98 | |
| 99 | msr = rdmsr(PIC_SENS_CFG); |
| 100 | |
| 101 | msr.lo |= (1 << 21); // inter-core lock TM1 |
| 102 | msr.lo |= (1 << 4); // Enable bypass filter |
| 103 | |
| 104 | wrmsr(PIC_SENS_CFG, msr); |
| 105 | } |
| 106 | |
Edward O'Callaghan | 2c9d2cf | 2014-10-27 23:29:29 +1100 | [diff] [blame] | 107 | static void model_6fx_init(struct device *cpu) |
Stefan Reinauer | 00a889c | 2008-10-29 04:48:44 +0000 | [diff] [blame] | 108 | { |
| 109 | char processor_name[49]; |
| 110 | |
| 111 | /* Turn on caching if we haven't already */ |
Felix Held | 10796d8 | 2021-10-25 17:52:49 +0200 | [diff] [blame] | 112 | enable_cache(); |
Stefan Reinauer | 00a889c | 2008-10-29 04:48:44 +0000 | [diff] [blame] | 113 | |
Stefan Reinauer | 00a889c | 2008-10-29 04:48:44 +0000 | [diff] [blame] | 114 | /* Print processor name */ |
| 115 | fill_processor_name(processor_name); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 116 | printk(BIOS_INFO, "CPU: %s.\n", processor_name); |
Stefan Reinauer | 00a889c | 2008-10-29 04:48:44 +0000 | [diff] [blame] | 117 | |
Stefan Reinauer | 4da810b | 2009-07-21 21:41:42 +0000 | [diff] [blame] | 118 | /* Setup Page Attribute Tables (PAT) */ |
| 119 | // TODO set up PAT |
| 120 | |
Stefan Reinauer | 45cc550 | 2009-03-06 19:54:15 +0000 | [diff] [blame] | 121 | /* Configure C States */ |
| 122 | configure_c_states(); |
| 123 | |
| 124 | /* Configure Enhanced SpeedStep and Thermal Sensors */ |
| 125 | configure_misc(); |
| 126 | |
| 127 | /* PIC thermal sensor control */ |
| 128 | configure_pic_thermal_sensors(); |
Stefan Reinauer | 00a889c | 2008-10-29 04:48:44 +0000 | [diff] [blame] | 129 | } |
| 130 | |
| 131 | static struct device_operations cpu_dev_ops = { |
Stefan Reinauer | 45cc550 | 2009-03-06 19:54:15 +0000 | [diff] [blame] | 132 | .init = model_6fx_init, |
Stefan Reinauer | 00a889c | 2008-10-29 04:48:44 +0000 | [diff] [blame] | 133 | }; |
| 134 | |
Jonathan Neuschäfer | 8f06ce3 | 2017-11-20 01:56:44 +0100 | [diff] [blame] | 135 | static const struct cpu_device_id cpu_table[] = { |
Stefan Reinauer | 00a889c | 2008-10-29 04:48:44 +0000 | [diff] [blame] | 136 | { X86_VENDOR_INTEL, 0x06f0 }, /* Intel Core 2 Solo/Core Duo */ |
Stefan Reinauer | c7757f2 | 2009-04-30 10:14:22 +0000 | [diff] [blame] | 137 | { X86_VENDOR_INTEL, 0x06f2 }, /* Intel Core 2 Solo/Core Duo */ |
Stefan Reinauer | 00a889c | 2008-10-29 04:48:44 +0000 | [diff] [blame] | 138 | { X86_VENDOR_INTEL, 0x06f6 }, /* Intel Core 2 Solo/Core Duo */ |
Stefan Reinauer | c7757f2 | 2009-04-30 10:14:22 +0000 | [diff] [blame] | 139 | { X86_VENDOR_INTEL, 0x06f7 }, /* Intel Core 2 Solo/Core Duo */ |
| 140 | { X86_VENDOR_INTEL, 0x06fa }, /* Intel Core 2 Solo/Core Duo */ |
| 141 | { X86_VENDOR_INTEL, 0x06fb }, /* Intel Core 2 Solo/Core Duo */ |
| 142 | { X86_VENDOR_INTEL, 0x06fd }, /* Intel Core 2 Solo/Core Duo */ |
Arthur Heymans | 3f2d6c0 | 2017-01-08 21:14:46 +0100 | [diff] [blame] | 143 | { X86_VENDOR_INTEL, 0x10661 }, /* Intel Core 2 Celeron Conroe-L */ |
Stefan Reinauer | 00a889c | 2008-10-29 04:48:44 +0000 | [diff] [blame] | 144 | { 0, 0 }, |
| 145 | }; |
| 146 | |
| 147 | static const struct cpu_driver driver __cpu_driver = { |
| 148 | .ops = &cpu_dev_ops, |
| 149 | .id_table = cpu_table, |
| 150 | }; |