Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * SATA Controller family specific service procedure |
| 6 | * |
| 7 | * |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: FCH |
| 12 | * @e \$Revision: 86583 $ @e \$Date: 2013-01-23 12:31:06 -0600 (Wed, 23 Jan 2013) $ |
| 13 | * |
| 14 | */ |
| 15 | |
| 16 | /* |
| 17 | ***************************************************************************** |
| 18 | * |
| 19 | * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc. |
| 20 | * All rights reserved. |
| 21 | * |
| 22 | * Redistribution and use in source and binary forms, with or without |
| 23 | * modification, are permitted provided that the following conditions are met: |
| 24 | * * Redistributions of source code must retain the above copyright |
| 25 | * notice, this list of conditions and the following disclaimer. |
| 26 | * * Redistributions in binary form must reproduce the above copyright |
| 27 | * notice, this list of conditions and the following disclaimer in the |
| 28 | * documentation and/or other materials provided with the distribution. |
| 29 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 30 | * its contributors may be used to endorse or promote products derived |
| 31 | * from this software without specific prior written permission. |
| 32 | * |
| 33 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 34 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 35 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 36 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 37 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 38 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 39 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 40 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 41 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 42 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 43 | * *************************************************************************** |
| 44 | */ |
| 45 | |
| 46 | |
| 47 | /*---------------------------------------------------------------------------------------- |
| 48 | * M O D U L E S U S E D |
| 49 | *---------------------------------------------------------------------------------------- |
| 50 | */ |
| 51 | #include "FchPlatform.h" |
| 52 | #include "Filecode.h" |
| 53 | #define FILECODE PROC_FCH_SATA_FAMILY_YANGTZE_YANGTZESATAENVSERVICE_FILECODE |
| 54 | |
| 55 | |
| 56 | SATA_PHY_SETTING SataPhyTable[] = |
| 57 | { |
| 58 | {0x0030, 0x0040F407}, |
| 59 | {0x0120, 0x00403204}, |
| 60 | {0x0110, 0x00403103}, |
| 61 | |
| 62 | {0x0031, 0x0040F407}, |
| 63 | {0x0121, 0x00403204}, |
| 64 | {0x0111, 0x00403103}, |
| 65 | |
| 66 | }; |
| 67 | |
| 68 | /*---------------------------------------------------------------------------------------- |
| 69 | * D E F I N I T I O N S A N D M A C R O S |
| 70 | *---------------------------------------------------------------------------------------- |
| 71 | */ |
| 72 | // |
| 73 | // Local Routine |
| 74 | // |
| 75 | VOID FchSataCombineControlDataByte (IN UINT8 *ControlReg); |
| 76 | VOID FchSataCombineControlDataWord (IN UINT16 *ControlReg); |
| 77 | |
| 78 | |
| 79 | /** |
| 80 | * FchInitEnvProgramSataPciRegs - Sata Pci Configuration Space |
| 81 | * register setting |
| 82 | * |
| 83 | * |
| 84 | * @param[in] FchDataPtr Fch configuration structure pointer. |
| 85 | * |
| 86 | */ |
| 87 | VOID |
| 88 | FchInitEnvProgramSataPciRegs ( |
| 89 | IN VOID *FchDataPtr |
| 90 | ) |
| 91 | { |
| 92 | UINT8 *PortRegByte; |
| 93 | UINT16 *PortRegWord; |
| 94 | FCH_DATA_BLOCK *LocalCfgPtr; |
| 95 | AMD_CONFIG_PARAMS *StdHeader; |
| 96 | |
| 97 | LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; |
| 98 | StdHeader = LocalCfgPtr->StdHeader; |
| 99 | // |
| 100 | //Caculate SataPortReg for SATA_ESP_PORT |
| 101 | // |
| 102 | PortRegByte = &(LocalCfgPtr->Sata.SataEspPort.SataPortReg); |
| 103 | FchSataCombineControlDataByte (PortRegByte); |
| 104 | PortRegByte = &(LocalCfgPtr->Sata.SataPortPower.SataPortReg); |
| 105 | FchSataCombineControlDataByte (PortRegByte); |
| 106 | PortRegWord = &(LocalCfgPtr->Sata.SataPortMd.SataPortMode); |
| 107 | FchSataCombineControlDataWord (PortRegWord); |
| 108 | PortRegByte = &(LocalCfgPtr->Sata.SataHotRemovalEnhPort.SataPortReg); |
| 109 | FchSataCombineControlDataByte (PortRegByte); |
| 110 | |
| 111 | // |
| 112 | // Set Sata PCI Configuration Space Write enable |
| 113 | // |
| 114 | SataEnableWriteAccess (StdHeader); |
| 115 | |
| 116 | // * |
| 117 | // Enables the SATA watchdog timer register prior to the SATA BIOS post |
| 118 | // |
| 119 | RwPci (((SATA_BUS_DEV_FUN << 16) + 0x44), AccessWidth8, 0xff, BIT0, StdHeader); |
| 120 | |
| 121 | // * |
| 122 | // SATA PCI Watchdog timer setting |
| 123 | // Set timer out to 0x20 to fix IDE to SATA Bridge dropping drive issue. |
| 124 | // |
| 125 | RwPci (((SATA_BUS_DEV_FUN << 16) + 0x44 + 2), AccessWidth8, 0, 0x20, StdHeader); |
| 126 | |
| 127 | // |
| 128 | // BIT4: Enable fast boot (SpeedupXPBoot) |
| 129 | // |
| 130 | RwPci (((SATA_BUS_DEV_FUN << 16) + 0x040), AccessWidth8, 0xef, 0, StdHeader); |
| 131 | |
| 132 | RwPci (((SATA_BUS_DEV_FUN << 16) + 0x48 + 3), AccessWidth8, 0xff, BIT7, StdHeader); |
| 133 | |
| 134 | // |
| 135 | // Unused SATA Ports Disabled |
| 136 | // |
| 137 | RwPci (((SATA_BUS_DEV_FUN << 16) + 0x040 + 2), AccessWidth8, 0, LocalCfgPtr->Sata.SataPortPower.SataPortReg, StdHeader); |
| 138 | |
| 139 | RwPci (((SATA_BUS_DEV_FUN << 16) + 0x084), AccessWidth32, (UINT32) (~ (0x01 << 31)), (UINT32) (0x00 << 31), StdHeader); |
| 140 | } |
| 141 | |
| 142 | /** |
| 143 | * FchSataCombineControlDataByte - Combine port control options |
| 144 | * to one control byte. |
| 145 | * |
| 146 | * |
| 147 | * @param[in] *ControlReg - Data pointer for control byte. |
| 148 | * |
| 149 | */ |
| 150 | VOID |
| 151 | FchSataCombineControlDataByte ( |
| 152 | IN UINT8 *ControlReg |
| 153 | ) |
| 154 | { |
| 155 | UINT8 Index; |
| 156 | UINT8 PortControl; |
| 157 | |
| 158 | *ControlReg = 0; |
| 159 | for ( Index = 0; Index < 8; Index++ ) { |
| 160 | PortControl = *( ControlReg + 1 + Index ); |
| 161 | *ControlReg |= PortControl << Index; |
| 162 | } |
| 163 | } |
| 164 | /** |
| 165 | * FchSataCombineControlDataWord - Combine port control options |
| 166 | * to one control Word. |
| 167 | * |
| 168 | * |
| 169 | * @param[in] *ControlReg - Data pointer for control byte. |
| 170 | * |
| 171 | */ |
| 172 | VOID |
| 173 | FchSataCombineControlDataWord ( |
| 174 | IN UINT16 *ControlReg |
| 175 | ) |
| 176 | { |
| 177 | UINT8 Index; |
| 178 | UINT8 PortControl; |
| 179 | |
| 180 | *ControlReg = 0; |
| 181 | for ( Index = 0; Index < 8; Index++ ) { |
| 182 | PortControl = *( (UINT8 *)ControlReg + 2 + Index ); |
| 183 | *ControlReg |= PortControl << (Index * 2); |
| 184 | } |
| 185 | } |
| 186 | |
| 187 | /** |
| 188 | * FchProgramSataPhy - Program Sata PHY registers |
| 189 | * |
| 190 | * @param[in] StdHeader |
| 191 | * |
| 192 | */ |
| 193 | VOID |
| 194 | FchProgramSataPhy ( |
| 195 | IN AMD_CONFIG_PARAMS *StdHeader |
| 196 | ) |
| 197 | { |
| 198 | SATA_PHY_SETTING *PhyTablePtr; |
| 199 | UINT16 Index; |
| 200 | UINT32 SquelchValue[2]; |
| 201 | UINT8 PortNum; |
| 202 | |
| 203 | PhyTablePtr = &SataPhyTable[0]; |
| 204 | |
Patrick Georgi | 6b688f5 | 2021-02-12 13:49:11 +0100 | [diff] [blame^] | 205 | for (Index = 0; Index < ARRAY_SIZE(SataPhyTable); Index++) { |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 206 | RwPci ((SATA_BUS_DEV_FUN << 16) + 0x080, AccessWidth16, 0xFC00, PhyTablePtr->PhyCoreControlWord, StdHeader); |
| 207 | RwPci ((SATA_BUS_DEV_FUN << 16) + 0x98, AccessWidth32, 0x00, PhyTablePtr->PhyFineTuneDword, StdHeader); |
| 208 | ++PhyTablePtr; |
| 209 | } |
| 210 | SquelchValue[0] = (0x07 << 9); |
| 211 | SquelchValue[1] = (0x07 << 9); |
| 212 | for (PortNum = 0; PortNum < 2; PortNum ++) { |
WANG Siyuan | 7b6d412 | 2013-07-31 16:55:26 +0800 | [diff] [blame] | 213 | RwPci ((SATA_BUS_DEV_FUN << 16) + 0x080, AccessWidth16, 0x00, ( 0x30 + PortNum), StdHeader); |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 214 | RwPci ((SATA_BUS_DEV_FUN << 16) + 0x09C, AccessWidth32, (UINT32) (~(0x7 << 9)), SquelchValue[PortNum], StdHeader); |
| 215 | RwPci ((SATA_BUS_DEV_FUN << 16) + 0x09C, AccessWidth32, (UINT32) (~(0x7 << 13)), (UINT32) (0x0 << 13), StdHeader); |
WANG Siyuan | 7b6d412 | 2013-07-31 16:55:26 +0800 | [diff] [blame] | 216 | RwPci ((SATA_BUS_DEV_FUN << 16) + 0x080, AccessWidth16, 0x00, ( 0x20 + PortNum), StdHeader); |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 217 | RwPci ((SATA_BUS_DEV_FUN << 16) + 0x09C, AccessWidth32, (UINT32) (~(0x7 << 9)), SquelchValue[PortNum], StdHeader); |
WANG Siyuan | 7b6d412 | 2013-07-31 16:55:26 +0800 | [diff] [blame] | 218 | RwPci ((SATA_BUS_DEV_FUN << 16) + 0x080, AccessWidth16, 0x00, ( 0x10 + PortNum), StdHeader); |
Siyuan Wang | affe85f | 2013-07-25 15:14:15 +0800 | [diff] [blame] | 219 | RwPci ((SATA_BUS_DEV_FUN << 16) + 0x09C, AccessWidth32, (UINT32) (~(0x7 << 9)), SquelchValue[PortNum], StdHeader); |
| 220 | RwPci ((SATA_BUS_DEV_FUN << 16) + 0x080, AccessWidth16, 0x00, 0x010, StdHeader); |
| 221 | } |
| 222 | } |
| 223 | |
| 224 | |