zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * Config Fch Pcib controller |
| 6 | * |
| 7 | * Init Pcib Controller features. |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: FCH |
| 12 | * @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $ |
| 13 | * |
| 14 | */ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 18 | * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
| 20 | * |
| 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
| 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
| 30 | * from this software without specific prior written permission. |
| 31 | * |
| 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 42 | **************************************************************************** |
| 43 | */ |
| 44 | #include "FchPlatform.h" |
| 45 | #define FILECODE PROC_FCH_PCIB_PCIBENV_FILECODE |
| 46 | |
| 47 | /** |
| 48 | * FchInitEnvPcibPciTable - PCI device registers initial during |
| 49 | * early POST. |
| 50 | * |
| 51 | */ |
| 52 | REG8_MASK FchInitEnvPcibPciTable[] = |
| 53 | { |
| 54 | // |
| 55 | // PCIB Bridge (Bus 0, Dev 20, Func 4) |
| 56 | // |
| 57 | {0x00, PCIB_BUS_DEV_FUN, 0}, |
| 58 | {FCH_PCIB_REG40, 0xFF, BIT5}, /// PCI-bridge Subtractive Decode |
| 59 | {FCH_PCIB_REG4B, 0xFF, BIT7}, /// |
| 60 | {0x66 , 0xFF, BIT4}, /// Enabling One-Prefetch-Channel Mode, PCIB_PCI_config 0x64 [20] |
| 61 | {0x65 , 0xFF, BIT7}, /// proper operation of CLKRUN#. |
| 62 | {FCH_PCIB_REG0D, 0x00, 0x40}, /// Setting Latency Timers to 0x40, Enables the PCIB to retain ownership |
| 63 | {FCH_PCIB_REG1B, 0x00, 0x40}, /// of the bus on the Primary side and on the Secondary side when GNT# is deasserted. |
| 64 | {FCH_PCIB_REG66 + 1, 0xFF, BIT1}, /// Enable PCI bus GNT3#.. |
| 65 | {0xFF, 0xFF, 0xFF}, |
| 66 | }; |
| 67 | |
| 68 | /** |
| 69 | * FchInitEnvPcib - Config Pcib controller before PCI emulation |
| 70 | * |
| 71 | * |
| 72 | * |
| 73 | * @param[in] FchDataPtr Fch configuration structure pointer. |
| 74 | * |
| 75 | */ |
| 76 | VOID |
| 77 | FchInitEnvPcib ( |
| 78 | IN VOID *FchDataPtr |
| 79 | ) |
| 80 | { |
| 81 | UINT8 VerbPciClks; |
| 82 | FCH_DATA_BLOCK *LocalCfgPtr; |
| 83 | AMD_CONFIG_PARAMS *StdHeader; |
| 84 | |
| 85 | LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; |
| 86 | StdHeader = LocalCfgPtr->StdHeader; |
| 87 | |
| 88 | // |
| 89 | //Early post initialization of pci config space |
| 90 | // |
Patrick Georgi | 6b688f5 | 2021-02-12 13:49:11 +0100 | [diff] [blame^] | 91 | ProgramPciByteTable ((REG8_MASK*) (&FchInitEnvPcibPciTable[0]), |
| 92 | ARRAY_SIZE(FchInitEnvPcibPciTable), StdHeader); |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 93 | |
| 94 | // |
| 95 | //Disable or Enable PCI Clks based on input |
| 96 | // |
| 97 | VerbPciClks = ((LocalCfgPtr->Pcib.PciClks & 0x0F) << 2); |
| 98 | RwPci ((PCIB_BUS_DEV_FUN << 16) + FCH_PCIB_REG42, AccessWidth8, (UINT32)~(BIT5 + BIT4 + BIT3 + BIT2), VerbPciClks, StdHeader); |
| 99 | VerbPciClks = ((LocalCfgPtr->Pcib.PciClks & 0x10) >> 4); |
| 100 | RwPci ((PCIB_BUS_DEV_FUN << 16) + 0x4A , AccessWidth8, (UINT32)~BIT0, VerbPciClks, StdHeader); |
| 101 | // |
| 102 | // PCIB MSI |
| 103 | // |
| 104 | if (LocalCfgPtr->Pcib.PcibMsiEnable) { |
| 105 | RwPci ((PCIB_BUS_DEV_FUN << 16) + 0x40 , AccessWidth8, (UINT32)~BIT3, BIT3, StdHeader); |
| 106 | } |
| 107 | } |
| 108 | |