Rizwan Qureshi | ae6a4b6 | 2017-04-26 21:06:35 +0530 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Subrata Banik | 7d8c0c2 | 2018-09-27 19:27:39 +0530 | [diff] [blame] | 4 | * Copyright 2017-2018 Intel Corporation. |
Rizwan Qureshi | ae6a4b6 | 2017-04-26 21:06:35 +0530 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 16 | #include <device/pci_ops.h> |
Subrata Banik | e62836b | 2018-05-07 16:27:51 +0530 | [diff] [blame] | 17 | #include <console/console.h> |
| 18 | #include <device/device.h> |
| 19 | #include <device/i2c_simple.h> |
Rizwan Qureshi | ae6a4b6 | 2017-04-26 21:06:35 +0530 | [diff] [blame] | 20 | #include <device/pci.h> |
| 21 | #include <device/pci_def.h> |
| 22 | #include <device/pci_ids.h> |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 23 | #include <drivers/i2c/designware/dw_i2c.h> |
Kyösti Mälkki | 32d47eb | 2019-09-28 00:00:30 +0300 | [diff] [blame] | 24 | #include <intelblocks/cfg.h> |
Subrata Banik | e62836b | 2018-05-07 16:27:51 +0530 | [diff] [blame] | 25 | #include <intelblocks/lpss.h> |
| 26 | #include <soc/iomap.h> |
| 27 | #include <soc/pci_devs.h> |
| 28 | |
| 29 | int dw_i2c_soc_dev_to_bus(struct device *dev) |
| 30 | { |
| 31 | pci_devfn_t devfn = dev->path.pci.devfn; |
| 32 | return dw_i2c_soc_devfn_to_bus(devfn); |
| 33 | } |
| 34 | |
| 35 | /* Getting I2C bus configuration from devicetree config */ |
| 36 | const struct dw_i2c_bus_config *dw_i2c_get_soc_cfg(unsigned int bus) |
| 37 | { |
| 38 | const struct soc_intel_common_config *common_config; |
| 39 | common_config = chip_get_common_soc_structure(); |
| 40 | |
| 41 | return &common_config->i2c[bus]; |
| 42 | } |
| 43 | |
| 44 | /* Get base address for early init of I2C controllers. */ |
| 45 | uintptr_t dw_i2c_get_soc_early_base(unsigned int bus) |
| 46 | { |
| 47 | return EARLY_I2C_BASE(bus); |
| 48 | } |
| 49 | |
Subrata Banik | 42c44c2 | 2019-05-15 20:27:04 +0530 | [diff] [blame] | 50 | #if !ENV_PAYLOAD_LOADER |
Subrata Banik | e62836b | 2018-05-07 16:27:51 +0530 | [diff] [blame] | 51 | static int lpss_i2c_early_init_bus(unsigned int bus) |
| 52 | { |
| 53 | const struct dw_i2c_bus_config *config; |
| 54 | const struct device *tree_dev; |
| 55 | pci_devfn_t dev; |
| 56 | int devfn; |
| 57 | uintptr_t base; |
| 58 | |
| 59 | /* Find the PCI device for this bus controller */ |
| 60 | devfn = dw_i2c_soc_bus_to_devfn(bus); |
| 61 | if (devfn < 0) { |
| 62 | printk(BIOS_ERR, "I2C%u device not found\n", bus); |
| 63 | return -1; |
| 64 | } |
| 65 | |
| 66 | /* Look up the controller device in the devicetree */ |
| 67 | dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); |
Kyösti Mälkki | e737755 | 2018-06-21 16:20:55 +0300 | [diff] [blame] | 68 | tree_dev = pcidev_path_on_root(devfn); |
Subrata Banik | e62836b | 2018-05-07 16:27:51 +0530 | [diff] [blame] | 69 | if (!tree_dev || !tree_dev->enabled) { |
| 70 | printk(BIOS_ERR, "I2C%u device not enabled\n", bus); |
| 71 | return -1; |
| 72 | } |
| 73 | |
| 74 | /* Skip if not enabled for early init */ |
| 75 | config = dw_i2c_get_soc_cfg(bus); |
| 76 | if (!config || !config->early_init) { |
| 77 | printk(BIOS_DEBUG, "I2C%u not enabled for early init\n", bus); |
| 78 | return -1; |
| 79 | } |
| 80 | |
| 81 | /* Prepare early base address for access before memory */ |
| 82 | base = dw_i2c_get_soc_early_base(bus); |
| 83 | pci_write_config32(dev, PCI_BASE_ADDRESS_0, base); |
| 84 | pci_write_config32(dev, PCI_COMMAND, |
| 85 | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); |
| 86 | |
| 87 | /* Take device out of reset */ |
| 88 | lpss_reset_release(base); |
| 89 | |
Aamir Bohra | f5202a6 | 2019-07-12 14:37:55 +0530 | [diff] [blame] | 90 | /* Ensure controller is in D0 state */ |
| 91 | lpss_set_power_state(tree_dev, STATE_D0); |
| 92 | |
Subrata Banik | e62836b | 2018-05-07 16:27:51 +0530 | [diff] [blame] | 93 | /* Initialize the controller */ |
| 94 | if (dw_i2c_init(bus, config) < 0) { |
| 95 | printk(BIOS_ERR, "I2C%u failed to initialize\n", bus); |
| 96 | return -1; |
| 97 | } |
| 98 | |
| 99 | return 0; |
| 100 | } |
| 101 | |
| 102 | uintptr_t dw_i2c_base_address(unsigned int bus) |
| 103 | { |
| 104 | int devfn; |
| 105 | pci_devfn_t dev; |
| 106 | uintptr_t base; |
| 107 | |
| 108 | /* Find device+function for this controller */ |
| 109 | devfn = dw_i2c_soc_bus_to_devfn(bus); |
| 110 | if (devfn < 0) |
| 111 | return (uintptr_t)NULL; |
| 112 | |
| 113 | /* Form a PCI address for this device */ |
| 114 | dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); |
| 115 | |
| 116 | /* Read the first base address for this device */ |
| 117 | base = ALIGN_DOWN(pci_read_config32(dev, PCI_BASE_ADDRESS_0), 16); |
| 118 | |
| 119 | /* Attempt to initialize bus if base is not set yet */ |
| 120 | if (!base && !lpss_i2c_early_init_bus(bus)) |
| 121 | base = ALIGN_DOWN(pci_read_config32(dev, PCI_BASE_ADDRESS_0), |
| 122 | 16); |
| 123 | return base; |
| 124 | } |
| 125 | #else |
Rizwan Qureshi | ae6a4b6 | 2017-04-26 21:06:35 +0530 | [diff] [blame] | 126 | |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 127 | uintptr_t dw_i2c_base_address(unsigned int bus) |
Rizwan Qureshi | ae6a4b6 | 2017-04-26 21:06:35 +0530 | [diff] [blame] | 128 | { |
| 129 | int devfn; |
| 130 | struct device *dev; |
| 131 | struct resource *res; |
| 132 | |
| 133 | /* bus -> devfn */ |
Aaron Durbin | 9aee819 | 2018-01-22 20:29:25 -0700 | [diff] [blame] | 134 | devfn = dw_i2c_soc_bus_to_devfn(bus); |
Rizwan Qureshi | ae6a4b6 | 2017-04-26 21:06:35 +0530 | [diff] [blame] | 135 | |
| 136 | if (devfn < 0) |
| 137 | return (uintptr_t)NULL; |
| 138 | |
| 139 | /* devfn -> dev */ |
Kyösti Mälkki | e737755 | 2018-06-21 16:20:55 +0300 | [diff] [blame] | 140 | dev = pcidev_path_on_root(devfn); |
Furquan Shaikh | d629e433 | 2017-06-09 17:54:00 -0700 | [diff] [blame] | 141 | if (!dev || !dev->enabled) |
Rizwan Qureshi | ae6a4b6 | 2017-04-26 21:06:35 +0530 | [diff] [blame] | 142 | return (uintptr_t)NULL; |
| 143 | |
| 144 | /* dev -> bar0 */ |
| 145 | res = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 146 | if (res) |
| 147 | return res->base; |
| 148 | |
| 149 | return (uintptr_t)NULL; |
| 150 | } |
| 151 | |
Subrata Banik | 7d8c0c2 | 2018-09-27 19:27:39 +0530 | [diff] [blame] | 152 | /* |
| 153 | * This function ensures that the device is actually out of reset and |
| 154 | * its ready for initialization sequence. |
| 155 | */ |
| 156 | static void dw_i2c_device_init(struct device *dev) |
| 157 | { |
| 158 | uintptr_t base_address; |
| 159 | int bus = dw_i2c_soc_dev_to_bus(dev); |
| 160 | |
| 161 | if (bus < 0) |
| 162 | return; |
| 163 | |
| 164 | base_address = dw_i2c_base_address(bus); |
| 165 | if (!base_address) |
| 166 | return; |
| 167 | |
Aamir Bohra | f5202a6 | 2019-07-12 14:37:55 +0530 | [diff] [blame] | 168 | /* Ensure controller is in D0 state */ |
| 169 | lpss_set_power_state(dev, STATE_D0); |
| 170 | |
Subrata Banik | 7d8c0c2 | 2018-09-27 19:27:39 +0530 | [diff] [blame] | 171 | /* Take device out of reset if its not done before */ |
| 172 | if (lpss_is_controller_in_reset(base_address)) |
| 173 | lpss_reset_release(base_address); |
| 174 | |
| 175 | dw_i2c_dev_init(dev); |
| 176 | } |
| 177 | |
Rizwan Qureshi | ae6a4b6 | 2017-04-26 21:06:35 +0530 | [diff] [blame] | 178 | static struct device_operations i2c_dev_ops = { |
Elyes HAOUAS | 1d19127 | 2018-11-27 12:23:48 +0100 | [diff] [blame] | 179 | .read_resources = pci_dev_read_resources, |
| 180 | .set_resources = pci_dev_set_resources, |
| 181 | .enable_resources = pci_dev_enable_resources, |
| 182 | .scan_bus = scan_smbus, |
Aaron Durbin | b7d79cd | 2018-01-22 21:31:48 -0700 | [diff] [blame] | 183 | .ops_i2c_bus = &dw_i2c_bus_ops, |
Subrata Banik | 6bbc91a | 2017-12-07 14:55:51 +0530 | [diff] [blame] | 184 | .ops_pci = &pci_dev_ops_pci, |
Elyes HAOUAS | 1d19127 | 2018-11-27 12:23:48 +0100 | [diff] [blame] | 185 | .init = dw_i2c_device_init, |
| 186 | .acpi_fill_ssdt_generator = dw_i2c_acpi_fill_ssdt, |
Rizwan Qureshi | ae6a4b6 | 2017-04-26 21:06:35 +0530 | [diff] [blame] | 187 | }; |
| 188 | |
| 189 | static const unsigned short pci_device_ids[] = { |
| 190 | PCI_DEVICE_ID_INTEL_SPT_I2C0, |
| 191 | PCI_DEVICE_ID_INTEL_SPT_I2C1, |
| 192 | PCI_DEVICE_ID_INTEL_SPT_I2C2, |
| 193 | PCI_DEVICE_ID_INTEL_SPT_I2C3, |
| 194 | PCI_DEVICE_ID_INTEL_SPT_I2C4, |
| 195 | PCI_DEVICE_ID_INTEL_SPT_I2C5, |
V Sowmya | acc2a48 | 2018-01-23 15:27:23 +0530 | [diff] [blame] | 196 | PCI_DEVICE_ID_INTEL_KBP_H_I2C0, |
| 197 | PCI_DEVICE_ID_INTEL_KBP_H_I2C1, |
| 198 | PCI_DEVICE_ID_INTEL_KBP_H_I2C2, |
| 199 | PCI_DEVICE_ID_INTEL_KBP_H_I2C3, |
Rizwan Qureshi | ae6a4b6 | 2017-04-26 21:06:35 +0530 | [diff] [blame] | 200 | PCI_DEVICE_ID_INTEL_APL_I2C0, |
| 201 | PCI_DEVICE_ID_INTEL_APL_I2C1, |
| 202 | PCI_DEVICE_ID_INTEL_APL_I2C2, |
| 203 | PCI_DEVICE_ID_INTEL_APL_I2C3, |
| 204 | PCI_DEVICE_ID_INTEL_APL_I2C4, |
| 205 | PCI_DEVICE_ID_INTEL_APL_I2C5, |
| 206 | PCI_DEVICE_ID_INTEL_APL_I2C6, |
| 207 | PCI_DEVICE_ID_INTEL_APL_I2C7, |
Lijian Zhao | bbedef9 | 2017-07-29 16:38:38 -0700 | [diff] [blame] | 208 | PCI_DEVICE_ID_INTEL_CNL_I2C0, |
| 209 | PCI_DEVICE_ID_INTEL_CNL_I2C1, |
| 210 | PCI_DEVICE_ID_INTEL_CNL_I2C2, |
| 211 | PCI_DEVICE_ID_INTEL_CNL_I2C3, |
| 212 | PCI_DEVICE_ID_INTEL_CNL_I2C4, |
| 213 | PCI_DEVICE_ID_INTEL_CNL_I2C5, |
Ravi Sarawadi | 3038e9b | 2017-05-18 16:00:35 -0700 | [diff] [blame] | 214 | PCI_DEVICE_ID_INTEL_GLK_I2C0, |
| 215 | PCI_DEVICE_ID_INTEL_GLK_I2C1, |
| 216 | PCI_DEVICE_ID_INTEL_GLK_I2C2, |
| 217 | PCI_DEVICE_ID_INTEL_GLK_I2C3, |
| 218 | PCI_DEVICE_ID_INTEL_GLK_I2C4, |
| 219 | PCI_DEVICE_ID_INTEL_GLK_I2C5, |
| 220 | PCI_DEVICE_ID_INTEL_GLK_I2C6, |
| 221 | PCI_DEVICE_ID_INTEL_GLK_I2C7, |
praveen hodagatta pranesh | e26c4a4 | 2018-09-20 03:49:45 +0800 | [diff] [blame] | 222 | PCI_DEVICE_ID_INTEL_CNP_H_I2C0, |
| 223 | PCI_DEVICE_ID_INTEL_CNP_H_I2C1, |
| 224 | PCI_DEVICE_ID_INTEL_CNP_H_I2C2, |
| 225 | PCI_DEVICE_ID_INTEL_CNP_H_I2C3, |
Aamir Bohra | 9eac039 | 2018-06-30 12:07:04 +0530 | [diff] [blame] | 226 | PCI_DEVICE_ID_INTEL_ICP_I2C0, |
| 227 | PCI_DEVICE_ID_INTEL_ICP_I2C1, |
| 228 | PCI_DEVICE_ID_INTEL_ICP_I2C2, |
| 229 | PCI_DEVICE_ID_INTEL_ICP_I2C3, |
| 230 | PCI_DEVICE_ID_INTEL_ICP_I2C4, |
| 231 | PCI_DEVICE_ID_INTEL_ICP_I2C5, |
Ronak Kanabar | da7ffb48 | 2019-02-05 01:51:13 +0530 | [diff] [blame] | 232 | PCI_DEVICE_ID_INTEL_CMP_I2C0, |
| 233 | PCI_DEVICE_ID_INTEL_CMP_I2C1, |
| 234 | PCI_DEVICE_ID_INTEL_CMP_I2C2, |
| 235 | PCI_DEVICE_ID_INTEL_CMP_I2C3, |
| 236 | PCI_DEVICE_ID_INTEL_CMP_I2C4, |
| 237 | PCI_DEVICE_ID_INTEL_CMP_I2C5, |
Ravi Sarawadi | 6b5bf40 | 2019-10-21 22:25:04 -0700 | [diff] [blame^] | 238 | PCI_DEVICE_ID_INTEL_TGP_I2C0, |
| 239 | PCI_DEVICE_ID_INTEL_TGP_I2C1, |
| 240 | PCI_DEVICE_ID_INTEL_TGP_I2C2, |
| 241 | PCI_DEVICE_ID_INTEL_TGP_I2C3, |
| 242 | PCI_DEVICE_ID_INTEL_TGP_I2C4, |
| 243 | PCI_DEVICE_ID_INTEL_TGP_I2C5, |
| 244 | PCI_DEVICE_ID_INTEL_TGP_I2C6, |
| 245 | PCI_DEVICE_ID_INTEL_TGP_I2C7, |
Ravi Sarawadi | 3038e9b | 2017-05-18 16:00:35 -0700 | [diff] [blame] | 246 | 0, |
Rizwan Qureshi | ae6a4b6 | 2017-04-26 21:06:35 +0530 | [diff] [blame] | 247 | }; |
| 248 | |
| 249 | static const struct pci_driver pch_i2c __pci_driver = { |
| 250 | .ops = &i2c_dev_ops, |
| 251 | .vendor = PCI_VENDOR_ID_INTEL, |
| 252 | .devices = pci_device_ids, |
| 253 | }; |
Subrata Banik | e62836b | 2018-05-07 16:27:51 +0530 | [diff] [blame] | 254 | #endif |