Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License as published by |
| 7 | * the Free Software Foundation; version 2 of the License. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 13 | */ |
| 14 | |
| 15 | #include <arch/io.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 16 | #include <device/mmio.h> |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 17 | #include <console/console.h> |
| 18 | #include <delay.h> |
| 19 | #include <device/device.h> |
| 20 | #include <device/pci.h> |
| 21 | #include <device/pci_ids.h> |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 22 | #include <device/pci_ops.h> |
Vladimir Serbinenko | 1315730 | 2014-02-19 22:18:08 +0100 | [diff] [blame] | 23 | #include <drivers/intel/gma/edid.h> |
| 24 | #include <drivers/intel/gma/i915.h> |
Patrick Rudolph | 5c82026 | 2017-05-17 19:39:12 +0200 | [diff] [blame] | 25 | #include <drivers/intel/gma/intel_bios.h> |
Nico Huber | 1822816 | 2017-06-08 16:31:57 +0200 | [diff] [blame] | 26 | #include <drivers/intel/gma/libgfxinit.h> |
Vladimir Serbinenko | 1315730 | 2014-02-19 22:18:08 +0100 | [diff] [blame] | 27 | #include <pc80/vga.h> |
Patrick Rudolph | 2be2840 | 2017-04-12 16:54:55 +0200 | [diff] [blame] | 28 | #include <southbridge/intel/ibexpeak/nvs.h> |
Matt DeVillier | ebe08e0 | 2017-07-14 13:28:42 -0500 | [diff] [blame] | 29 | #include <drivers/intel/gma/opregion.h> |
Patrick Rudolph | 2be2840 | 2017-04-12 16:54:55 +0200 | [diff] [blame] | 30 | #include <cbmem.h> |
Elyes HAOUAS | 51401c3 | 2019-05-15 21:09:30 +0200 | [diff] [blame] | 31 | #include <types.h> |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 32 | |
| 33 | #include "chip.h" |
Angel Pons | 95de231 | 2020-02-17 13:08:53 +0100 | [diff] [blame] | 34 | #include "ironlake.h" |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 35 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 36 | /* some vga option roms are used for several chipsets but they only have one |
| 37 | * PCI ID in their header. If we encounter such an option rom, we need to do |
Martin Roth | 128c104 | 2016-11-18 09:29:03 -0700 | [diff] [blame] | 38 | * the mapping ourselves |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 39 | */ |
| 40 | |
| 41 | u32 map_oprom_vendev(u32 vendev) |
| 42 | { |
| 43 | u32 new_vendev = vendev; |
| 44 | |
Martin Roth | 128c104 | 2016-11-18 09:29:03 -0700 | [diff] [blame] | 45 | /* none currently. */ |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 46 | |
| 47 | return new_vendev; |
| 48 | } |
| 49 | |
| 50 | static struct resource *gtt_res = NULL; |
| 51 | |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 52 | u32 gtt_read(u32 reg) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 53 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 54 | return read32(res2mmio(gtt_res, reg, 0)); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 55 | } |
| 56 | |
Furquan Shaikh | 77f48cd | 2013-08-19 10:16:50 -0700 | [diff] [blame] | 57 | void gtt_write(u32 reg, u32 data) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 58 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 59 | write32(res2mmio(gtt_res, reg, 0), data); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 60 | } |
| 61 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 62 | #define GTT_RETRY 1000 |
Ronald G. Minnich | 9518b56 | 2013-09-19 16:45:22 -0700 | [diff] [blame] | 63 | int gtt_poll(u32 reg, u32 mask, u32 value) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 64 | { |
Martin Roth | 468d02c | 2019-10-23 21:44:42 -0600 | [diff] [blame] | 65 | unsigned int try = GTT_RETRY; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 66 | u32 data; |
| 67 | |
| 68 | while (try--) { |
| 69 | data = gtt_read(reg); |
| 70 | if ((data & mask) == value) |
| 71 | return 1; |
| 72 | udelay(10); |
| 73 | } |
| 74 | |
| 75 | printk(BIOS_ERR, "GT init timeout\n"); |
| 76 | return 0; |
| 77 | } |
| 78 | |
Patrick Rudolph | 19c2ad8 | 2017-06-30 14:52:01 +0200 | [diff] [blame] | 79 | uintptr_t gma_get_gnvs_aslb(const void *gnvs) |
| 80 | { |
| 81 | const global_nvs_t *gnvs_ptr = gnvs; |
| 82 | return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); |
| 83 | } |
| 84 | |
| 85 | void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) |
| 86 | { |
| 87 | global_nvs_t *gnvs_ptr = gnvs; |
| 88 | if (gnvs_ptr) |
| 89 | gnvs_ptr->aslb = aslb; |
| 90 | } |
| 91 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 92 | static void gma_pm_init_post_vbios(struct device *dev) |
| 93 | { |
Angel Pons | 95de231 | 2020-02-17 13:08:53 +0100 | [diff] [blame] | 94 | struct northbridge_intel_ironlake_config *conf = dev->chip_info; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 95 | u32 reg32; |
| 96 | |
| 97 | printk(BIOS_DEBUG, "GT Power Management Init (post VBIOS)\n"); |
| 98 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 99 | /* Setup Digital Port Hotplug */ |
| 100 | reg32 = gtt_read(0xc4030); |
| 101 | if (!reg32) { |
| 102 | reg32 = (conf->gpu_dp_b_hotplug & 0x7) << 2; |
| 103 | reg32 |= (conf->gpu_dp_c_hotplug & 0x7) << 10; |
| 104 | reg32 |= (conf->gpu_dp_d_hotplug & 0x7) << 18; |
| 105 | gtt_write(0xc4030, reg32); |
| 106 | } |
| 107 | |
| 108 | /* Setup Panel Power On Delays */ |
| 109 | reg32 = gtt_read(0xc7208); |
| 110 | if (!reg32) { |
| 111 | reg32 = (conf->gpu_panel_port_select & 0x3) << 30; |
| 112 | reg32 |= (conf->gpu_panel_power_up_delay & 0x1fff) << 16; |
| 113 | reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff); |
| 114 | gtt_write(0xc7208, reg32); |
| 115 | } |
| 116 | |
| 117 | /* Setup Panel Power Off Delays */ |
| 118 | reg32 = gtt_read(0xc720c); |
| 119 | if (!reg32) { |
| 120 | reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16; |
| 121 | reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff); |
| 122 | gtt_write(0xc720c, reg32); |
| 123 | } |
| 124 | |
| 125 | /* Setup Panel Power Cycle Delay */ |
| 126 | if (conf->gpu_panel_power_cycle_delay) { |
| 127 | reg32 = gtt_read(0xc7210); |
| 128 | reg32 &= ~0xff; |
| 129 | reg32 |= conf->gpu_panel_power_cycle_delay & 0xff; |
| 130 | gtt_write(0xc7210, reg32); |
| 131 | } |
| 132 | |
| 133 | /* Enable Backlight if needed */ |
| 134 | if (conf->gpu_cpu_backlight) { |
| 135 | gtt_write(0x48250, (1 << 31)); |
| 136 | gtt_write(0x48254, conf->gpu_cpu_backlight); |
| 137 | } |
| 138 | if (conf->gpu_pch_backlight) { |
| 139 | gtt_write(0xc8250, (1 << 31)); |
| 140 | gtt_write(0xc8254, conf->gpu_pch_backlight); |
| 141 | } |
| 142 | } |
| 143 | |
Patrick Rudolph | 64a702f | 2017-06-20 18:28:56 +0200 | [diff] [blame] | 144 | /* Enable SCI to ACPI _GPE._L06 */ |
| 145 | static void gma_enable_swsci(void) |
| 146 | { |
| 147 | u16 reg16; |
| 148 | |
| 149 | /* clear DMISCI status */ |
| 150 | reg16 = inw(DEFAULT_PMBASE + TCO1_STS); |
| 151 | reg16 &= DMISCI_STS; |
| 152 | outw(DEFAULT_PMBASE + TCO1_STS, reg16); |
| 153 | |
| 154 | /* clear acpi tco status */ |
| 155 | outl(DEFAULT_PMBASE + GPE0_STS, TCOSCI_STS); |
| 156 | |
| 157 | /* enable acpi tco scis */ |
| 158 | reg16 = inw(DEFAULT_PMBASE + GPE0_EN); |
| 159 | reg16 |= TCOSCI_EN; |
| 160 | outw(DEFAULT_PMBASE + GPE0_EN, reg16); |
| 161 | } |
| 162 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 163 | static void gma_func0_init(struct device *dev) |
| 164 | { |
| 165 | u32 reg32; |
| 166 | |
| 167 | /* IGD needs to be Bus Master */ |
| 168 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 169 | reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; |
| 170 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 171 | |
Arthur Heymans | f266dc6 | 2019-10-01 22:02:31 +0200 | [diff] [blame] | 172 | gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 173 | if (!gtt_res || !gtt_res->base) |
| 174 | return; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 175 | |
Arthur Heymans | 38750f8 | 2019-10-03 09:34:57 +0200 | [diff] [blame] | 176 | if (!acpi_is_wakeup_s3() && |
| 177 | CONFIG(MAINBOARD_USE_LIBGFXINIT)) { |
Angel Pons | 95de231 | 2020-02-17 13:08:53 +0100 | [diff] [blame] | 178 | struct northbridge_intel_ironlake_config *conf = dev->chip_info; |
Arthur Heymans | 4c2f26c | 2018-07-17 16:59:38 +0200 | [diff] [blame] | 179 | int lightup_ok; |
| 180 | printk(BIOS_SPEW, "Initializing VGA without OPROM."); |
Vladimir Serbinenko | 1315730 | 2014-02-19 22:18:08 +0100 | [diff] [blame] | 181 | |
Arthur Heymans | 4c2f26c | 2018-07-17 16:59:38 +0200 | [diff] [blame] | 182 | gma_gfxinit(&lightup_ok); |
Nico Huber | d4ebeaf | 2017-05-22 13:49:22 +0200 | [diff] [blame] | 183 | /* Linux relies on VBT for panel info. */ |
| 184 | generate_fake_intel_oprom(&conf->gfx, dev, |
| 185 | "$VBT IRONLAKE-MOBILE"); |
| 186 | } else { |
| 187 | /* PCI Init, will run VBIOS */ |
| 188 | pci_dev_init(dev); |
Vladimir Serbinenko | 1315730 | 2014-02-19 22:18:08 +0100 | [diff] [blame] | 189 | } |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 190 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 191 | /* Post VBIOS init */ |
| 192 | gma_pm_init_post_vbios(dev); |
Patrick Rudolph | 64a702f | 2017-06-20 18:28:56 +0200 | [diff] [blame] | 193 | |
| 194 | gma_enable_swsci(); |
| 195 | intel_gma_restore_opregion(); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 196 | } |
| 197 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 198 | static void gma_read_resources(struct device *dev) |
| 199 | { |
| 200 | pci_dev_read_resources(dev); |
| 201 | |
| 202 | struct resource *res; |
| 203 | |
| 204 | /* Set the graphics memory to write combining. */ |
| 205 | res = find_resource(dev, PCI_BASE_ADDRESS_2); |
| 206 | if (res == NULL) { |
| 207 | printk(BIOS_DEBUG, "gma: memory resource not found.\n"); |
| 208 | return; |
| 209 | } |
| 210 | res->flags |= IORESOURCE_RESERVE | IORESOURCE_FIXED | IORESOURCE_ASSIGNED; |
Elyes HAOUAS | cf5430f | 2016-09-13 21:27:22 +0200 | [diff] [blame] | 211 | pci_write_config32(dev, PCI_BASE_ADDRESS_2, 0xd0000001); |
| 212 | pci_write_config32(dev, PCI_BASE_ADDRESS_2 + 4, 0); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 213 | res->base = (resource_t) 0xd0000000; |
| 214 | res->size = (resource_t) 0x10000000; |
| 215 | } |
| 216 | |
Matt DeVillier | 6b059ea | 2020-03-30 19:31:54 -0500 | [diff] [blame^] | 217 | static void gma_generate_ssdt(struct device *device) |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 218 | { |
Matt DeVillier | 6b059ea | 2020-03-30 19:31:54 -0500 | [diff] [blame^] | 219 | const struct northbridge_intel_ironlake_config *chip = device->chip_info; |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 220 | |
Matt DeVillier | 6b059ea | 2020-03-30 19:31:54 -0500 | [diff] [blame^] | 221 | drivers_intel_gma_displays_ssdt_generate(&chip->gfx); |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 222 | } |
| 223 | |
Patrick Rudolph | 2be2840 | 2017-04-12 16:54:55 +0200 | [diff] [blame] | 224 | static unsigned long |
| 225 | gma_write_acpi_tables(struct device *const dev, |
| 226 | unsigned long current, |
| 227 | struct acpi_rsdp *const rsdp) |
| 228 | { |
Patrick Rudolph | 5c82026 | 2017-05-17 19:39:12 +0200 | [diff] [blame] | 229 | igd_opregion_t *opregion = (igd_opregion_t *)current; |
Patrick Rudolph | 2be2840 | 2017-04-12 16:54:55 +0200 | [diff] [blame] | 230 | global_nvs_t *gnvs; |
| 231 | |
Matt DeVillier | ebe08e0 | 2017-07-14 13:28:42 -0500 | [diff] [blame] | 232 | if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) |
Patrick Rudolph | 5c82026 | 2017-05-17 19:39:12 +0200 | [diff] [blame] | 233 | return current; |
| 234 | |
| 235 | current += sizeof(igd_opregion_t); |
| 236 | |
| 237 | /* GNVS has been already set up */ |
| 238 | gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); |
| 239 | if (gnvs) { |
| 240 | /* IGD OpRegion Base Address */ |
Patrick Rudolph | 19c2ad8 | 2017-06-30 14:52:01 +0200 | [diff] [blame] | 241 | gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion); |
Patrick Rudolph | 5c82026 | 2017-05-17 19:39:12 +0200 | [diff] [blame] | 242 | } else { |
| 243 | printk(BIOS_ERR, "Error: GNVS table not found.\n"); |
Patrick Rudolph | 2be2840 | 2017-04-12 16:54:55 +0200 | [diff] [blame] | 244 | } |
| 245 | |
Patrick Rudolph | 5c82026 | 2017-05-17 19:39:12 +0200 | [diff] [blame] | 246 | current = acpi_align_current(current); |
Patrick Rudolph | 2be2840 | 2017-04-12 16:54:55 +0200 | [diff] [blame] | 247 | return current; |
| 248 | } |
| 249 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 250 | static struct pci_operations gma_pci_ops = { |
Subrata Banik | 4a0f071 | 2019-03-20 14:29:47 +0530 | [diff] [blame] | 251 | .set_subsystem = pci_dev_set_subsystem, |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 252 | }; |
| 253 | |
| 254 | static struct device_operations gma_func0_ops = { |
Matt DeVillier | 6b059ea | 2020-03-30 19:31:54 -0500 | [diff] [blame^] | 255 | .read_resources = gma_read_resources, |
| 256 | .set_resources = pci_dev_set_resources, |
| 257 | .enable_resources = pci_dev_enable_resources, |
| 258 | .acpi_fill_ssdt = gma_generate_ssdt, |
| 259 | .init = gma_func0_init, |
| 260 | .scan_bus = 0, |
| 261 | .enable = 0, |
| 262 | .ops_pci = &gma_pci_ops, |
Patrick Rudolph | 2be2840 | 2017-04-12 16:54:55 +0200 | [diff] [blame] | 263 | .write_acpi_tables = gma_write_acpi_tables, |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 264 | }; |
| 265 | |
Elyes HAOUAS | cf5430f | 2016-09-13 21:27:22 +0200 | [diff] [blame] | 266 | static const unsigned short pci_device_ids[] = { |
| 267 | 0x0046, 0x0102, 0x0106, 0x010a, 0x0112, |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 268 | 0x0116, 0x0122, 0x0126, 0x0156, |
| 269 | 0x0166, |
| 270 | 0 |
| 271 | }; |
| 272 | |
| 273 | static const struct pci_driver gma __pci_driver = { |
| 274 | .ops = &gma_func0_ops, |
| 275 | .vendor = PCI_VENDOR_ID_INTEL, |
| 276 | .devices = pci_device_ids, |
| 277 | }; |