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review.coreboot.org / coreboot / 6af42005230d05088fe814206fac87b7169fd458 / . / src / vendorcode / intel / fsp / fsp2_0 / elkhartlake / FspmUpd.h
blob: af987bbdd87b9b6eae474bb0737574de72c324a9 [file] [log] [blame]
Martin Roth062c4a12021-02-14 13:58:31 -0700[diff] [blame]1/** @file
2
Tan, Lean Shengef41e8a2021-05-24 00:13:59 -0700[diff] [blame]3Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
Martin Roth062c4a12021-02-14 13:58:31 -0700[diff] [blame]4
5Redistribution and use in source and binary forms, with or without modification,
6are permitted provided that the following conditions are met:
7
8* Redistributions of source code must retain the above copyright notice, this
9 list of conditions and the following disclaimer.
10* Redistributions in binary form must reproduce the above copyright notice, this
11 list of conditions and the following disclaimer in the documentation and/or
12 other materials provided with the distribution.
13* Neither the name of Intel Corporation nor the names of its contributors may
14 be used to endorse or promote products derived from this software without
15 specific prior written permission.
16
17 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
21 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 THE POSSIBILITY OF SUCH DAMAGE.
28
29 This file is automatically generated. Please do NOT modify !!!
30
31**/
32
33#ifndef __FSPMUPD_H__
34#define __FSPMUPD_H__
35
36#include <FspUpd.h>
37
38#pragma pack(1)
39
40
41#include <MemInfoHob.h>
42
43///
44/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC.
45///
46typedef struct {
47 UINT8 Revision; ///< Chipset Init Info Revision
48 UINT8 Rsvd[3]; ///< Reserved
49 UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table
50 UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table
51} CHIPSET_INIT_INFO;
52
53
54/** Fsp M Configuration
55**/
56typedef struct {
57
58/** Offset 0x0040 - Platform Reserved Memory Size
59 The minimum platform memory size required to pass control into DXE
60**/
61 UINT64 PlatformMemorySize;
62
63/** Offset 0x0048 - SPD Data Length
64 Length of SPD Data
65 0x100:256 Bytes, 0x200:512 Bytes
66**/
67 UINT16 MemorySpdDataLen;
68
69/** Offset 0x004A - Enable above 4GB MMIO resource support
70 Enable/disable above 4GB MMIO resource support
71 $EN_DIS
72**/
73 UINT8 EnableAbove4GBMmio;
74
75/** Offset 0x004B - Enable/Disable CrashLog Device 10
76 Enable(Default): Enable CPU CrashLog Device 10, Disable: Disable CPU CrashLog
77 $EN_DIS
78**/
79 UINT8 CpuCrashLogDevice;
80
81/** Offset 0x004C - Memory SPD Pointer Channel 0 Dimm 0
82 Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
83**/
84 UINT32 MemorySpdPtr00;
85
86/** Offset 0x0050 - Memory SPD Pointer Channel 0 Dimm 1
87 Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
88**/
89 UINT32 MemorySpdPtr01;
90
91/** Offset 0x0054 - Memory SPD Pointer Channel 1 Dimm 0
92 Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
93**/
94 UINT32 MemorySpdPtr10;
95
96/** Offset 0x0058 - Memory SPD Pointer Channel 1 Dimm 1
97 Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
98**/
99 UINT32 MemorySpdPtr11;
100
101/** Offset 0x005C - Dq Byte Map CH0
102 Dq byte mapping between CPU and DRAM, Channel 0: board-dependent
103**/
104 UINT8 DqByteMapCh0[12];
105
106/** Offset 0x0068 - Dq Byte Map CH1
107 Dq byte mapping between CPU and DRAM, Channel 1: board-dependent
108**/
109 UINT8 DqByteMapCh1[12];
110
111/** Offset 0x0074 - Dqs Map CPU to DRAM CH 0
112 Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent
113**/
114 UINT8 DqsMapCpu2DramCh0[8];
115
116/** Offset 0x007C - Dqs Map CPU to DRAM CH 1
117 Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent
118**/
119 UINT8 DqsMapCpu2DramCh1[8];
120
121/** Offset 0x0084 - RcompResister settings
122 Indicates RcompReister settings: Board-dependent
123**/
124 UINT16 RcompResistor[3];
125
126/** Offset 0x008A - RcompTarget settings
127 RcompTarget settings: board-dependent
128**/
129 UINT16 RcompTarget[5];
130
131/** Offset 0x0094 - VREF_CA
132 CA Vref routing: board-dependent
133 0:VREF_CA goes to both CH_A and CH_B, 1: VREF_CA to CH_A and VREF_DQ_A to CH_B,
134 2:VREF_CA to CH_A and VREF_DQ_B to CH_B
135**/
136 UINT8 CaVrefConfig;
137
138/** Offset 0x0095 - Smram Mask
139 The SMM Regions AB-SEG and/or H-SEG reserved
140 0: Neither, 1:AB-SEG, 2:H-SEG, 3: Both
141**/
142 UINT8 SmramMask;
143
144/** Offset 0x0096 - Dqs Pins Interleaved Setting
145 Indicates DqPinsInterleaved setting: board-dependent
146 $EN_DIS
147**/
148 UINT8 DqPinsInterleaved;
149
150/** Offset 0x0097 - LPDDR4 Write DQ/DQS Retraining
151 Enables/Disable LPDDR4 Write DQ/DQS Retraining
152 $EN_DIS
153**/
154 UINT8 Lp4DqsOscEn;
155
156/** Offset 0x0098 - Ibecc
157 Enables/Disable Ibecc
158 $EN_DIS
159**/
160 UINT8 Ibecc;
161
162/** Offset 0x0099 - IbeccParity
163 In-Band ECC Parity Control
164 $EN_DIS
165**/
166 UINT8 IbeccParity;
167
168/** Offset 0x009A - IbeccOperationMode
169 In-Band ECC Operation Mode
170 0:Protect base on address range, 1: Non-protected, 2: All protected
171**/
172 UINT8 IbeccOperationMode;
173
174/** Offset 0x009B - IbeccErrorInj Note: Modification accepts the disclaimer shown in the Help text
175 Disclaimer: Warning: This must NOT be enabled for production!!! Enabling Error Injection
176 allows attackers who have access to the Host Operating System to inject IBECC errors
177 that can cause unintended memory corruption and enable the leak of security data
178 in the BIOS stolen memory regions.
179 $EN_DIS
180**/
181 UINT8 IbeccErrorInj;
182
183/** Offset 0x009C - IbeccProtectedRegionEnable
184 In-Band ECC Protected Region Enable
185 $EN_DIS
186**/
187 UINT8 IbeccProtectedRegionEnable[8];
188
189/** Offset 0x00A4 - IbeccProtectedRegionBases
190 IBECC Protected Region Bases
191**/
192 UINT16 IbeccProtectedRegionBase[8];
193
194/** Offset 0x00B4 - IbeccProtectedRegionMasks
195 IBECC Protected Region Masks
196**/
197 UINT16 IbeccProtectedRegionMask[8];
198
199/** Offset 0x00C4 - MrcTaskDebugPrintEnable
200 Mrc Task Debug Print Enable. 0(Default)=Disable, non-Zero=Enable Task Debug print
201**/
202 UINT8 MrcTaskDebugEnable;
203
204/** Offset 0x00C5 - Rank Margin Tool per Task
205 This option enables the user to execute Rank Margin Tool per major training step
206 in the MRC.
207 $EN_DIS
208**/
209 UINT8 RmtPerTask;
210
211/** Offset 0x00C6 - Training Trace
212 This option enables the trained state tracing feature in MRC. This feature will
213 print out the key training parameters state across major training steps.
214 $EN_DIS
215**/
216 UINT8 TrainTrace;
217
218/** Offset 0x00C7
219**/
220 UINT8 UnusedUpdSpace0;
221
222/** Offset 0x00C8 - Intel Enhanced Debug
223 Intel Enhanced Debug (IED): 0=Disabled, 0x400000=Enabled and 4MB SMRAM occupied
224 0 : Disable, 0x400000 : Enable
225**/
226 UINT32 IedSize;
227
228/** Offset 0x00CC - Tseg Size
229 Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build
230 0x0400000:4MB, 0x01000000:16MB
231**/
232 UINT32 TsegSize;
233
234/** Offset 0x00D0 - MMIO Size
235 Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB
236**/
237 UINT16 MmioSize;
238
239/** Offset 0x00D2 - LowSupplyEnData
240 Enable: Enable Low Supply for LPDDR4 Data, Disable(Default)
241 $EN_DIS
242**/
243 UINT8 LowSupplyEnData;
244
245/** Offset 0x00D3 - LowSupplyEnCcc
246 Enable: Enable Low Supply for LPDDR4 Clock/Command/Control, Disable(Default)
247 $EN_DIS
248**/
249 UINT8 LowSupplyEnCcc;
250
251/** Offset 0x00D4 - Memory Test on Warm Boot
252 Run Base Memory Test on Warm Boot
253 0:Disable, 1:Enable
254**/
255 UINT8 MemTestOnWarmBoot;
256
257/** Offset 0x00D5 - Probeless Trace
258 Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB.
259 This also requires IED to be enabled.
260 $EN_DIS
261**/
262 UINT8 ProbelessTrace;
263
264/** Offset 0x00D6 - Enable SMBus
265 Enable/disable SMBus controller.
266 $EN_DIS
267**/
268 UINT8 SmbusEnable;
269
270/** Offset 0x00D7 - Spd Address Tabl
271 Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used
272 if SPD Address is 00
273**/
274 UINT8 SpdAddressTable[4];
275
276/** Offset 0x00DB - Platform Debug Consent
277 To 'opt-in' for debug, please select 'Enabled' with the desired debug probe type.
278 Enabling this BIOS option may alter the default value of other debug-related BIOS
279 options.\Manual: Do not use Platform Debug Consent to override other debug-relevant
280 policies, but the user must set each debug option manually, aimed at advanced users.\n
281 Note: DCI OOB (aka BSSB) uses CCA probe;[DCI OOB+DbC] and [USB2 DbC] have the same setting.
282 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), 3:Enabled (USB3 DbC),
283 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), 6:Enable (2-wire DCI OOB), 7:Manual
284**/
285 UINT8 PlatformDebugConsent;
286
287/** Offset 0x00DC - DCI Enable
288 Determine if to enable DCI debug from host
289 $EN_DIS
290**/
291 UINT8 DciEn;
292
293/** Offset 0x00DD - DCI DbC Mode
294 Disabled: Clear both USB2/3DBCEN; USB2: set USB2DBCEN; USB3: set USB3DBCEN; Both:
295 Set both USB2/3DBCEN; No Change: Comply with HW value
296 0:Disabled, 1:USB2 DbC, 2:USB3 DbC, 3:Both, 4:No Change
297**/
298 UINT8 DciDbcMode;
299
300/** Offset 0x00DE - Enable DCI ModPHY Pwoer Gate
301 Enable ModPHY Pwoer Gate when DCI is enabled
302 $EN_DIS
303**/
304 UINT8 DciModphyPg;
305
306/** Offset 0x00DF - USB3 Type-C UFP2DFP Kernel/Platform Debug Support
307 This BIOS option enables kernel and platform debug for USB3 interface over a UFP
308 Type-C receptacle, select 'No Change' will do nothing to UFP2DFP setting.
309 0:Disabled, 1:Enabled, 2:No Change
310**/
311 UINT8 DciUsb3TypecUfpDbg;
312
313/** Offset 0x00E0 - PCH Trace Hub Mode
314 Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger'
315 if Trace Hub is used by target debugger software or 'Disable' trace hub functionality.
316 0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode
317**/
318 UINT8 PchTraceHubMode;
319
320/** Offset 0x00E1 - PCH Trace Hub Memory Region 0 buffer Size
321 Specify size of Pch trace memory region 0 buffer, the size can be 0, 1MB, 8MB, 64MB,
322 128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB.
323 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB
324**/
325 UINT8 PchTraceHubMemReg0Size;
326
327/** Offset 0x00E2 - PCH Trace Hub Memory Region 1 buffer Size
328 Specify size of Pch trace memory region 1 buffer, the size can be 0, 1MB, 8MB, 64MB,
329 128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB.
330 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB
331**/
332 UINT8 PchTraceHubMemReg1Size;
333
334/** Offset 0x00E3 - PchPreMemRsvd
335 Reserved for PCH Pre-Mem Reserved
336 $EN_DIS
337**/
338 UINT8 PchPreMemRsvd[7];
339
340/** Offset 0x00EA - State of X2APIC_OPT_OUT bit in the DMAR table
341 0=Disable/Clear, 1=Enable/Set
342 $EN_DIS
343**/
344 UINT8 X2ApicOptOut;
345
346/** Offset 0x00EB - State of DMA_CONTROL_GUARANTEE bit in the DMAR table
347 0=Disable/Clear, 1=Enable/Set
348 $EN_DIS
349**/
350 UINT8 DmaControlGuarantee;
351
352/** Offset 0x00EC - Base addresses for VT-d function MMIO access
353 Base addresses for VT-d MMIO access per VT-d engine
354**/
355 UINT32 VtdBaseAddress[9];
356
357/** Offset 0x0110 - Disable VT-d
358 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled)
359 $EN_DIS
360**/
361 UINT8 VtdDisable;
362
363/** Offset 0x0111 - Vtd Programming for Igd
364 1=Enable/TRUE (Igd VT-d Bar programming enabled), 0=Disable/FLASE (Igd VT-d Bar
365 programming disabled)
366 $EN_DIS
367**/
368 UINT8 VtdIgdEnable;
369
370/** Offset 0x0112 - Vtd Programming for Ipu
371 1=Enable/TRUE (Ipu VT-d Bar programming enabled), 0=Disable/FLASE (Ipu VT-d Bar
372 programming disabled)
373 $EN_DIS
374**/
375 UINT8 VtdIpuEnable;
376
377/** Offset 0x0113 - Vtd Programming for Iop
378 1=Enable/TRUE (Iop VT-d Bar programming enabled), 0=Disable/FLASE (Iop VT-d Bar
379 programming disabled)
380 $EN_DIS
381**/
382 UINT8 VtdIopEnable;
383
384/** Offset 0x0114 - Vtd Programming for ITbt
385 1=Enable/TRUE (ITbt VT-d Bar programming enabled), 0=Disable/FLASE (ITbt VT-d Bar
386 programming disabled)
387 $EN_DIS
388**/
389 UINT8 VtdItbtEnable;
390
391/** Offset 0x0115 - Disable Te Igd
392 0=Enable/FALSE(Te Igd enabled), 1=Disable/TRUE (Te Igd disabled)
393 $EN_DIS
394**/
395 UINT8 DisableTeIgd;
396
397/** Offset 0x0116 - Internal Graphics Pre-allocated Memory
398 Size of memory preallocated for internal graphics.
399 0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0x05:160MB, 0xF0:4MB, 0xF1:8MB,
400 0xF2:12MB, 0xF3:16MB, 0xF4:20MB, 0xF5:24MB, 0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB,
401 0xFA:44MB, 0xFB:48MB, 0xFC:52MB, 0xFD:56MB, 0xFE:60MB
402**/
403 UINT8 IgdDvmt50PreAlloc;
404
405/** Offset 0x0117 - Internal Graphics
406 Enable/disable internal graphics.
407 $EN_DIS
408**/
409 UINT8 InternalGfx;
410
411/** Offset 0x0118 - Aperture Size
412 Select the Aperture Size.
413 0:128 MB, 1:256 MB, 2:512 MB
414**/
415 UINT8 ApertureSize;
416
417/** Offset 0x0119 - Board Type
418 MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile
419 Halo, 7=UP Server
420 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server
421**/
422 UINT8 UserBd;
423
424/** Offset 0x011A - DDR Frequency Limit
425 Maximum Memory Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867,
426 2133, 2400, 2667, 2933 and 0 for Auto.
427 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto
428**/
429 UINT16 DdrFreqLimit;
430
431/** Offset 0x011C - SA GV
432 System Agent dynamic frequency support and when enabled memory will be training
433 at three different frequencies.
434 0:Disabled, 1:FixedLow, 2:FixedMid, 3:FixedHigh, 4:Enabled
435**/
436 UINT8 SaGv;
437
438/** Offset 0x011D - DDR Speed Control
439 DDR Frequency and Gear control for all SAGV points.
440 0:Auto, 1:Manual
441**/
442 UINT8 DdrSpeedControl;
443
444/** Offset 0x011E - Low Frequency
445 SAGV Low Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133,
446 2400, 2667, 2933 and 0 for Auto.
447 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto
448**/
449 UINT16 FreqSaGvLow;
450
451/** Offset 0x0120 - Mid Frequency
452 SAGV Mid Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133,
453 2400, 2667, 2933 and 0 for Auto.
454 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto
455**/
456 UINT16 FreqSaGvMid;
457
458/** Offset 0x0122 - Channel A DIMM Control
459 Channel A DIMM Control Support - Enable or Disable Dimms on Channel A.
460 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
461**/
462 UINT8 DisableDimmChannel0;
463
464/** Offset 0x0123 - Channel B DIMM Control
465 Channel B DIMM Control Support - Enable or Disable Dimms on Channel B.
466 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
467**/
468 UINT8 DisableDimmChannel1;
469
470/** Offset 0x0124 - Scrambler Support
471 This option enables data scrambling in memory.
472 $EN_DIS
473**/
474 UINT8 ScramblerSupport;
475
476/** Offset 0x0125 - Ddr4OneDpc
477 DDR4 1DPC performance feature for 2R DIMMs. Can be enabled on DIMM0 or DIMM1 only,
478 or on both (default)
479 0: Disabled, 1: Enabled on DIMM0 only, 2: Enabled on DIMM1 only, 3: Enabled
480**/
481 UINT8 Ddr4OneDpc;
482
483/** Offset 0x0126
484**/
485 UINT8 UnusedUpdSpace1[2];
486
487/** Offset 0x0128 - MMA Test Content Pointer
488 Pointer to MMA Test Content in Memory
489**/
490 UINT32 MmaTestContentPtr;
491
492/** Offset 0x012C - MMA Test Content Size
493 Size of MMA Test Content in Memory
494**/
495 UINT32 MmaTestContentSize;
496
497/** Offset 0x0130 - MMA Test Config Pointer
498 Pointer to MMA Test Config in Memory
499**/
500 UINT32 MmaTestConfigPtr;
501
502/** Offset 0x0134 - MMA Test Config Size
503 Size of MMA Test Config in Memory
504**/
505 UINT32 MmaTestConfigSize;
506
507/** Offset 0x0138 - SPD Profile Selected
508 Select DIMM timing profile. Options are 0=Default profile, 1=Custom profile, 2=XMP
509 Profile 1, 3=XMP Profile 2
510 0:Default profile, 1:Custom profile, 2:XMP profile 1, 3:XMP profile 2
511**/
512 UINT8 SpdProfileSelected;
513
514/** Offset 0x0139
515**/
516 UINT8 UnusedUpdSpace2;
517
518/** Offset 0x013A - Memory Voltage
519 Memory Voltage Override (Vddq). Default = no override
520 0:Default, 1200:1.20 Volts, 1250:1.25 Volts, 1300:1.30 Volts, 1350:1.35 Volts, 1400:1.40
521 Volts, 1450:1.45 Volts, 1500:1.50 Volts, 1550:1.55 Volts, 1600:1.60 Volts, 1650:1.65 Volts
522**/
523 UINT16 VddVoltage;
524
525/** Offset 0x013C - Memory Reference Clock
526 100MHz, 133MHz.
527 0:133MHz, 1:100MHz
528**/
529 UINT8 RefClk;
530
531/** Offset 0x013D - Memory Ratio
532 Automatic or the frequency will equal ratio times reference clock. Set to Auto to
533 recalculate memory timings listed below.
534 0:Auto, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15
535**/
536 UINT8 Ratio;
537
538/** Offset 0x013E - tCL
539 CAS Latency, 0: AUTO, max: 31
540**/
541 UINT8 tCL;
542
543/** Offset 0x013F - tCWL
544 Min CAS Write Latency Delay Time, 0: AUTO, max: 34
545**/
546 UINT8 tCWL;
547
548/** Offset 0x0140 - tFAW
549 Min Four Activate Window Delay Time, 0: AUTO, max: 63
550**/
551 UINT16 tFAW;
552
553/** Offset 0x0142 - tRAS
554 RAS Active Time, 0: AUTO, max: 64
555**/
556 UINT16 tRAS;
557
558/** Offset 0x0144 - tRCD/tRP
559 RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 63
560**/
561 UINT8 tRCDtRP;
562
563/** Offset 0x0145
564**/
565 UINT8 UnusedUpdSpace3;
566
567/** Offset 0x0146 - tREFI
568 Refresh Interval, 0: AUTO, max: 65535
569**/
570 UINT16 tREFI;
571
572/** Offset 0x0148 - tRFC
573 Min Refresh Recovery Delay Time, 0: AUTO, max: 1023
574**/
575 UINT16 tRFC;
576
577/** Offset 0x014A - tRRD
578 Min Row Active to Row Active Delay Time, 0: AUTO, max: 15
579**/
580 UINT8 tRRD;
581
582/** Offset 0x014B - tRTP
583 Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 15. DDR4 legal
584 values: 5, 6, 7, 8, 9, 10, 12
585**/
586 UINT8 tRTP;
587
588/** Offset 0x014C - tWR
589 Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18,
590 20, 24, 30, 34, 40
591 0:Auto, 5:5, 6:6, 7:7, 8:8, 10:10, 12:12, 14:14, 16:16, 18:18, 20:20, 24:24, 30:30,
592 34:34, 40:40
593**/
594 UINT8 tWR;
595
596/** Offset 0x014D - tWTR
597 Min Internal Write to Read Command Delay Time, 0: AUTO, max: 28
598**/
599 UINT8 tWTR;
600
601/** Offset 0x014E - NMode
602 System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N
603**/
604 UINT8 NModeSupport;
605
606/** Offset 0x014F - DllBwEn[0]
607 DllBwEn[0], for 1067 (0..7)
608**/
609 UINT8 DllBwEn0;
610
611/** Offset 0x0150 - DllBwEn[1]
612 DllBwEn[1], for 1333 (0..7)
613**/
614 UINT8 DllBwEn1;
615
616/** Offset 0x0151 - DllBwEn[2]
617 DllBwEn[2], for 1600 (0..7)
618**/
619 UINT8 DllBwEn2;
620
621/** Offset 0x0152 - DllBwEn[3]
622 DllBwEn[3], for 1867 and up (0..7)
623**/
624 UINT8 DllBwEn3;
625
626/** Offset 0x0153 - ISVT IO Port Address
627 ISVT IO Port Address. 0=Minimal, 0xFF=Maximum, 0x99=Default
628**/
629 UINT8 IsvtIoPort;
630
631/** Offset 0x0154 - Enable Intel HD Audio (Azalia)
632 0: Disable, 1: Enable (Default) Azalia controller
633 $EN_DIS
634**/
635 UINT8 PchHdaEnable;
636
637/** Offset 0x0155 - Enable PSE Controller
638 0: Disable; 1: Enable (Default) PSE controller
639 $EN_DIS
640**/
641 UINT8 PchPseEnable;
642
643/** Offset 0x0156 - CPU Trace Hub Mode
644 Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger'
645 if Trace Hub is used by target debugger software or 'Disable' trace hub functionality.
646 0: Disable, 1:Target Debugger Mode, 2:Host Debugger Mode
647**/
648 UINT8 CpuTraceHubMode;
649
650/** Offset 0x0157 - CPU Trace Hub Memory Region 0
651 CPU Trace Hub Memory Region 0, The avaliable memory size is : 0MB, 1MB, 8MB, 64MB,
652 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB.
653 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB
654**/
655 UINT8 CpuTraceHubMemReg0Size;
656
657/** Offset 0x0158 - CPU Trace Hub Memory Region 1
658 CPU Trace Hub Memory Region 1. The avaliable memory size is : 0MB, 1MB, 8MB, 64MB,
659 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB.
660 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB
661**/
662 UINT8 CpuTraceHubMemReg1Size;
663
664/** Offset 0x0159 - SA GV Low Gear
665 Gear Selection for SAGV Low point
666 0:Gear1, 1:Gear2
667**/
668 UINT8 SaGvLowGear2;
669
670/** Offset 0x015A - SA GV Mid Gear
671 Gear Selection for SAGV Mid point
672 0:Gear1, 1:Gear2
673**/
674 UINT8 SaGvMidGear2;
675
676/** Offset 0x015B - SA GV High Gear
677 Gear Selection for SAGV High point, or when SAGV is disabled
678 0:Gear1, 1:Gear2
679**/
680 UINT8 SaGvHighGear2;
681
682/** Offset 0x015C - HECI Timeouts
683 0: Disable, 1: Enable (Default) timeout check for HECI
684 $EN_DIS
685**/
686 UINT8 HeciTimeouts;
687
688/** Offset 0x015D
689**/
690 UINT8 UnusedUpdSpace4[3];
691
692/** Offset 0x0160 - HECI1 BAR address
693 BAR address of HECI1
694**/
695 UINT32 Heci1BarAddress;
696
697/** Offset 0x0164 - HECI2 BAR address
698 BAR address of HECI2
699**/
700 UINT32 Heci2BarAddress;
701
702/** Offset 0x0168 - HECI3 BAR address
703 BAR address of HECI3
704**/
705 UINT32 Heci3BarAddress;
706
707/** Offset 0x016C - HG dGPU Power Delay
708 HG dGPU delay interval after power enabling: 0=Minimal, 1000=Maximum, default is
709 300=300 microseconds
710**/
711 UINT16 HgDelayAfterPwrEn;
712
713/** Offset 0x016E - HG dGPU Reset Delay
714 HG dGPU delay interval for Reset complete: 0=Minimal, 1000=Maximum, default is 100=100
715 microseconds
716**/
717 UINT16 HgDelayAfterHoldReset;
718
719/** Offset 0x0170 - MMIO size adjustment for AUTO mode
720 Positive number means increasing MMIO size, Negative value means decreasing MMIO
721 size: 0 (Default)=no change to AUTO mode MMIO size
722**/
723 UINT16 MmioSizeAdjustment;
724
725/** Offset 0x0172 - PCIe ASPM programming will happen in relation to the Oprom
726 Select when PCIe ASPM programming will happen in relation to the Oprom. Before(0x0)(Default):
727 Do PCIe ASPM programming before Oprom, After(0x1): Do PCIe ASPM programming after
728 Oprom, requires an SMI handler to save/restore ASPM settings during S3 resume
729 0:Before, 1:After
730**/
731 UINT8 InitPcieAspmAfterOprom;
732
733/** Offset 0x0173 - Selection of the primary display device
734 0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, 3(Default)=AUTO, 4=Hybrid Graphics
735 0:iGFX, 1:PEG, 2:PCIe Graphics on PCH, 3:AUTO, 4:Hybrid Graphics
736**/
737 UINT8 PrimaryDisplay;
738
739/** Offset 0x0174 - Selection of PSMI Region size
740 0=32MB, 1=288MB, 2=544MB, 3=800MB, 4=1024MB Default is 0
741 0:32MB, 1:288MB, 2:544MB, 3:800MB, 4:1024MB
742**/
743 UINT8 PsmiRegionSize;
744
745/** Offset 0x0175
746**/
747 UINT8 UnusedUpdSpace5[3];
748
749/** Offset 0x0178 - Temporary MMIO address for GMADR
750 The reference code will use this as Temporary MMIO address space to access GMADR
751 Registers.Platform should provide conflict free Temporary MMIO Range: GmAdr to
752 (GmAdr + ApertureSize). Default is (PciExpressBaseAddress - ApertureSize) to (PciExpressBaseAddress
753 - 0x1) (Where ApertureSize = 256MB)
754**/
755 UINT32 GmAdr;
756
757/** Offset 0x017C - Temporary MMIO address for GTTMMADR
758 The reference code will use this as Temporary MMIO address space to access GTTMMADR
759 Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr
760 to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO
761 + 6MB Reserved + GttSize)) to (GmAdr - 0x1) (Where GttSize = 8MB)
762**/
763 UINT32 GttMmAdr;
764
765/** Offset 0x0180 - Selection of iGFX GTT Memory size
766 1=2MB, 2=4MB, 3=8MB, Default is 3
767 1:2MB, 2:4MB, 3:8MB
768**/
769 UINT16 GttSize;
770
771/** Offset 0x0182 - Hybrid Graphics GPIO information for PEG 0
772 Hybrid Graphics GPIO information for PEG 0, for Reset, power and wake GPIOs
773**/
774 UINT8 CpuPcie0Rtd3Gpio[24];
775
776/** Offset 0x019A - Enable/Disable MRC TXT dependency
777 When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default):
778 MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization
779 $EN_DIS
780**/
781 UINT8 TxtImplemented;
782
783/** Offset 0x019B - Enable/Disable SA OcSupport
784 Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport
785 $EN_DIS
786**/
787 UINT8 SaOcSupport;
788
789/** Offset 0x019C - GT slice Voltage Mode
790 0(Default): Adaptive, 1: Override
791 0: Adaptive, 1: Override
792**/
793 UINT8 GtVoltageMode;
794
795/** Offset 0x019D - Maximum GTs turbo ratio override
796 0(Default)=Minimal/Auto, 60=Maximum
797**/
798 UINT8 GtMaxOcRatio;
799
800/** Offset 0x019E - The voltage offset applied to GT slice
801 0(Default)=Minimal, 1000=Maximum
802**/
803 UINT16 GtVoltageOffset;
804
805/** Offset 0x01A0 - The GT slice voltage override which is applied to the entire range of GT frequencies
806 0(Default)=Minimal, 2000=Maximum
807**/
808 UINT16 GtVoltageOverride;
809
810/** Offset 0x01A2 - adaptive voltage applied during turbo frequencies
811 0(Default)=Minimal, 2000=Maximum
812**/
813 UINT16 GtExtraTurboVoltage;
814
815/** Offset 0x01A4 - voltage offset applied to the SA
816 0(Default)=Minimal, 1000=Maximum
817**/
818 UINT16 SaVoltageOffset;
819
820/** Offset 0x01A6 - PCIe root port Function number for Hybrid Graphics dGPU
821 Root port Index number to indicate which PCIe root port has dGPU
822**/
823 UINT8 RootPortIndex;
824
825/** Offset 0x01A7 - Realtime Memory Timing
826 0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform
827 realtime memory timing changes after MRC_DONE.
828 0: Disabled, 1: Enabled
829**/
830 UINT8 RealtimeMemoryTiming;
831
832/** Offset 0x01A8 - This is policy to control iTBT PCIe Multiple Segment setting.
833 When Disabled all the TBT PCIe RP are located at Segment0, When Enabled all the
834 TBT PCIe RP are located at Segment1. <b>0: Disable</b>; 1: Enable.
835 $EN_DIS
836**/
837 UINT8 PcieMultipleSegmentEnabled;
838
839/** Offset 0x01A9 - Enable/Disable SA IPU
840 Enable(Default): Enable SA IPU, Disable: Disable SA IPU
841 $EN_DIS
842**/
843 UINT8 SaIpuEnable;
844
845/** Offset 0x01AA - IPU IMR Configuration
846 0:IPU Camera, 1:IPU Gen Default is 0
847 0:IPU Camera, 1:IPU Gen
848**/
849 UINT8 SaIpuImrConfiguration;
850
851/** Offset 0x01AB - IMGU CLKOUT Configuration
852 The configuration of IMGU CLKOUT, 0: Disable;<b>1: Enable</b>.
853 $EN_DIS
854**/
855 UINT8 ImguClkOutEn[5];
856
857/** Offset 0x01B0 - IPU FUSA Configuration
858 0:FUSA Disable, 1:FUSA Enable Default is 0
859 0:FUSA Disable, 1:FUSA Enable
860**/
861 UINT8 SaIpuFusaConfigEnable;
862
863/** Offset 0x01B1
864**/
865 UINT8 UnusedUpdSpace6[3];
866
867/** Offset 0x01B4 - Enable PCIE RP Mask
868 Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
869 for port1, bit1 for port2, and so on.
870**/
871 UINT32 CpuPcieRpEnableMask;
872
873/** Offset 0x01B8 - Assertion on Link Down GPIOs
874 GPIO Assertion on Link Down. Disabled(0x0)(Default): Disable assertion on Link Down
875 GPIOs, Enabled(0x1): Enable assertion on Link Down GPIOs
876 0:Disable, 1:Enable
877**/
878 UINT8 CpuPcieRpLinkDownGpios;
879
880/** Offset 0x01B9 - Enable ClockReq Messaging
881 ClockReq Messaging. Disabled(0x0): Disable ClockReq Messaging, Enabled(0x1)(Default):
882 Enable ClockReq Messaging
883 0:Disable, 1:Enable
884**/
885 UINT8 CpuPcieRpClockReqMsgEnable;
886
887/** Offset 0x01BA - PCIE RP Pcie Speed
888 Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3;
889 4: Gen4 (see: CPU_PCIE_SPEED).
890**/
891 UINT8 CpuPcieRpPcieSpeed[4];
892
893/** Offset 0x01BE - Selection of PSMI Support On/Off
894 0(Default) = FALSE, 1 = TRUE. When TRUE, it will allow the PSMI Support
895 $EN_DIS
896**/
897 UINT8 GtPsmiSupport;
898
899/** Offset 0x01BF - Selection of DiSM Region Size
900 DiSM Size to be allocated for 2LM Sku Default is 0
901 0:0GB, 1:1GB, 2:2GB, 3:3GB, 4:4GB, 5:5GB, 6:6GB, 7:7GB
902**/
903 UINT8 DismSize;
904
905/** Offset 0x01C0 - Pram Size
906 Persisted Ram Size. Default is Disabled
907 0x30:Disable, 0x31:4MB, 0x32:16MB, 0x33:64MB
908**/
909 UINT8 PramSize;
910
911/** Offset 0x01C1 - SaPreMemProductionRsvd
912 Reserved for SA Pre-Mem Production
913 $EN_DIS
914**/
915 UINT8 SaPreMemProductionRsvd[138];
916
917/** Offset 0x024B - DMI Max Link Speed
918 Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1
919 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed
920 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3
921**/
922 UINT8 DmiMaxLinkSpeed;
923
924/** Offset 0x024C - DMI Equalization Phase 2
925 DMI Equalization Phase 2. (0x0): Disable phase 2, (0x1): Enable phase 2, (0x2)(Default):
926 AUTO - Use the current default method
927 0:Disable phase2, 1:Enable phase2, 2:Auto
928**/
929 UINT8 DmiGen3EqPh2Enable;
930
931/** Offset 0x024D - DMI Gen3 Equalization Phase3
932 DMI Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method,
933 HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software
934 Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static
935 EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just
936 Phase1), Disabled(0x4): Bypass Equalization Phase 3
937 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3
938**/
939 UINT8 DmiGen3EqPh3Method;
940
941/** Offset 0x024E - Enable/Disable DMI GEN3 Static EQ Phase1 programming
942 Program DMI Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static
943 Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming
944 $EN_DIS
945**/
946 UINT8 DmiGen3ProgramStaticEq;
947
948/** Offset 0x024F - DeEmphasis control for DMI
949 DeEmphasis control for DMI. 0=-6dB, 1(Default)=-3.5 dB
950 0: -6dB, 1: -3.5dB
951**/
952 UINT8 DmiDeEmphasis;
953
954/** Offset 0x0250 - DMI Gen3 Root port preset values per lane
955 Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
956**/
957 UINT8 DmiGen3RootPortPreset[8];
958
959/** Offset 0x0258 - DMI Gen3 End port preset values per lane
960 Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane
961**/
962 UINT8 DmiGen3EndPointPreset[8];
963
964/** Offset 0x0260 - DMI Gen3 End port Hint values per lane
965 Used for programming DMI Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane
966**/
967 UINT8 DmiGen3EndPointHint[8];
968
969/** Offset 0x0268 - DMI Gen3 RxCTLEp per-Bundle control
970 Range: 0-15, 0 is default for each bundle, must be specified based upon platform design
971**/
972 UINT8 DmiGen3RxCtlePeaking[4];
973
974/** Offset 0x026C - BIST on Reset
975 Enable or Disable BIST on Reset; <b>0: Disable</b>; 1: Enable.
976 $EN_DIS
977**/
978 UINT8 BistOnReset;
979
980/** Offset 0x026D - Skip Stop PBET Timer Enable/Disable
981 Skip Stop PBET Timer; <b>0: Disable</b>; 1: Enable
982 $EN_DIS
983**/
984 UINT8 SkipStopPbet;
985
986/** Offset 0x026E - Over clocking support
987 Over clocking support; <b>0: Disable</b>; 1: Enable
988 $EN_DIS
989**/
990 UINT8 OcSupport;
991
992/** Offset 0x026F - Over clocking Lock
Tan, Lean Shengef41e8a2021-05-24 00:13:59 -0700[diff] [blame]993 Over clocking Lock Enable/Disable; 0: Disable; <b>1: Enable</b>
Martin Roth062c4a12021-02-14 13:58:31 -0700[diff] [blame]994 $EN_DIS
995**/
996 UINT8 OcLock;
997
998/** Offset 0x0270 - Maximum Core Turbo Ratio Override
999 Maximum core turbo ratio override allows to increase CPU core frequency beyond the
1000 fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-85
1001**/
1002 UINT8 CoreMaxOcRatio;
1003
1004/** Offset 0x0271 - Core voltage mode
1005 Core voltage mode; <b>0: Adaptive</b>; 1: Override.
1006 $EN_DIS
1007**/
1008 UINT8 CoreVoltageMode;
1009
1010/** Offset 0x0272 - Maximum clr turbo ratio override
1011 Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the
1012 fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-85
1013**/
1014 UINT8 RingMaxOcRatio;
1015
1016/** Offset 0x0273 - Hyper Threading Enable/Disable
1017 Enable or Disable Hyper Threading; 0: Disable; <b>1: Enable</b>
1018 $EN_DIS
1019**/
1020 UINT8 HyperThreading;
1021
1022/** Offset 0x0274 - Enable or Disable CPU Ratio Override
1023 Enable or Disable CPU Ratio Override; <b>0: Disable</b>; 1: Enable.
1024 $EN_DIS
1025**/
1026 UINT8 CpuRatioOverride;
1027
1028/** Offset 0x0275 - CPU ratio value
1029 CPU ratio value. Valid Range 0 to 63
1030**/
1031 UINT8 CpuRatio;
1032
1033/** Offset 0x0276 - Boot frequency
1034 Sets the boot frequency starting from reset vector.- 0: Maximum battery performance.-
1035 <b>1: Maximum non-turbo performance</b>.- 2: Turbo performance. @note If Turbo
1036 is selected BIOS will start in max non-turbo mode and switch to Turbo mode.
1037 0:0, 1:1, 2:2
1038**/
1039 UINT8 BootFrequency;
1040
1041/** Offset 0x0277 - Number of active cores
1042 Number of active cores(Depends on Number of cores). <b>0: All</b>;<b>1: 1 </b>;<b>2:
1043 2 </b>;<b>3: 3 </b>
1044 0:All, 1:1, 2:2, 3:3
1045**/
1046 UINT8 ActiveCoreCount;
1047
1048/** Offset 0x0278 - Processor Early Power On Configuration FCLK setting
1049 <b>0: 800 MHz (ULT/ULX)</b>. <b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.-
1050 2: 400 MHz. - 3: Reserved
1051 0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved
1052**/
1053 UINT8 FClkFrequency;
1054
1055/** Offset 0x0279 - Set JTAG power in C10 and deeper power states
1056 False: JTAG is power gated in C10 state. True: keeps the JTAG power up during C10
1057 and deeper power states for debug purpose. <b>0: False</b>; 1: True.
1058 0: False, 1: True
1059**/
1060 UINT8 JtagC10PowerGateDisable;
1061
1062/** Offset 0x027A - Enable or Disable VMX
1063 Enable or Disable VMX; 0: Disable; <b>1: Enable</b>.
1064 $EN_DIS
1065**/
1066 UINT8 VmxEnable;
1067
1068/** Offset 0x027B - AVX2 Ratio Offset
1069 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio
1070 vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B.
1071**/
1072 UINT8 Avx2RatioOffset;
1073
1074/** Offset 0x027C - AVX3 Ratio Offset
1075 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio
1076 vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B.
1077**/
1078 UINT8 Avx3RatioOffset;
1079
1080/** Offset 0x027D - BCLK Adaptive Voltage Enable
1081 When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. </b>0:
1082 Disable;<b> 1: Enable
1083 $EN_DIS
1084**/
1085 UINT8 BclkAdaptiveVoltage;
1086
1087/** Offset 0x027E - core voltage override
1088 The core voltage override which is applied to the entire range of cpu core frequencies.
1089 Valid Range 0 to 2000
1090**/
1091 UINT16 CoreVoltageOverride;
1092
1093/** Offset 0x0280 - Core Turbo voltage Adaptive
1094 Extra Turbo voltage applied to the cpu core when the cpu is operating in turbo mode.
1095 Valid Range 0 to 2000
1096**/
1097 UINT16 CoreVoltageAdaptive;
1098
1099/** Offset 0x0282 - Core Turbo voltage Offset
1100 The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000
1101**/
1102 UINT16 CoreVoltageOffset;
1103
1104/** Offset 0x0284 - Core PLL voltage offset
1105 Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
1106**/
1107 UINT8 CorePllVoltageOffset;
1108
1109/** Offset 0x0285 - Ring Downbin
1110 Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always
1111 lower than the core ratio.0: Disable; <b>1: Enable.</b>
1112 $EN_DIS
1113**/
1114 UINT8 RingDownBin;
1115
1116/** Offset 0x0286 - Ring voltage mode
1117 Ring voltage mode; <b>0: Adaptive</b>; 1: Override.
1118 $EN_DIS
1119**/
1120 UINT8 RingVoltageMode;
1121
1122/** Offset 0x0287 - TjMax Offset
1123 TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support
1124 TjMax in the range of 62 to 115 deg Celsius. Valid Range 10 - 63
1125**/
1126 UINT8 TjMaxOffset;
1127
1128/** Offset 0x0288 - Ring voltage override
1129 The ring voltage override which is applied to the entire range of cpu ring frequencies.
1130 Valid Range 0 to 2000
1131**/
1132 UINT16 RingVoltageOverride;
1133
1134/** Offset 0x028A - Ring Turbo voltage Adaptive
1135 Extra Turbo voltage applied to the cpu ring when the cpu is operating in turbo mode.
1136 Valid Range 0 to 2000
1137**/
1138 UINT16 RingVoltageAdaptive;
1139
1140/** Offset 0x028C - Ring Turbo voltage Offset
1141 The voltage offset applied to the ring while operating in turbo mode. Valid Range 0 to 1000
1142**/
1143 UINT16 RingVoltageOffset;
1144
1145/** Offset 0x028E
1146**/
1147 UINT8 UnusedUpdSpace7[2];
1148
1149/** Offset 0x0290 - ElixirSpringsPatchAddr
1150 Address of Elixir Springs Patches
1151**/
1152 UINT32 ElixirSpringsPatchAddr;
1153
1154/** Offset 0x0294 - ElixirSpringsPatchSize
1155 Size of Elixir Springs Patches
1156**/
1157 UINT32 ElixirSpringsPatchSize;
1158
1159/** Offset 0x0298 - CPU Run Control
1160 Enable, Disable or Do not configure CPU Run Control; 0: Disable; 1: Enable ; <b>2:
1161 No Change</b>
1162 0:Disabled, 1:Enabled, 2:No Change
1163**/
1164 UINT8 DebugInterfaceEnable;
1165
1166/** Offset 0x0299 - CPU Run Control Lock
1167 Lock or Unlock CPU Run Control; 0: Disable; <b>1: Enable</b>.
1168 $EN_DIS
1169**/
1170 UINT8 DebugInterfaceLockEnable;
1171
1172/** Offset 0x029A - BiosGuard
1173 Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable
1174 $EN_DIS
1175**/
1176 UINT8 BiosGuard;
1177
1178/** Offset 0x029B
1179**/
1180 UINT8 BiosGuardToolsInterface;
1181
1182/** Offset 0x029C - EnableSgx
1183 Enable/Disable. 0: Disable, Enable/Disable SGX feature, 1: enable, 2: Software Control
1184 0: Disable, 1: Enable, 2: Software Control
1185**/
1186 UINT8 EnableSgx;
1187
1188/** Offset 0x029D - Txt
1189 Enable/Disable. 0: Disable, Enable/Disable Txt feature, 1: enable
1190 $EN_DIS
1191**/
1192 UINT8 Txt;
1193
1194/** Offset 0x029E
1195**/
1196 UINT8 UnusedUpdSpace8[2];
1197
1198/** Offset 0x02A0 - PrmrrSize
1199 Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable
1200**/
1201 UINT32 PrmrrSize;
1202
1203/** Offset 0x02A4 - SinitMemorySize
1204 Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable
1205**/
1206 UINT32 SinitMemorySize;
1207
1208/** Offset 0x02A8 - TxtDprMemoryBase
1209 Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable
1210**/
1211 UINT64 TxtDprMemoryBase;
1212
1213/** Offset 0x02B0 - TxtHeapMemorySize
1214 Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable
1215**/
1216 UINT32 TxtHeapMemorySize;
1217
1218/** Offset 0x02B4 - TxtDprMemorySize
1219 Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable
1220**/
1221 UINT32 TxtDprMemorySize;
1222
1223/** Offset 0x02B8 - BiosAcmBase
1224 Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable
1225**/
1226 UINT32 BiosAcmBase;
1227
1228/** Offset 0x02BC - BiosAcmSize
1229 Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable
1230**/
1231 UINT32 BiosAcmSize;
1232
1233/** Offset 0x02C0 - ApStartupBase
1234 Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable
1235**/
1236 UINT32 ApStartupBase;
1237
1238/** Offset 0x02C4 - TgaSize
1239 Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable
1240**/
1241 UINT32 TgaSize;
1242
1243/** Offset 0x02C8 - TxtLcpPdBase
1244 Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable
1245**/
1246 UINT64 TxtLcpPdBase;
1247
1248/** Offset 0x02D0 - TxtLcpPdSize
1249 Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable
1250**/
1251 UINT64 TxtLcpPdSize;
1252
1253/** Offset 0x02D8 - IsTPMPresence
1254 IsTPMPresence default values
1255**/
1256 UINT8 IsTPMPresence;
1257
1258/** Offset 0x02D9 - ReservedSecurityPreMem
1259 Reserved for Security Pre-Mem
1260 $EN_DIS
1261**/
1262 UINT8 ReservedSecurityPreMem[6];
1263
1264/** Offset 0x02DF - PCH Master Clock Gating Control
1265 Provide a master control for clock gating for all PCH devices, 0: Disabled; 1: Default
1266 $EN_DIS
1267**/
1268 UINT8 PchMasterClockGating;
1269
1270/** Offset 0x02E0 - PCH Master Power Gating Control
1271 Provide a master control for pwoer gating for all PCH devices, 0: Disabled; 1: Default
1272 $EN_DIS
1273**/
1274 UINT8 PchMasterPowerGating;
1275
1276/** Offset 0x02E1
1277**/
1278 UINT8 UnusedUpdSpace9;
1279
1280/** Offset 0x02E2 - FIA Lane Reversal Enable/Disable config mask
1281 Enable/Disable. 0: Disable, 1: enable, Enable or disable Lane Reversal. If Enabled,
1282 the x2 FIA Lane will be flipped
1283**/
1284 UINT16 FiaLaneReversalEnable;
1285
1286/** Offset 0x02E4 - Enable PCH HSIO PCIE Rx Set Ctle
1287 Enable PCH PCIe Gen 3 Set CTLE Value.
1288**/
1289 UINT8 PchPcieHsioRxSetCtleEnable[24];
1290
1291/** Offset 0x02FC - PCH HSIO PCIE Rx Set Ctle Value
1292 PCH PCIe Gen 3 Set CTLE Value.
1293**/
1294 UINT8 PchPcieHsioRxSetCtle[24];
1295
1296/** Offset 0x0314 - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override
1297 0: Disable; 1: Enable.
1298**/
1299 UINT8 PchPcieHsioTxGen1DownscaleAmpEnable[24];
1300
1301/** Offset 0x032C - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value
1302 PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value.
1303**/
1304 UINT8 PchPcieHsioTxGen1DownscaleAmp[24];
1305
1306/** Offset 0x0344 - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override
1307 0: Disable; 1: Enable.
1308**/
1309 UINT8 PchPcieHsioTxGen2DownscaleAmpEnable[24];
1310
1311/** Offset 0x035C - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value
1312 PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value.
1313**/
1314 UINT8 PchPcieHsioTxGen2DownscaleAmp[24];
1315
1316/** Offset 0x0374 - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override
1317 0: Disable; 1: Enable.
1318**/
1319 UINT8 PchPcieHsioTxGen3DownscaleAmpEnable[24];
1320
1321/** Offset 0x038C - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value
1322 PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value.
1323**/
1324 UINT8 PchPcieHsioTxGen3DownscaleAmp[24];
1325
1326/** Offset 0x03A4 - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override
1327 0: Disable; 1: Enable.
1328**/
1329 UINT8 PchPcieHsioTxGen1DeEmphEnable[24];
1330
1331/** Offset 0x03BC - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value
1332 PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting.
1333**/
1334 UINT8 PchPcieHsioTxGen1DeEmph[24];
1335
1336/** Offset 0x03D4 - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override
1337 0: Disable; 1: Enable.
1338**/
1339 UINT8 PchPcieHsioTxGen2DeEmph3p5Enable[24];
1340
1341/** Offset 0x03EC - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value
1342 PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting.
1343**/
1344 UINT8 PchPcieHsioTxGen2DeEmph3p5[24];
1345
1346/** Offset 0x0404 - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override
1347 0: Disable; 1: Enable.
1348**/
1349 UINT8 PchPcieHsioTxGen2DeEmph6p0Enable[24];
1350
1351/** Offset 0x041C - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value
1352 PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting.
1353**/
1354 UINT8 PchPcieHsioTxGen2DeEmph6p0[24];
1355
1356/** Offset 0x0434 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
1357 0: Disable; 1: Enable.
1358**/
1359 UINT8 PchSataHsioRxGen1EqBoostMagEnable[8];
1360
1361/** Offset 0x043C - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value
1362 PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
1363**/
1364 UINT8 PchSataHsioRxGen1EqBoostMag[8];
1365
1366/** Offset 0x0444 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
1367 0: Disable; 1: Enable.
1368**/
1369 UINT8 PchSataHsioRxGen2EqBoostMagEnable[8];
1370
1371/** Offset 0x044C - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value
1372 PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
1373**/
1374 UINT8 PchSataHsioRxGen2EqBoostMag[8];
1375
1376/** Offset 0x0454 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
1377 0: Disable; 1: Enable.
1378**/
1379 UINT8 PchSataHsioRxGen3EqBoostMagEnable[8];
1380
1381/** Offset 0x045C - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value
1382 PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
1383**/
1384 UINT8 PchSataHsioRxGen3EqBoostMag[8];
1385
1386/** Offset 0x0464 - Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override
1387 0: Disable; 1: Enable.
1388**/
1389 UINT8 PchSataHsioTxGen1DownscaleAmpEnable[8];
1390
1391/** Offset 0x046C - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value
1392 PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value.
1393**/
1394 UINT8 PchSataHsioTxGen1DownscaleAmp[8];
1395
1396/** Offset 0x0474 - Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override
1397 0: Disable; 1: Enable.
1398**/
1399 UINT8 PchSataHsioTxGen2DownscaleAmpEnable[8];
1400
1401/** Offset 0x047C - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value
1402 PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value.
1403**/
1404 UINT8 PchSataHsioTxGen2DownscaleAmp[8];
1405
1406/** Offset 0x0484 - Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override
1407 0: Disable; 1: Enable.
1408**/
1409 UINT8 PchSataHsioTxGen3DownscaleAmpEnable[8];
1410
1411/** Offset 0x048C - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value
1412 PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value.
1413**/
1414 UINT8 PchSataHsioTxGen3DownscaleAmp[8];
1415
1416/** Offset 0x0494 - Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override
1417 0: Disable; 1: Enable.
1418**/
1419 UINT8 PchSataHsioTxGen1DeEmphEnable[8];
1420
1421/** Offset 0x049C - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting
1422 PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting.
1423**/
1424 UINT8 PchSataHsioTxGen1DeEmph[8];
1425
1426/** Offset 0x04A4 - Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
1427 0: Disable; 1: Enable.
1428**/
1429 UINT8 PchSataHsioTxGen2DeEmphEnable[8];
1430
1431/** Offset 0x04AC - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting
1432 PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting.
1433**/
1434 UINT8 PchSataHsioTxGen2DeEmph[8];
1435
1436/** Offset 0x04B4 - Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
1437 0: Disable; 1: Enable.
1438**/
1439 UINT8 PchSataHsioTxGen3DeEmphEnable[8];
1440
1441/** Offset 0x04BC - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting
1442 PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting.
1443**/
1444 UINT8 PchSataHsioTxGen3DeEmph[8];
1445
1446/** Offset 0x04C4 - PCH LPC Enhance the port 8xh decoding
1447 Original LPC only decodes one byte of port 80h.
1448 $EN_DIS
1449**/
1450 UINT8 PchLpcEnhancePort8xhDecoding;
1451
1452/** Offset 0x04C5 - PCH Port80 Route
1453 Control where the Port 80h cycles are sent, 0: LPC; 1: PCI.
1454 $EN_DIS
1455**/
1456 UINT8 PchPort80Route;
1457
1458/** Offset 0x04C6 - Enable SMBus ARP support
1459 Enable SMBus ARP support.
1460 $EN_DIS
1461**/
1462 UINT8 SmbusArpEnable;
1463
1464/** Offset 0x04C7 - Number of RsvdSmbusAddressTable.
1465 The number of elements in the RsvdSmbusAddressTable.
1466**/
1467 UINT8 PchNumRsvdSmbusAddresses;
1468
1469/** Offset 0x04C8 - SMBUS Base Address
1470 SMBUS Base Address (IO space).
1471**/
1472 UINT16 PchSmbusIoBase;
1473
1474/** Offset 0x04CA - Enable SMBus Alert Pin
1475 Enable SMBus Alert Pin.
1476 $EN_DIS
1477**/
1478 UINT8 PchSmbAlertEnable;
1479
1480/** Offset 0x04CB - Usage type for ClkSrc
1481 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use
1482 (free running), 0xFF: not used
1483**/
1484 UINT8 PcieClkSrcUsage[16];
1485
1486/** Offset 0x04DB - ClkReq-to-ClkSrc mapping
1487 Number of ClkReq signal assigned to ClkSrc
1488**/
1489 UINT8 PcieClkSrcClkReq[16];
1490
1491/** Offset 0x04EB
1492**/
1493 UINT8 UnusedUpdSpace10;
1494
1495/** Offset 0x04EC - Point of RsvdSmbusAddressTable
1496 Array of addresses reserved for non-ARP-capable SMBus devices.
1497**/
1498 UINT32 RsvdSmbusAddressTablePtr;
1499
1500/** Offset 0x04F0 - Enable PCIE RP Mask
1501 Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
1502 for port1, bit1 for port2, and so on.
1503**/
1504 UINT32 PcieRpEnableMask;
1505
1506/** Offset 0x04F4 - Debug Interfaces
1507 Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub,
1508 BIT2 - Not used.
1509**/
1510 UINT8 PcdDebugInterfaceFlags;
1511
1512/** Offset 0x04F5 - Serial Io Uart Debug Controller Number
1513 Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT
1514 Core interface, it cannot be used for debug purpose.
1515 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
1516**/
1517 UINT8 SerialIoUartDebugControllerNumber;
1518
1519/** Offset 0x04F6 - Serial Io Uart Debug Auto Flow
1520 Enables UART hardware flow control, CTS and RTS lines.
1521 $EN_DIS
1522**/
1523 UINT8 SerialIoUartDebugAutoFlow;
1524
1525/** Offset 0x04F7
1526**/
1527 UINT8 UnusedUpdSpace11;
1528
1529/** Offset 0x04F8 - Serial Io Uart Debug BaudRate
1530 Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600,
1531 19200, 57600, 115200, 460800, 921600, 1500000, 1843200, 3000000, 3686400, 6000000
1532**/
1533 UINT32 SerialIoUartDebugBaudRate;
1534
1535/** Offset 0x04FC - Serial Io Uart Debug Parity
1536 Set default Parity.
1537 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
1538**/
1539 UINT8 SerialIoUartDebugParity;
1540
1541/** Offset 0x04FD - Serial Io Uart Debug Stop Bits
1542 Set default stop bits.
1543 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits
1544**/
1545 UINT8 SerialIoUartDebugStopBits;
1546
1547/** Offset 0x04FE - Serial Io Uart Debug Data Bits
1548 Set default word length. 0: Default, 5,6,7,8
1549 5:5BITS, 6:6BITS, 7:7BITS, 8:8BITS
1550**/
1551 UINT8 SerialIoUartDebugDataBits;
1552
1553/** Offset 0x04FF
1554**/
1555 UINT8 UnusedUpdSpace12;
1556
1557/** Offset 0x0500 - Serial Io Uart Debug Mmio Base
1558 Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode
1559 = SerialIoUartPci.
1560**/
1561 UINT32 SerialIoUartDebugMmioBase;
1562
1563/** Offset 0x0504 - ISA Serial Base selection
1564 Select ISA Serial Base address. Default is 0x3F8.
1565 0:0x3F8, 1:0x2F8
1566**/
1567 UINT8 PcdIsaSerialUartBase;
1568
1569/** Offset 0x0505 - GT PLL voltage offset
1570 Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
1571**/
1572 UINT8 GtPllVoltageOffset;
1573
1574/** Offset 0x0506 - Ring PLL voltage offset
1575 Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
1576**/
1577 UINT8 RingPllVoltageOffset;
1578
1579/** Offset 0x0507 - System Agent PLL voltage offset
1580 Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
1581**/
1582 UINT8 SaPllVoltageOffset;
1583
1584/** Offset 0x0508 - Memory Controller PLL voltage offset
1585 Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
1586**/
1587 UINT8 McPllVoltageOffset;
1588
1589/** Offset 0x0509 - MRC Safe Config
1590 Enables/Disable MRC Safe Config
1591 $EN_DIS
1592**/
1593 UINT8 MrcSafeConfig;
1594
1595/** Offset 0x050A - TCSS Thunderbolt PCIE Root Port 0 Enable
1596 Set TCSS Thunderbolt PCIE Root Port 0. 0:Disabled 1:Enabled
1597 $EN_DIS
1598**/
1599 UINT8 TcssItbtPcie0En;
1600
1601/** Offset 0x050B - TCSS Thunderbolt PCIE Root Port 1 Enable
1602 Set TCSS Thunderbolt PCIE Root Port 1. 0:Disabled 1:Enabled
1603 $EN_DIS
1604**/
1605 UINT8 TcssItbtPcie1En;
1606
1607/** Offset 0x050C - TCSS Thunderbolt PCIE Root Port 2 Enable
1608 Set TCSS Thunderbolt PCIE Root Port 2. 0:Disabled 1:Enabled
1609 $EN_DIS
1610**/
1611 UINT8 TcssItbtPcie2En;
1612
1613/** Offset 0x050D - TCSS Thunderbolt PCIE Root Port 3 Enable
1614 Set TCSS Thunderbolt PCIE Root Port 3. 0:Disabled 1:Enabled
1615 $EN_DIS
1616**/
1617 UINT8 TcssItbtPcie3En;
1618
1619/** Offset 0x050E - TCSS USB HOST (xHCI) Enable
1620 Set TCSS XHCI. 0:Disabled 1:Enabled - Must be enabled if xDCI is enabled below
1621 $EN_DIS
1622**/
1623 UINT8 TcssXhciEn;
1624
1625/** Offset 0x050F - TCSS USB DEVICE (xDCI) Enable
1626 Set TCSS XDCI. 0:Disabled 1:Enabled - xHCI must be enabled if xDCI is enabled
1627 $EN_DIS
1628**/
1629 UINT8 TcssXdciEn;
1630
1631/** Offset 0x0510 - TCSS DMA0 Enable
1632 Set TCSS DMA0. 0:Disabled 1:Enabled
1633 $EN_DIS
1634**/
1635 UINT8 TcssDma0En;
1636
1637/** Offset 0x0511 - TCSS DMA1 Enable
1638 Set TCSS DMA1. 0:Disabled 1:Enabled
1639 $EN_DIS
1640**/
1641 UINT8 TcssDma1En;
1642
1643/** Offset 0x0512 - PcdSerialDebugBaudRate
1644 Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200.
1645 3:9600, 4:19200, 6:56700, 7:115200
1646**/
1647 UINT8 PcdSerialDebugBaudRate;
1648
1649/** Offset 0x0513 - HobBufferSize
1650 Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB
1651 total HOB size).
1652 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value
1653**/
1654 UINT8 HobBufferSize;
1655
1656/** Offset 0x0514 - Early Command Training
1657 Enables/Disable Early Command Training
1658 $EN_DIS
1659**/
1660 UINT8 ECT;
1661
1662/** Offset 0x0515 - SenseAmp Offset Training
1663 Enables/Disable SenseAmp Offset Training
1664 $EN_DIS
1665**/
1666 UINT8 SOT;
1667
1668/** Offset 0x0516 - Early ReadMPR Timing Centering 2D
1669 Enables/Disable Early ReadMPR Timing Centering 2D
1670 $EN_DIS
1671**/
1672 UINT8 ERDMPRTC2D;
1673
1674/** Offset 0x0517 - Read MPR Training
1675 Enables/Disable Read MPR Training
1676 $EN_DIS
1677**/
1678 UINT8 RDMPRT;
1679
1680/** Offset 0x0518 - Receive Enable Training
1681 Enables/Disable Receive Enable Training
1682 $EN_DIS
1683**/
1684 UINT8 RCVET;
1685
1686/** Offset 0x0519 - Jedec Write Leveling
1687 Enables/Disable Jedec Write Leveling
1688 $EN_DIS
1689**/
1690 UINT8 JWRL;
1691
1692/** Offset 0x051A - Early Write Time Centering 2D
1693 Enables/Disable Early Write Time Centering 2D
1694 $EN_DIS
1695**/
1696 UINT8 EWRTC2D;
1697
1698/** Offset 0x051B - Early Read Time Centering 2D
1699 Enables/Disable Early Read Time Centering 2D
1700 $EN_DIS
1701**/
1702 UINT8 ERDTC2D;
1703
1704/** Offset 0x051C - Write Timing Centering 1D
1705 Enables/Disable Write Timing Centering 1D
1706 $EN_DIS
1707**/
1708 UINT8 WRTC1D;
1709
1710/** Offset 0x051D - Write Voltage Centering 1D
1711 Enables/Disable Write Voltage Centering 1D
1712 $EN_DIS
1713**/
1714 UINT8 WRVC1D;
1715
1716/** Offset 0x051E - Read Timing Centering 1D
1717 Enables/Disable Read Timing Centering 1D
1718 $EN_DIS
1719**/
1720 UINT8 RDTC1D;
1721
1722/** Offset 0x051F - Dimm ODT Training
1723 Enables/Disable Dimm ODT Training
1724 $EN_DIS
1725**/
1726 UINT8 DIMMODTT;
1727
1728/** Offset 0x0520 - DIMM RON Training
1729 Enables/Disable DIMM RON Training
1730 $EN_DIS
1731**/
1732 UINT8 DIMMRONT;
1733
1734/** Offset 0x0521 - Write Drive Strength/Equalization 2D
1735 Enables/Disable Write Drive Strength/Equalization 2D
1736 $EN_DIS
1737**/
1738 UINT8 WRDSEQT;
1739
1740/** Offset 0x0522 - Write Slew Rate Training
1741 Enables/Disable Write Slew Rate Training
1742 $EN_DIS
1743**/
1744 UINT8 WRSRT;
1745
1746/** Offset 0x0523 - Read ODT Training
1747 Enables/Disable Read ODT Training
1748 $EN_DIS
1749**/
1750 UINT8 RDODTT;
1751
1752/** Offset 0x0524 - Read Equalization Training
1753 Enables/Disable Read Equalization Training
1754 $EN_DIS
1755**/
1756 UINT8 RDEQT;
1757
1758/** Offset 0x0525 - Read Amplifier Training
1759 Enables/Disable Read Amplifier Training
1760 $EN_DIS
1761**/
1762 UINT8 RDAPT;
1763
1764/** Offset 0x0526 - Write Timing Centering 2D
1765 Enables/Disable Write Timing Centering 2D
1766 $EN_DIS
1767**/
1768 UINT8 WRTC2D;
1769
1770/** Offset 0x0527 - Read Timing Centering 2D
1771 Enables/Disable Read Timing Centering 2D
1772 $EN_DIS
1773**/
1774 UINT8 RDTC2D;
1775
1776/** Offset 0x0528 - Write Voltage Centering 2D
1777 Enables/Disable Write Voltage Centering 2D
1778 $EN_DIS
1779**/
1780 UINT8 WRVC2D;
1781
1782/** Offset 0x0529 - Read Voltage Centering 2D
1783 Enables/Disable Read Voltage Centering 2D
1784 $EN_DIS
1785**/
1786 UINT8 RDVC2D;
1787
1788/** Offset 0x052A - Command Voltage Centering
1789 Enables/Disable Command Voltage Centering
1790 $EN_DIS
1791**/
1792 UINT8 CMDVC;
1793
1794/** Offset 0x052B - Late Command Training
1795 Enables/Disable Late Command Training
1796 $EN_DIS
1797**/
1798 UINT8 LCT;
1799
1800/** Offset 0x052C - Round Trip Latency Training
1801 Enables/Disable Round Trip Latency Training
1802 $EN_DIS
1803**/
1804 UINT8 RTL;
1805
1806/** Offset 0x052D - Turn Around Timing Training
1807 Enables/Disable Turn Around Timing Training
1808 $EN_DIS
1809**/
1810 UINT8 TAT;
1811
1812/** Offset 0x052E - Receive Enable Centering 1D
1813 Enables/Disable Receive Enable Centering 1D
1814 $EN_DIS
1815**/
1816 UINT8 RCVENC1D;
1817
1818/** Offset 0x052F - Rank Margin Tool
1819 Enable/disable Rank Margin Tool.
1820 $EN_DIS
1821**/
1822 UINT8 RMT;
1823
1824/** Offset 0x0530 - Margin Limit Check
1825 Margin Limit Check. Choose level of margin check
1826 0:Disable, 1:L1, 2:L2, 3:Both
1827**/
1828 UINT8 MarginLimitCheck;
1829
1830/** Offset 0x0531
1831**/
1832 UINT8 UnusedUpdSpace13;
1833
1834/** Offset 0x0532 - Margin Limit L2
1835 % of L1 check for margin limit check
1836**/
1837 UINT16 MarginLimitL2;
1838
1839/** Offset 0x0534 - Memory Test
1840 Enables/Disable Memory Test
1841 $EN_DIS
1842**/
1843 UINT8 MEMTST;
1844
1845/** Offset 0x0535 - DIMM SPD Alias Test
1846 Enables/Disable DIMM SPD Alias Test
1847 $EN_DIS
1848**/
1849 UINT8 ALIASCHK;
1850
1851/** Offset 0x0536 - Retrain Margin Check
1852 Enables/Disable Retrain Margin Check
1853 $EN_DIS
1854**/
1855 UINT8 RMC;
1856
1857/** Offset 0x0537 - Write Drive Strength Up/Dn independently
1858 Enables/Disable Write Drive Strength Up/Dn independently
1859 $EN_DIS
1860**/
1861 UINT8 WRDSUDT;
1862
1863/** Offset 0x0538 - Command Slew Rate Training
1864 Enables/Disable Command Slew Rate Training
1865 $EN_DIS
1866**/
1867 UINT8 CMDSR;
1868
1869/** Offset 0x0539 - Command Drive Strength and Equalization 2D
1870 Enables/Disable Command Drive Strength and Equalization 2D
1871 $EN_DIS
1872**/
1873 UINT8 CMDDSEQ;
1874
1875/** Offset 0x053A - Command Normalization
1876 Enables/Disable Command Normalization
1877 $EN_DIS
1878**/
1879 UINT8 CMDNORM;
1880
1881/** Offset 0x053B - Early DQ Write Drive Strength and Equalization Training
1882 Enables/Disable Early DQ Write Drive Strength and Equalization Training
1883 $EN_DIS
1884**/
1885 UINT8 EWRDSEQ;
1886
1887/** Offset 0x053C - Read Voltage Centering
1888 Enables/Disable Read Voltage Centering
1889 $EN_DIS
1890**/
1891 UINT8 RDVC1D;
1892
1893/** Offset 0x053D - Write TCO Comp Training
1894 Enables/Disable Write TCO Comp Training
1895 $EN_DIS
1896**/
1897 UINT8 TXTCO;
1898
1899/** Offset 0x053E - Clock TCO Comp Training
1900 Enables/Disable Clock TCO Comp Training
1901 $EN_DIS
1902**/
1903 UINT8 CLKTCO;
1904
1905/** Offset 0x053F - Dimm ODT CA Training
1906 Enables/Disable Dimm ODT CA Training
1907 $EN_DIS
1908**/
1909 UINT8 DIMMODTCA;
1910
1911/** Offset 0x0540 - Write TCO Dqs Training
1912 Enables/Disable Write TCO Dqs Training
1913 $EN_DIS
1914**/
1915 UINT8 TXTCODQS;
1916
1917/** Offset 0x0541 - Duty Cycle Correction
1918 Enables/Disable Duty Cycle Correction
1919 $EN_DIS
1920**/
1921 UINT8 DCC;
1922
1923/** Offset 0x0542 - DQ DFE Training
1924 Enable/Disable DQ DFE Training
1925 $EN_DIS
1926**/
1927 UINT8 DQDFE;
1928
1929/** Offset 0x0543 - Sense Amplifier Correction Training
1930 Enable/Disable Sense Amplifier Correction Training
1931 $EN_DIS
1932**/
1933 UINT8 SOTC;
1934
1935/** Offset 0x0544 - ECC Support
1936 Enables/Disable ECC Support
1937 $EN_DIS
1938**/
1939 UINT8 EccSupport;
1940
1941/** Offset 0x0545 - Memory Remap
1942 Enables/Disable Memory Remap
1943 $EN_DIS
1944**/
1945 UINT8 RemapEnable;
1946
1947/** Offset 0x0546 - MRC Time Measure
1948 Enable/Disable MRC Time Measure
1949 $EN_DIS
1950**/
1951 UINT8 MrcTimeMeasure;
1952
1953/** Offset 0x0547 - MRC Fast Boot
1954 Enable/Disable MRC Fast flow
1955 $EN_DIS
1956**/
1957 UINT8 MrcFastBoot;
1958
1959/** Offset 0x0548 - MRC Force Training on Warm
1960 Enables/Disable the MRC training on warm boot
1961 $EN_DIS
1962**/
1963 UINT8 MrcTrainOnWarm;
1964
1965/** Offset 0x0549 - Rank Interleave support
1966 Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at
1967 the same time.
1968 $EN_DIS
1969**/
1970 UINT8 RankInterleave;
1971
1972/** Offset 0x054A - Enhanced Interleave support
1973 Enables/Disable Enhanced Interleave support
1974 $EN_DIS
1975**/
1976 UINT8 EnhancedInterleave;
1977
1978/** Offset 0x054B - Memory Trace
1979 Enable Memory Trace of Ch 0 to Ch 1 using Stacked Mode. Both channels must be of
1980 equal size. This option may change TOLUD and REMAP values as needed.
1981 $EN_DIS
1982**/
1983 UINT8 MemoryTrace;
1984
1985/** Offset 0x054C - Ch Hash Support
1986 Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode
1987 $EN_DIS
1988**/
1989 UINT8 ChHashEnable;
1990
1991/** Offset 0x054D - Extern Therm Status
1992 Enables/Disable Extern Therm Status
1993 $EN_DIS
1994**/
1995 UINT8 EnableExtts;
1996
1997/** Offset 0x054E - Closed Loop Therm Manage
1998 Enables/Disable Closed Loop Therm Manage
1999 $EN_DIS
2000**/
2001 UINT8 EnableCltm;
2002
2003/** Offset 0x054F - Open Loop Therm Manage
2004 Enables/Disable Open Loop Therm Manage
2005 $EN_DIS
2006**/
2007 UINT8 EnableOltm;
2008
2009/** Offset 0x0550 - DDR PowerDown and idle counter
2010 Enables/Disable DDR PowerDown and idle counter
2011 $EN_DIS
2012**/
2013 UINT8 EnablePwrDn;
2014
2015/** Offset 0x0551 - DDR PowerDown and idle counter - LPDDR
2016 Enables/Disable DDR PowerDown and idle counter(For LPDDR Only)
2017 $EN_DIS
2018**/
2019 UINT8 EnablePwrDnLpddr;
2020
2021/** Offset 0x0552 - Use user provided power weights, scale factor, and channel power floor values
2022 Enables/Disable Use user provided power weights, scale factor, and channel power
2023 floor values
2024 $EN_DIS
2025**/
2026 UINT8 UserPowerWeightsEn;
2027
2028/** Offset 0x0553 - RAPL PL Lock
2029 Enables/Disable RAPL PL Lock
2030 $EN_DIS
2031**/
2032 UINT8 RaplLim2Lock;
2033
2034/** Offset 0x0554 - RAPL PL 2 enable
2035 Enables/Disable RAPL PL 2 enable
2036 $EN_DIS
2037**/
2038 UINT8 RaplLim2Ena;
2039
2040/** Offset 0x0555 - RAPL PL 1 enable
2041 Enables/Disable RAPL PL 1 enable
2042 $EN_DIS
2043**/
2044 UINT8 RaplLim1Ena;
2045
2046/** Offset 0x0556 - SelfRefresh Enable
2047 Enables/Disable SelfRefresh Enable
2048 $EN_DIS
2049**/
2050 UINT8 SrefCfgEna;
2051
2052/** Offset 0x0557 - Throttler CKEMin Defeature - LPDDR
2053 Enables/Disable Throttler CKEMin Defeature(For LPDDR Only)
2054 $EN_DIS
2055**/
2056 UINT8 ThrtCkeMinDefeatLpddr;
2057
2058/** Offset 0x0558 - Throttler CKEMin Defeature
2059 Enables/Disable Throttler CKEMin Defeature
2060 $EN_DIS
2061**/
2062 UINT8 ThrtCkeMinDefeat;
2063
2064/** Offset 0x0559 - Enable RH Prevention
2065 Enables/Disable RH Prevention
2066 $EN_DIS
2067**/
2068 UINT8 RhPrevention;
2069
2070/** Offset 0x055A - Exit On Failure (MRC)
2071 Enables/Disable Exit On Failure (MRC)
2072 $EN_DIS
2073**/
2074 UINT8 ExitOnFailure;
2075
2076/** Offset 0x055B - LPDDR Thermal Sensor
2077 Enables/Disable LPDDR Thermal Sensor
2078 $EN_DIS
2079**/
2080 UINT8 DdrThermalSensor;
2081
2082/** Offset 0x055C - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP
2083 Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP
2084 $EN_DIS
2085**/
2086 UINT8 Ddr4DdpSharedClock;
2087
2088/** Offset 0x055D - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP
2089 ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP
2090 $EN_DIS
2091**/
2092 UINT8 Ddr4DdpSharedZq;
2093
2094/** Offset 0x055E
2095**/
2096 UINT8 UnusedUpdSpace14[2];
2097
2098/** Offset 0x0560 - Base reference clock value
2099 Base reference clock value, in Hertz(Default is 125Hz)
2100 100000000:100Hz, 125000000:125Hz, 167000000:167Hz, 250000000:250Hz
2101**/
2102 UINT32 BClkFrequency;
2103
2104/** Offset 0x0564 - Ch Hash Interleaved Bit
2105 Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave
2106 the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8
2107 0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13
2108**/
2109 UINT8 ChHashInterleaveBit;
2110
2111/** Offset 0x0565
2112**/
2113 UINT8 UnusedUpdSpace15;
2114
2115/** Offset 0x0566 - Ch Hash Mask
2116 Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to
2117 BITS [19:6] Default is 0x30CC
2118**/
2119 UINT16 ChHashMask;
2120
2121/** Offset 0x0568 - Extended Bank Hashing
2122 Eanble/Disable ExtendedBankHashing
2123 $EN_DIS
2124**/
2125 UINT8 ExtendedBankHashing;
2126
2127/** Offset 0x0569 - Energy Scale Factor
2128 Energy Scale Factor, Default is 4
2129**/
2130 UINT8 EnergyScaleFact;
2131
2132/** Offset 0x056A - EPG DIMM Idd3N
2133 Active standby current (Idd3N) in milliamps from datasheet. Must be calculated on
2134 a per DIMM basis. Default is 26
2135**/
2136 UINT16 Idd3n;
2137
2138/** Offset 0x056C - EPG DIMM Idd3P
2139 Active power-down current (Idd3P) in milliamps from datasheet. Must be calculated
2140 on a per DIMM basis. Default is 11
2141**/
2142 UINT16 Idd3p;
2143
2144/** Offset 0x056E - RH Activation Probability
2145 RH Activation Probability, Probability value is 1/2^(inputvalue)
2146**/
2147 UINT8 RhActProbability;
2148
2149/** Offset 0x056F - RAPL PL 2 WindowX
2150 Power PL 2 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def)
2151**/
2152 UINT8 RaplLim2WindX;
2153
2154/** Offset 0x0570 - RAPL PL 2 WindowY
2155 Power PL 2 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def)
2156**/
2157 UINT8 RaplLim2WindY;
2158
2159/** Offset 0x0571 - RAPL PL 1 WindowX
2160 Power PL 1 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def)
2161**/
2162 UINT8 RaplLim1WindX;
2163
2164/** Offset 0x0572 - RAPL PL 1 WindowY
2165 Power PL 1 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def)
2166**/
2167 UINT8 RaplLim1WindY;
2168
2169/** Offset 0x0573
2170**/
2171 UINT8 UnusedUpdSpace16;
2172
2173/** Offset 0x0574 - RAPL PL 2 Power
2174 range[0;2^14-1]= [2047.875;0]in W, (224= Def)
2175**/
2176 UINT16 RaplLim2Pwr;
2177
2178/** Offset 0x0576 - RAPL PL 1 Power
2179 range[0;2^14-1]= [2047.875;0]in W, (224= Def)
2180**/
2181 UINT16 RaplLim1Pwr;
2182
2183/** Offset 0x0578 - Warm Threshold Ch0 Dimm0
2184 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255
2185**/
2186 UINT8 WarmThresholdCh0Dimm0;
2187
2188/** Offset 0x0579 - Warm Threshold Ch0 Dimm1
2189 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255
2190**/
2191 UINT8 WarmThresholdCh0Dimm1;
2192
2193/** Offset 0x057A - Warm Threshold Ch1 Dimm0
2194 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255
2195**/
2196 UINT8 WarmThresholdCh1Dimm0;
2197
2198/** Offset 0x057B - Warm Threshold Ch1 Dimm1
2199 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255
2200**/
2201 UINT8 WarmThresholdCh1Dimm1;
2202
2203/** Offset 0x057C - Hot Threshold Ch0 Dimm0
2204 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255
2205**/
2206 UINT8 HotThresholdCh0Dimm0;
2207
2208/** Offset 0x057D - Hot Threshold Ch0 Dimm1
2209 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255
2210**/
2211 UINT8 HotThresholdCh0Dimm1;
2212
2213/** Offset 0x057E - Hot Threshold Ch1 Dimm0
2214 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255
2215**/
2216 UINT8 HotThresholdCh1Dimm0;
2217
2218/** Offset 0x057F - Hot Threshold Ch1 Dimm1
2219 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255
2220**/
2221 UINT8 HotThresholdCh1Dimm1;
2222
2223/** Offset 0x0580 - Warm Budget Ch0 Dimm0
2224 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
2225**/
2226 UINT8 WarmBudgetCh0Dimm0;
2227
2228/** Offset 0x0581 - Warm Budget Ch0 Dimm1
2229 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
2230**/
2231 UINT8 WarmBudgetCh0Dimm1;
2232
2233/** Offset 0x0582 - Warm Budget Ch1 Dimm0
2234 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
2235**/
2236 UINT8 WarmBudgetCh1Dimm0;
2237
2238/** Offset 0x0583 - Warm Budget Ch1 Dimm1
2239 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
2240**/
2241 UINT8 WarmBudgetCh1Dimm1;
2242
2243/** Offset 0x0584 - Hot Budget Ch0 Dimm0
2244 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
2245**/
2246 UINT8 HotBudgetCh0Dimm0;
2247
2248/** Offset 0x0585 - Hot Budget Ch0 Dimm1
2249 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
2250**/
2251 UINT8 HotBudgetCh0Dimm1;
2252
2253/** Offset 0x0586 - Hot Budget Ch1 Dimm0
2254 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
2255**/
2256 UINT8 HotBudgetCh1Dimm0;
2257
2258/** Offset 0x0587 - Hot Budget Ch1 Dimm1
2259 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
2260**/
2261 UINT8 HotBudgetCh1Dimm1;
2262
2263/** Offset 0x0588 - Idle Energy Ch0Dimm0
2264 Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
2265**/
2266 UINT8 IdleEnergyCh0Dimm0;
2267
2268/** Offset 0x0589 - Idle Energy Ch0Dimm1
2269 Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
2270**/
2271 UINT8 IdleEnergyCh0Dimm1;
2272
2273/** Offset 0x058A - Idle Energy Ch1Dimm0
2274 Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
2275**/
2276 UINT8 IdleEnergyCh1Dimm0;
2277
2278/** Offset 0x058B - Idle Energy Ch1Dimm1
2279 Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
2280**/
2281 UINT8 IdleEnergyCh1Dimm1;
2282
2283/** Offset 0x058C - PowerDown Energy Ch0Dimm0
2284 PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)
2285**/
2286 UINT8 PdEnergyCh0Dimm0;
2287
2288/** Offset 0x058D - PowerDown Energy Ch0Dimm1
2289 PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)
2290**/
2291 UINT8 PdEnergyCh0Dimm1;
2292
2293/** Offset 0x058E - PowerDown Energy Ch1Dimm0
2294 PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)
2295**/
2296 UINT8 PdEnergyCh1Dimm0;
2297
2298/** Offset 0x058F - PowerDown Energy Ch1Dimm1
2299 PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)
2300**/
2301 UINT8 PdEnergyCh1Dimm1;
2302
2303/** Offset 0x0590 - Activate Energy Ch0Dimm0
2304 Activate Energy Contribution, range[255;0],(172= Def)
2305**/
2306 UINT8 ActEnergyCh0Dimm0;
2307
2308/** Offset 0x0591 - Activate Energy Ch0Dimm1
2309 Activate Energy Contribution, range[255;0],(172= Def)
2310**/
2311 UINT8 ActEnergyCh0Dimm1;
2312
2313/** Offset 0x0592 - Activate Energy Ch1Dimm0
2314 Activate Energy Contribution, range[255;0],(172= Def)
2315**/
2316 UINT8 ActEnergyCh1Dimm0;
2317
2318/** Offset 0x0593 - Activate Energy Ch1Dimm1
2319 Activate Energy Contribution, range[255;0],(172= Def)
2320**/
2321 UINT8 ActEnergyCh1Dimm1;
2322
2323/** Offset 0x0594 - Read Energy Ch0Dimm0
2324 Read Energy Contribution, range[255;0],(212= Def)
2325**/
2326 UINT8 RdEnergyCh0Dimm0;
2327
2328/** Offset 0x0595 - Read Energy Ch0Dimm1
2329 Read Energy Contribution, range[255;0],(212= Def)
2330**/
2331 UINT8 RdEnergyCh0Dimm1;
2332
2333/** Offset 0x0596 - Read Energy Ch1Dimm0
2334 Read Energy Contribution, range[255;0],(212= Def)
2335**/
2336 UINT8 RdEnergyCh1Dimm0;
2337
2338/** Offset 0x0597 - Read Energy Ch1Dimm1
2339 Read Energy Contribution, range[255;0],(212= Def)
2340**/
2341 UINT8 RdEnergyCh1Dimm1;
2342
2343/** Offset 0x0598 - Write Energy Ch0Dimm0
2344 Write Energy Contribution, range[255;0],(221= Def)
2345**/
2346 UINT8 WrEnergyCh0Dimm0;
2347
2348/** Offset 0x0599 - Write Energy Ch0Dimm1
2349 Write Energy Contribution, range[255;0],(221= Def)
2350**/
2351 UINT8 WrEnergyCh0Dimm1;
2352
2353/** Offset 0x059A - Write Energy Ch1Dimm0
2354 Write Energy Contribution, range[255;0],(221= Def)
2355**/
2356 UINT8 WrEnergyCh1Dimm0;
2357
2358/** Offset 0x059B - Write Energy Ch1Dimm1
2359 Write Energy Contribution, range[255;0],(221= Def)
2360**/
2361 UINT8 WrEnergyCh1Dimm1;
2362
2363/** Offset 0x059C - Throttler CKEMin Timer
2364 Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4).
2365 Dfault is 0x30
2366**/
2367 UINT8 ThrtCkeMinTmr;
2368
2369/** Offset 0x059D - Cke Rank Mapping
2370 Bits [7:4] - Channel 1, bits [3:0] - Channel 0. <b>0xAA=Default</b> Bit [i] specifies
2371 which rank CKE[i] goes to.
2372**/
2373 UINT8 CkeRankMapping;
2374
2375/** Offset 0x059E - Rapl Power Floor Ch0
2376 Power budget ,range[255;0],(0= 5.3W Def)
2377**/
2378 UINT8 RaplPwrFlCh0;
2379
2380/** Offset 0x059F - Rapl Power Floor Ch1
2381 Power budget ,range[255;0],(0= 5.3W Def)
2382**/
2383 UINT8 RaplPwrFlCh1;
2384
2385/** Offset 0x05A0 - Command Rate Support
2386 CMD Rate and Limit Support Option. NOTE: ONLY supported in 1N Mode, Default is 3 CMDs
2387 0:Disable, 1:1 CMD, 2:2 CMDS, 3:3 CMDS, 4:4 CMDS, 5:5 CMDS, 6:6 CMDS, 7:7 CMDS
2388**/
2389 UINT8 EnCmdRate;
2390
2391/** Offset 0x05A1 - REFRESH_2X_MODE
2392 0- (Default)Disabled 1-iMC enables 2xRef when Warm and Hot 2- iMC enables 2xRef when Hot
2393 0:Disable, 1:Enabled for WARM or HOT, 2:Enabled HOT only
2394**/
2395 UINT8 Refresh2X;
2396
2397/** Offset 0x05A2 - Energy Performance Gain
2398 Enable/disable(default) Energy Performance Gain.
2399 $EN_DIS
2400**/
2401 UINT8 EpgEnable;
2402
2403/** Offset 0x05A3 - Row Hammer Solution
2404 Type of method used to prevent Row Hammer. Default is 2x Refresh
2405 0:Hardware RHP, 1:2x Refresh
2406**/
2407 UINT8 RhSolution;
2408
2409/** Offset 0x05A4 - User Manual Threshold
2410 Disabled: Predefined threshold will be used.\n
2411 Enabled: User Input will be used.
2412 $EN_DIS
2413**/
2414 UINT8 UserThresholdEnable;
2415
2416/** Offset 0x05A5 - User Manual Budget
2417 Disabled: Configuration of memories will defined the Budget value.\n
2418 Enabled: User Input will be used.
2419 $EN_DIS
2420**/
2421 UINT8 UserBudgetEnable;
2422
2423/** Offset 0x05A6 - Power Down Mode
2424 This option controls command bus tristating during idle periods
2425 0x0:No Power Down, 0x1:APD, 0x6:PPD DLL OFF, 0xFF:Auto
2426**/
2427 UINT8 PowerDownMode;
2428
2429/** Offset 0x05A7 - TcritMax
2430 Maximum Critical Temperature in Centigrade of the On-DIMM Thermal Sensor. TCRITMax
2431 has to be greater than THIGHMax .\n
2432 Critical temperature will be TcritMax
2433**/
2434 UINT8 TsodTcritMax;
2435
2436/** Offset 0x05A8 - Event mode
2437 Disable:Comparator mode.\n
2438 Enable:Interrupt mode
2439 $EN_DIS
2440**/
2441 UINT8 TsodEventMode;
2442
2443/** Offset 0x05A9 - EVENT polarity
2444 Disable:Active LOW.\n
2445 Enable:Active HIGH
2446 $EN_DIS
2447**/
2448 UINT8 TsodEventPolarity;
2449
2450/** Offset 0x05AA - Critical event only
2451 Disable:Trips on alarm or critical.\n
2452 Enable:Trips only if criticaal temperature is reached
2453 $EN_DIS
2454**/
2455 UINT8 TsodCriticalEventOnly;
2456
2457/** Offset 0x05AB - Event output control
2458 Disable:Event output disable.\n
2459 Enable:Event output enabled
2460 $EN_DIS
2461**/
2462 UINT8 TsodEventOutputControl;
2463
2464/** Offset 0x05AC - Alarm window lock bit
2465 Disable:Alarm trips are not locked and can be changed.\n
2466 Enable:Alarm trips are locked and cannot be changed
2467 $EN_DIS
2468**/
2469 UINT8 TsodAlarmwindowLockBit;
2470
2471/** Offset 0x05AD - Critical trip lock bit
2472 Disable:Critical trip is not locked and can be changed.\n
2473 Enable:Critical trip is locked and cannot be changed
2474 $EN_DIS
2475**/
2476 UINT8 TsodCriticaltripLockBit;
2477
2478/** Offset 0x05AE - Shutdown mode
2479 Disable:Temperature sensor enable.\n
2480 Enable:Temperature sensor disable
2481 $EN_DIS
2482**/
2483 UINT8 TsodShutdownMode;
2484
2485/** Offset 0x05AF - ThighMax
2486 Thigh = ThighMax (Default is 93)
2487**/
2488 UINT8 TsodThigMax;
2489
2490/** Offset 0x05B0 - User Manual Thig and Tcrit
2491 Disabled(Default): Temperature will be given by the configuration of memories and
2492 1x or 2xrefresh rate.\n
2493 Enabled: User Input will define for Thigh and Tcrit.
2494 $EN_DIS
2495**/
2496 UINT8 TsodManualEnable;
2497
2498/** Offset 0x05B1 - Force OLTM or 2X Refresh when needed
2499 Disabled(Default): = Force OLTM.\n
2500 Enabled: = Force 2x Refresh.
2501 $EN_DIS
2502**/
2503 UINT8 ForceOltmOrRefresh2x;
2504
2505/** Offset 0x05B2 - Pwr Down Idle Timer
2506 The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means
2507 AUTO: 64 for ULX/ULT, 128 for DT/Halo
2508**/
2509 UINT8 PwdwnIdleCounter;
2510
2511/** Offset 0x05B3 - Page Close Idle Timeout
2512 This option controls Page Close Idle Timeout
2513 0:Enabled, 1:Disabled
2514**/
2515 UINT8 DisPgCloseIdleTimeout;
2516
2517/** Offset 0x05B4 - Bitmask of ranks that have CA bus terminated
2518 Offset 225 LPDDR4: Bitmask of ranks that have CA bus terminated. <b>0x01=Default,
2519 Rank0 is terminating and Rank1 is non-terminating</b>
2520**/
2521 UINT8 CmdRanksTerminated;
2522
2523/** Offset 0x05B5 - RMTLoopCount
2524 Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO
2525**/
2526 UINT8 RMTLoopCount;
2527
2528/** Offset 0x05B6 - Throttler CKEMin Timer for LPDDR
2529 LPDDR Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH
2530 (4). Dfault is 0x40
2531**/
2532 UINT8 ThrtCkeMinTmrLpddr;
2533
2534/** Offset 0x05B7 - Retrain on Fast Fail
2535 Restart MRC in Cold mode if SW MemTest fails during Fast flow. Default = Enabled
2536 $EN_DIS
2537**/
2538 UINT8 RetrainOnFastFail;
2539
2540/** Offset 0x05B8 - Rank Margin Tool Per Bit
2541 Enable/disable Rank Margin Tool Per Bit.
2542 $EN_DIS
2543**/
2544 UINT8 RMTBIT;
2545
2546/** Offset 0x05B9 - Read Timing Optimization
2547 Enables/Disable Read Timing Optimization
2548 $EN_DIS
2549**/
2550 UINT8 RDTOPT;
2551
2552/** Offset 0x05BA - REFRESH_PANIC_WM
2553 Refresh Panic Watermark, range 1-9, Default is 9
2554**/
2555 UINT8 RefreshPanicWm;
2556
2557/** Offset 0x05BB - REFRESH_HP_WM
2558 Refresh High Priority Watermark, range 1-9, Default is 8
2559**/
2560 UINT8 RefreshHpWm;
2561
2562/** Offset 0x05BC - PcdSerialDebugLevel
2563 Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
2564 Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
2565 Info & Verbose.
2566 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load
2567 Error Warnings and Info, 5:Load Error Warnings Info and Verbose
2568**/
2569 UINT8 PcdSerialDebugLevel;
2570
2571/** Offset 0x05BD - Fivr Faults
2572 Fivr Faults; 0: Disabled; <b>1: Enabled.</b>
2573 $EN_DIS
2574**/
2575 UINT8 FivrFaults;
2576
2577/** Offset 0x05BE - Fivr Efficiency
2578 Fivr Efficiency Management; 0: Disabled; <b>1: Enabled.</b>
2579 $EN_DIS
2580**/
2581 UINT8 FivrEfficiency;
2582
2583/** Offset 0x05BF - Safe Mode Support
2584 This option configures the varous items in the IO and MC to be more conservative.(def=Disable)
2585 $EN_DIS
2586**/
2587 UINT8 SafeMode;
2588
2589/** Offset 0x05C0 - Ask MRC to clear memory content
2590 Ask MRC to clear memory content <b>0: Do not Clear Memory;</b> 1: Clear Memory.
2591 $EN_DIS
2592**/
2593 UINT8 CleanMemory;
2594
2595/** Offset 0x05C1 - TCSS USB Port Enable
2596 Bitmap for per port enabling
2597**/
2598 UINT8 UsbTcPortEnPreMem;
2599
2600/** Offset 0x05C2 - Post Code Output Port
2601 This option configures Post Code Output Port
2602**/
2603 UINT16 PostCodeOutputPort;
2604
2605/** Offset 0x05C4 - Enable/Disable SA CRID
2606 Enable: SA CRID, Disable (Default): SA CRID
2607 $EN_DIS
2608**/
2609 UINT8 CridEnable;
2610
2611/** Offset 0x05C5
2612**/
2613 UINT8 UnusedUpdSpace17[3];
2614
2615/** Offset 0x05C8 - BCLK RFI Frequency
2616 Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz <b>0 - No
2617 RFI Tuning</b>. Range is 98Mhz-100Mhz.
2618**/
2619 UINT32 BclkRfiFreq[4];
2620
2621/** Offset 0x05D8 - Size of PCIe IMR.
2622 Size of PCIe IMR in megabytes
2623**/
2624 UINT16 PcieImrSize;
2625
2626/** Offset 0x05DA - Enable PCIe IMR
2627 0: Disable(AUTO), 1: Enable
2628 $EN_DIS
2629**/
2630 UINT8 PcieImrEnabled;
2631
2632/** Offset 0x05DB - Enable PCIe IMR
2633 1: PCH PCIE, 2: SA PCIE. If PCIeImrEnabled is TRUE then this will use to select
2634 the Root port location from PCH PCIe or SA PCIe
2635 $EN_DIS
2636**/
2637 UINT8 PcieImrRpLocation;
2638
2639/** Offset 0x05DC - Root port number for IMR.
2640 Root port number for IMR.If PCieImrRpLocation is PCH PCIe then select root port
2641 from 0 to 23 and if it is SA PCIe then select root port from 0 to 3
2642**/
2643 UINT8 PcieImrRpSelection;
2644
2645/** Offset 0x05DD - Mem Boot Mode
2646 0: BOOT_MODE_1LM(Default), 1: BOOT_MODE_2LM, 2: BOOT_MODE_PROVISION
2647 0: BOOT_MODE_1LM, 1: BOOT_MODE_2LM, 2: BOOT_MODE_PROVISION
2648**/
2649 UINT8 MemBootMode;
2650
2651/** Offset 0x05DE - PCIe ASPM programming will happen in relation to the Oprom
2652 This option is specifically needed for ASPM configuration in 2LM feature
2653 0:Disabled, 1:L0, 2:L1, 3:L0L1, 4:Auto
2654**/
2655 UINT8 Peg3Aspm;
2656
2657/** Offset 0x05DF - MFVC WRR VC Arbitration
2658 0: DEFAULT_PHASES(Default), 1: PROGRAM_128PHASES
2659 0: DEFAULT_PHASES, 1: PROGRAM_128PHASES
2660**/
2661 UINT8 MfvcWrrArb;
2662
2663/** Offset 0x05E0 - VcId_7_0 values
2664 Select VC ID for arbitration
2665**/
2666 UINT8 VcId_7_0[16];
2667
2668/** Offset 0x05F0 - Set Hw Parameters enable/disable
2669 1: enable, 0: disable, Enable/disable setting of HW parameters
2670 $EN_DIS
2671**/
2672 UINT8 SetHwParameters;
2673
2674/** Offset 0x05F1
2675**/
2676 UINT8 UnusedUpdSpace18;
2677
2678/** Offset 0x05F2 - LTR L1.2 Threshold Value
2679 LTR L1.2 Threshold Value
2680**/
2681 UINT16 Ltr_L1D2_ThVal;
2682
2683/** Offset 0x05F4 - LTR L1.2 Threshold Scale
2684 LTR L1.2 Threshold Scale
2685**/
2686 UINT8 Ltr_L1D2_ThScale;
2687
2688/** Offset 0x05F5 - system power state
2689 system power state indicates the platform power state
2690**/
2691 UINT8 SysPwrState;
2692
2693/** Offset 0x05F6 - Media Death Notification Enable/Disable
2694 1: enable, 0: disable, Enable/disable for Media Death Notification
2695 $EN_DIS
2696**/
2697 UINT8 MediaDeathNotification;
2698
2699/** Offset 0x05F7 - Health Log Notification Enable/Disable
2700 1: enable, 0: disable, Enable/disable for Health Log Notification
2701 $EN_DIS
2702**/
2703 UINT8 HealthLogNotification;
2704
2705/** Offset 0x05F8 - Temp crosses below TempThrottle Notification Enable/Disable
2706 1: enable, 0: disable, Enable/disable for Temp crosses below TempThrottle Notification
2707 $EN_DIS
2708**/
2709 UINT8 TempBelowThrottleNotification;
2710
2711/** Offset 0x05F9 - Temp crosses above TempThrottle Notification Enable/Disable
2712 1: enable, 0: disable, Enable/disable for Temp crosses above TempThrottle Notification
2713 $EN_DIS
2714**/
2715 UINT8 TempAboveThrottleNotification;
2716
2717/** Offset 0x05FA - Missing Commit Bit Notification Enable/Disable
2718 1: enable, 0: disable, Enable/disable for Missing Commit Bit Notification
2719 $EN_DIS
2720**/
2721 UINT8 MissingCommitBitNotification;
2722
2723/** Offset 0x05FB - NVMeHoldDisableBit
2724 1: enable, 0: disable, Enable/disable for NVMeHoldDisableBit
2725 $EN_DIS
2726**/
2727 UINT8 NVMeHoldDisableBit;
2728
2729/** Offset 0x05FC - PreMemRsvd
2730 Reserved for Pre-Mem
2731 $EN_DIS
2732**/
2733 UINT8 ReservedFspmUpd[18];
2734
2735/** Offset 0x060E - Skip external display device scanning
2736 Enable: Do not scan for external display device, Disable (Default): Scan external
2737 display devices
2738 $EN_DIS
2739**/
2740 UINT8 SkipExtGfxScan;
2741
2742/** Offset 0x060F - Generate BIOS Data ACPI Table
2743 Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it
2744 $EN_DIS
2745**/
2746 UINT8 BdatEnable;
2747
2748/** Offset 0x0610 - Detect External Graphics device for LegacyOpROM
2749 Detect and report if external graphics device only support LegacyOpROM or not (to
2750 support CSM auto-enable). Enable(Default)=1, Disable=0
2751 $EN_DIS
2752**/
2753 UINT8 ScanExtGfxForLegacyOpRom;
2754
2755/** Offset 0x0611 - Lock PCU Thermal Management registers
2756 Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0
2757 $EN_DIS
2758**/
2759 UINT8 LockPTMregs;
2760
2761/** Offset 0x0612 - Rsvd
2762 Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1):
2763 Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE
2764 peak values unmodified
2765 $EN_DIS
2766**/
2767 UINT8 PegGen3Rsvd;
2768
2769/** Offset 0x0613 - Panel Power Enable
2770 Control for enabling/disabling VDD force bit (Required only for early enabling of
2771 eDP panel). 0=Disable, 1(Default)=Enable
2772 $EN_DIS
2773**/
2774 UINT8 PanelPowerEnable;
2775
2776/** Offset 0x0614 - BdatTestType
2777 Indicates the type of Memory Training data to populate into the BDAT ACPI table.
2778 0:RMT per Rank, 1:RMT per Bit, 2:Margin2D
2779**/
2780 UINT8 BdatTestType;
2781
2782/** Offset 0x0615 - SaPreMemTestRsvd
2783 Reserved for SA Pre-Mem Test
2784 $EN_DIS
2785**/
2786 UINT8 SaPreMemTestRsvd[98];
2787
2788/** Offset 0x0677
2789**/
2790 UINT8 UnusedUpdSpace19;
2791
2792/** Offset 0x0678 - TotalFlashSize
2793 Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable
2794**/
2795 UINT16 TotalFlashSize;
2796
2797/** Offset 0x067A - BiosSize
2798 Enable/Disable. 0: Disable, define default value of BiosSize , 1: enable
2799**/
2800 UINT16 BiosSize;
2801
2802/** Offset 0x067C - TxtAcheckRequest
2803 Enable/Disable. When Enabled, it will forcing calling TXT Acheck once.
2804 $EN_DIS
2805**/
2806 UINT8 TxtAcheckRequest;
2807
2808/** Offset 0x067D - SecurityTestRsvd
2809 Reserved for SA Pre-Mem Test
2810 $EN_DIS
2811**/
2812 UINT8 SecurityTestRsvd[11];
2813
2814/** Offset 0x0688 - Smbus dynamic power gating
2815 Disable or Enable Smbus dynamic power gating.
2816 $EN_DIS
2817**/
2818 UINT8 SmbusDynamicPowerGating;
2819
2820/** Offset 0x0689 - Disable and Lock Watch Dog Register
2821 Set 1 to clear WDT status, then disable and lock WDT registers.
2822 $EN_DIS
2823**/
2824 UINT8 WdtDisableAndLock;
2825
2826/** Offset 0x068A - SMBUS SPD Write Disable
2827 Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write
2828 Disable bit. For security recommendations, SPD write disable bit must be set.
2829 $EN_DIS
2830**/
2831 UINT8 SmbusSpdWriteDisable;
2832
2833/** Offset 0x068B - VC Type
2834 Virtual Channel Type Select: 0: VC0, 1: VC1.
2835 0: VC0, 1: VC1
2836**/
2837 UINT8 PchHdaVcType;
2838
2839/** Offset 0x068C - Universal Audio Architecture compliance for DSP enabled system
2840 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox
2841 driver or SST driver supported).
2842 $EN_DIS
2843**/
2844 UINT8 PchHdaDspUaaCompliance;
2845
2846/** Offset 0x068D - Enable HD Audio Link
2847 Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1.
2848 $EN_DIS
2849**/
2850 UINT8 PchHdaAudioLinkHdaEnable;
2851
2852/** Offset 0x068E - Enable HDA SDI lanes
2853 Enable/disable HDA SDI lanes.
2854**/
2855 UINT8 PchHdaSdiEnable[2];
2856
2857/** Offset 0x0690 - HDA Power/Clock Gating (PGD/CGD)
2858 Enable/Disable HD Audio Power and Clock Gating(POR: Enable). 0: PLATFORM_POR, 1:
2859 FORCE_ENABLE, 2: FORCE_DISABLE.
2860 0: POR, 1: Force Enable, 2: Force Disable
2861**/
2862 UINT8 PchHdaTestPowerClockGating;
2863
2864/** Offset 0x0691 - Enable HD Audio DMIC_N Link
2865 Enable/disable HD Audio DMIC1 link. Muxed with SNDW3.
2866**/
2867 UINT8 PchHdaAudioLinkDmicEnable[2];
2868
2869/** Offset 0x0693
2870**/
2871 UINT8 UnusedUpdSpace20[1];
2872
2873/** Offset 0x0694 - DMIC<N> ClkA Pin Muxing (N - DMIC number)
2874 Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKA_*
2875**/
2876 UINT32 PchHdaAudioLinkDmicClkAPinMux[2];
2877
2878/** Offset 0x069C - DMIC<N> ClkB Pin Muxing
2879 Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKB_*
2880**/
2881 UINT32 PchHdaAudioLinkDmicClkBPinMux[2];
2882
2883/** Offset 0x06A4 - Enable HD Audio DSP
2884 Enable/disable HD Audio DSP feature.
2885 $EN_DIS
2886**/
2887 UINT8 PchHdaDspEnable;
2888
2889/** Offset 0x06A5
2890**/
2891 UINT8 UnusedUpdSpace21[3];
2892
2893/** Offset 0x06A8 - DMIC<N> Data Pin Muxing
2894 Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_*
2895**/
2896 UINT32 PchHdaAudioLinkDmicDataPinMux[2];
2897
2898/** Offset 0x06B0 - Enable HD Audio SSP0 Link
2899 Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5
2900**/
2901 UINT8 PchHdaAudioLinkSspEnable[6];
2902
2903/** Offset 0x06B6 - Enable HD Audio SoundWire#N Link
2904 Enable/disable HD Audio SNDW#N link. Muxed with HDA.
2905**/
2906 UINT8 PchHdaAudioLinkSndwEnable[4];
2907
2908/** Offset 0x06BA - iDisp-Link Frequency
2909 iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz.
2910 4: 96MHz, 3: 48MHz
2911**/
2912 UINT8 PchHdaIDispLinkFrequency;
2913
2914/** Offset 0x06BB - iDisp-Link T-mode
2915 iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T
2916 0: 2T, 2: 4T, 3: 8T, 4: 16T
2917**/
2918 UINT8 PchHdaIDispLinkTmode;
2919
2920/** Offset 0x06BC - iDisplay Audio Codec disconnection
2921 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable.
2922 $EN_DIS
2923**/
2924 UINT8 PchHdaIDispCodecDisconnect;
2925
2926/** Offset 0x06BD - Tcc Tuning enable/disable
2927 Tcc (Time Coordinated Computing) Tuning Enabled
2928 $EN_DIS
2929**/
Tan, Lean Shengef41e8a2021-05-24 00:13:59 -0700[diff] [blame]2930 UINT8 TccTuningEnablePreMem;
Martin Roth062c4a12021-02-14 13:58:31 -0700[diff] [blame]2931
2932/** Offset 0x06BE
2933**/
2934 UINT8 UnusedUpdSpace22[2];
2935
Tan, Lean Shengef41e8a2021-05-24 00:13:59 -0700[diff] [blame]2936/** Offset 0x06C0 - Tcc Buffer Config File Base Address
2937 Tcc (Time Coordinated Computing) Buffer Config File File Base Address
Martin Roth062c4a12021-02-14 13:58:31 -0700[diff] [blame]2938**/
Tan, Lean Shengef41e8a2021-05-24 00:13:59 -0700[diff] [blame]2939 UINT32 TccBufferCfgBase;
Martin Roth062c4a12021-02-14 13:58:31 -0700[diff] [blame]2940
Tan, Lean Shengef41e8a2021-05-24 00:13:59 -0700[diff] [blame]2941/** Offset 0x06C4 - Tcc Buffer Config File Size
2942 Tcc (Time Coordinated Computing) Buffer Config File Size
Martin Roth062c4a12021-02-14 13:58:31 -0700[diff] [blame]2943**/
Tan, Lean Shengef41e8a2021-05-24 00:13:59 -0700[diff] [blame]2944 UINT32 TccBufferCfgSize;
Martin Roth062c4a12021-02-14 13:58:31 -0700[diff] [blame]2945
Tan, Lean Shengef41e8a2021-05-24 00:13:59 -0700[diff] [blame]2946/** Offset 0x06C8 - Tcc BIOS Config File Base Address
2947 Tcc (Time Coordinated Computing) TCC BIOS Config File Base Address
2948**/
2949 UINT32 TccStreamCfgBasePreMem;
2950
2951/** Offset 0x06CC - Tcc BIOS Config File Size
2952 Tcc (Time Coordinated Computing) TCC BIOS Config File Size
2953**/
2954 UINT32 TccStreamCfgSizePreMem;
2955
2956/** Offset 0x06D0 - Force ME DID Init Status
Martin Roth062c4a12021-02-14 13:58:31 -0700[diff] [blame]2957 Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set
2958 ME DID init stat value
2959 $EN_DIS
2960**/
2961 UINT8 DidInitStat;
2962
Tan, Lean Shengef41e8a2021-05-24 00:13:59 -0700[diff] [blame]2963/** Offset 0x06D1 - CPU Replaced Polling Disable
Martin Roth062c4a12021-02-14 13:58:31 -0700[diff] [blame]2964 Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop
2965 $EN_DIS
2966**/
2967 UINT8 DisableCpuReplacedPolling;
2968
Tan, Lean Shengef41e8a2021-05-24 00:13:59 -0700[diff] [blame]2969/** Offset 0x06D2 - ME DID Message
Martin Roth062c4a12021-02-14 13:58:31 -0700[diff] [blame]2970 Test, 0: disable, 1: enable, Enable/Disable ME DID Message (disable will prevent
2971 the DID message from being sent)
2972 $EN_DIS
2973**/
2974 UINT8 SendDidMsg;
2975
Tan, Lean Shengef41e8a2021-05-24 00:13:59 -0700[diff] [blame]2976/** Offset 0x06D3 - Check HECI message before send
Martin Roth062c4a12021-02-14 13:58:31 -0700[diff] [blame]2977 Test, 0: disable, 1: enable, Enable/Disable message check.
2978 $EN_DIS
2979**/
2980 UINT8 DisableMessageCheck;
2981
Tan, Lean Shengef41e8a2021-05-24 00:13:59 -0700[diff] [blame]2982/** Offset 0x06D4 - Skip MBP HOB
Martin Roth062c4a12021-02-14 13:58:31 -0700[diff] [blame]2983 Test, 0: disable, 1: enable, Enable/Disable MOB HOB.
2984 $EN_DIS
2985**/
2986 UINT8 SkipMbpHob;
2987
Tan, Lean Shengef41e8a2021-05-24 00:13:59 -0700[diff] [blame]2988/** Offset 0x06D5 - HECI2 Interface Communication
Martin Roth062c4a12021-02-14 13:58:31 -0700[diff] [blame]2989 Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space.
2990 $EN_DIS
2991**/
2992 UINT8 HeciCommunication2;
2993
Tan, Lean Shengef41e8a2021-05-24 00:13:59 -0700[diff] [blame]2994/** Offset 0x06D6 - Enable KT device
Martin Roth062c4a12021-02-14 13:58:31 -0700[diff] [blame]2995 Test, 0: disable, 1: enable, Enable or Disable KT device.
2996 $EN_DIS
2997**/
2998 UINT8 KtDeviceEnable;
2999
Tan, Lean Shengef41e8a2021-05-24 00:13:59 -0700[diff] [blame]3000/** Offset 0x06D7 - Skip CPU replacement check
3001 Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check
3002 $EN_DIS
Martin Roth062c4a12021-02-14 13:58:31 -0700[diff] [blame]3003**/
Tan, Lean Shengef41e8a2021-05-24 00:13:59 -0700[diff] [blame]3004 UINT8 SkipCpuReplacementCheck;
Martin Roth062c4a12021-02-14 13:58:31 -0700[diff] [blame]3005
Tan, Lean Shengef41e8a2021-05-24 00:13:59 -0700[diff] [blame]3006/** Offset 0x06D8
3007**/
3008 UINT8 UnusedUpdSpace23[4];
3009
3010/** Offset 0x06DC
Martin Roth062c4a12021-02-14 13:58:31 -0700[diff] [blame]3011**/
3012 UINT8 ReservedFspmUpd2[20];
3013} FSP_M_CONFIG;
3014
3015/** Fsp M UPD Configuration
3016**/
3017typedef struct {
3018
3019/** Offset 0x0000
3020**/
3021 FSP_UPD_HEADER FspUpdHeader;
3022
3023/** Offset 0x0020
3024**/
3025 FSPM_ARCH_UPD FspmArchUpd;
3026
3027/** Offset 0x0040
3028**/
3029 FSP_M_CONFIG FspmConfig;
3030
Tan, Lean Shengef41e8a2021-05-24 00:13:59 -0700[diff] [blame]3031/** Offset 0x06F0
Martin Roth062c4a12021-02-14 13:58:31 -0700[diff] [blame]3032**/
3033 UINT8 UnusedUpdSpace24[6];
3034
Tan, Lean Shengef41e8a2021-05-24 00:13:59 -0700[diff] [blame]3035/** Offset 0x06F6
Martin Roth062c4a12021-02-14 13:58:31 -0700[diff] [blame]3036**/
3037 UINT16 UpdTerminator;
3038} FSPM_UPD;
3039
3040#pragma pack()
3041
3042#endif