Greg Watson | 14a90f1 | 2003-11-02 17:05:20 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> |
| 3 | * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> |
| 4 | * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de> |
| 5 | * |
| 6 | * See file CREDITS for list of people who contributed to this |
| 7 | * project. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License as |
| 11 | * published by the Free Software Foundation; either version 2 of |
| 12 | * the License, or (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
Stefan Reinauer | 6ab43fc | 2005-10-05 18:17:45 +0000 | [diff] [blame^] | 21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, |
| 22 | * MA 02110-1301 USA |
Greg Watson | 14a90f1 | 2003-11-02 17:05:20 +0000 | [diff] [blame] | 23 | * |
| 24 | * This source code has been made available to you by IBM on an AS-IS |
| 25 | * basis. Anyone receiving this source is licensed under IBM |
| 26 | * copyrights to use it in any way he or she deems fit, including |
| 27 | * copying it, modifying it, compiling it, and redistributing it either |
| 28 | * with or without modifications. No license under IBM patents or |
| 29 | * patent applications is to be implied by the copyright license. |
| 30 | * |
| 31 | * Any user of this software should understand that IBM cannot provide |
| 32 | * technical support for this software and will not be responsible for |
| 33 | * any consequences resulting from the use of this software. |
| 34 | * |
| 35 | * Any person who transfers this source code or any derivative work |
| 36 | * must include the IBM copyright notice, this paragraph, and the |
| 37 | * preceding two paragraphs in the transferred software. |
| 38 | * |
| 39 | * COPYRIGHT I B M CORPORATION 1995 |
| 40 | * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M |
| 41 | * |
| 42 | */ |
| 43 | |
| 44 | #include <ppc_asm.tmpl> |
| 45 | |
| 46 | #define CACHELINE_SIZE 32 /* 32 bytes (8 words) */ |
| 47 | |
| 48 | /* |
| 49 | * Cache functions. |
| 50 | */ |
| 51 | .globl invalidate_icache |
| 52 | invalidate_icache: |
| 53 | iccci r0,r0 /* for 405, iccci invalidates the */ |
| 54 | blr /* entire I cache */ |
| 55 | |
| 56 | .globl invalidate_dcache |
| 57 | invalidate_dcache: |
Greg Watson | b020d53 | 2004-01-14 17:21:22 +0000 | [diff] [blame] | 58 | li r6,0x0000 /* clear GPR 6 */ |
Greg Watson | 14a90f1 | 2003-11-02 17:05:20 +0000 | [diff] [blame] | 59 | /* Do loop for # of dcache congruence classes. */ |
Greg Watson | b020d53 | 2004-01-14 17:21:22 +0000 | [diff] [blame] | 60 | li r7,(DCACHE_RAM_SIZE / CACHELINE_SIZE / 2) |
Greg Watson | 14a90f1 | 2003-11-02 17:05:20 +0000 | [diff] [blame] | 61 | /* NOTE: dccci invalidates both */ |
| 62 | mtctr r7 /* ways in the D cache */ |
| 63 | 1: |
| 64 | dccci 0,r6 /* invalidate line */ |
| 65 | addi r6,r6, CACHELINE_SIZE /* bump to next line */ |
| 66 | bdnz 1b |
| 67 | blr |
| 68 | |
| 69 | .globl flush_dcache |
| 70 | flush_dcache: |
Greg Watson | b020d53 | 2004-01-14 17:21:22 +0000 | [diff] [blame] | 71 | lis r9,0x0002 /* set mask for EE and CE msr bits */ |
Greg Watson | 14a90f1 | 2003-11-02 17:05:20 +0000 | [diff] [blame] | 72 | ori r9,r9,0x8000 |
| 73 | mfmsr r12 /* save msr */ |
| 74 | andc r9,r12,r9 |
| 75 | mtmsr r9 /* disable EE and CE */ |
Greg Watson | b020d53 | 2004-01-14 17:21:22 +0000 | [diff] [blame] | 76 | li r10,0x0001 /* enable data cache for unused memory */ |
Greg Watson | 14a90f1 | 2003-11-02 17:05:20 +0000 | [diff] [blame] | 77 | mfdccr r9 /* region 0xF8000000-0xFFFFFFFF via */ |
| 78 | or r10,r10,r9 /* bit 31 in dccr */ |
| 79 | mtdccr r10 |
| 80 | |
| 81 | /* do loop for # of congruence classes. */ |
Greg Watson | b020d53 | 2004-01-14 17:21:22 +0000 | [diff] [blame] | 82 | li r10,(DCACHE_RAM_SIZE / CACHELINE_SIZE / 2) |
| 83 | li r11,(DCACHE_RAM_SIZE / 2) /* D cache set size - 2 way sets */ |
Greg Watson | 14a90f1 | 2003-11-02 17:05:20 +0000 | [diff] [blame] | 84 | mtctr r10 |
Greg Watson | b020d53 | 2004-01-14 17:21:22 +0000 | [diff] [blame] | 85 | li r10,(0xE000-0x10000) /* start at 0xFFFFE000 */ |
Greg Watson | 14a90f1 | 2003-11-02 17:05:20 +0000 | [diff] [blame] | 86 | add r11,r10,r11 /* add to get to other side of cache line */ |
| 87 | 1: |
| 88 | lwz r3,0(r10) /* least recently used side */ |
| 89 | lwz r3,0(r11) /* the other side */ |
| 90 | dccci r0,r11 /* invalidate both sides */ |
| 91 | addi r10,r10,CACHELINE_SIZE /* bump to next line */ |
| 92 | addi r11,r11,CACHELINE_SIZE /* bump to next line */ |
| 93 | bdnz 1b |
| 94 | sync /* allow memory access to complete */ |
| 95 | mtdccr r9 /* restore dccr */ |
| 96 | mtmsr r12 /* restore msr */ |
| 97 | blr |
| 98 | |
| 99 | .globl icache_enable |
| 100 | icache_enable: |
| 101 | mflr r8 |
| 102 | bl invalidate_icache |
| 103 | mtlr r8 |
| 104 | isync |
Greg Watson | b020d53 | 2004-01-14 17:21:22 +0000 | [diff] [blame] | 105 | lis r3,0x8000 /* set bit 0 */ |
Greg Watson | 14a90f1 | 2003-11-02 17:05:20 +0000 | [diff] [blame] | 106 | mticcr r3 |
| 107 | blr |
| 108 | |
| 109 | .globl icache_disable |
| 110 | icache_disable: |
Greg Watson | b020d53 | 2004-01-14 17:21:22 +0000 | [diff] [blame] | 111 | lis r3,0x0000 /* clear bit 0 */ |
Greg Watson | 14a90f1 | 2003-11-02 17:05:20 +0000 | [diff] [blame] | 112 | mticcr r3 |
| 113 | isync |
| 114 | blr |
| 115 | |
| 116 | .globl icache_status |
| 117 | icache_status: |
| 118 | mficcr r3 |
| 119 | srwi r3, r3, 31 /* >>31 => select bit 0 */ |
| 120 | blr |
| 121 | |
| 122 | .globl dcache_enable |
| 123 | dcache_enable: |
| 124 | mflr r8 |
| 125 | bl invalidate_dcache |
| 126 | mtlr r8 |
| 127 | isync |
Greg Watson | b020d53 | 2004-01-14 17:21:22 +0000 | [diff] [blame] | 128 | lis r3,0x8000 /* set bit 0 */ |
Greg Watson | 14a90f1 | 2003-11-02 17:05:20 +0000 | [diff] [blame] | 129 | mtdccr r3 |
| 130 | blr |
| 131 | |
| 132 | .globl dcache_disable |
| 133 | dcache_disable: |
| 134 | mflr r8 |
| 135 | bl flush_dcache |
| 136 | mtlr r8 |
Greg Watson | b020d53 | 2004-01-14 17:21:22 +0000 | [diff] [blame] | 137 | lis r3,0x0000 /* clear bit 0 */ |
Greg Watson | 14a90f1 | 2003-11-02 17:05:20 +0000 | [diff] [blame] | 138 | mtdccr r3 |
| 139 | blr |
| 140 | |
| 141 | .globl dcache_status |
| 142 | dcache_status: |
| 143 | mfdccr r3 |
| 144 | srwi r3, r3, 31 /* >>31 => select bit 0 */ |
| 145 | blr |
| 146 | |
| 147 | /*------------------------------------------------------------------------------- */ |
| 148 | /* Function: ppcDcbf */ |
| 149 | /* Description: Data Cache block flush */ |
| 150 | /* Input: r3 = effective address */ |
| 151 | /* Output: none. */ |
| 152 | /*------------------------------------------------------------------------------- */ |
| 153 | .globl ppcDcbf |
| 154 | ppcDcbf: |
| 155 | dcbf r0,r3 |
| 156 | blr |
| 157 | |
| 158 | /*------------------------------------------------------------------------------- */ |
| 159 | /* Function: ppcDcbi */ |
| 160 | /* Description: Data Cache block Invalidate */ |
| 161 | /* Input: r3 = effective address */ |
| 162 | /* Output: none. */ |
| 163 | /*------------------------------------------------------------------------------- */ |
| 164 | .globl ppcDcbi |
| 165 | ppcDcbi: |
| 166 | dcbi r0,r3 |
| 167 | blr |
| 168 | |
| 169 | /*------------------------------------------------------------------------------- */ |
| 170 | /* Function: ppcSync */ |
| 171 | /* Description: Processor Synchronize */ |
| 172 | /* Input: none. */ |
| 173 | /* Output: none. */ |
| 174 | /*------------------------------------------------------------------------------- */ |
| 175 | .globl ppcSync |
| 176 | ppcSync: |
| 177 | sync |
| 178 | blr |
| 179 | |