Kyösti Mälkki | 7b73e852 | 2022-11-08 04:43:41 +0000 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | /* This was originally for the e7500, modified for e7501 |
| 4 | * The primary differences are that 7501 apparently can |
| 5 | * support single channel RAM (i haven't tested), |
| 6 | * CAS1.5 is no longer supported, The ECC scrubber |
| 7 | * now supports a mode to zero RAM and init ECC in one step |
| 8 | * and the undocumented registers at 0x80 require new |
| 9 | * (undocumented) values determined by guesswork and |
| 10 | * comparison w/ OEM BIOS values. |
| 11 | * Steven James 02/06/2003 |
| 12 | */ |
| 13 | |
| 14 | #include <stdint.h> |
| 15 | #include <device/pci_def.h> |
| 16 | #include <arch/io.h> |
| 17 | #include <device/mmio.h> |
| 18 | #include <device/pci_ops.h> |
| 19 | #include <device/smbus_host.h> |
| 20 | #include <lib.h> |
| 21 | #include <commonlib/helpers.h> |
| 22 | #include <console/console.h> |
| 23 | #include <assert.h> |
| 24 | #include <spd.h> |
| 25 | #include <sdram_mode.h> |
| 26 | #include <timestamp.h> |
| 27 | |
| 28 | #include "raminit.h" |
| 29 | #include "e7505.h" |
| 30 | |
| 31 | /*----------------------------------------------------------------------------- |
| 32 | Definitions: |
| 33 | -----------------------------------------------------------------------------*/ |
| 34 | |
| 35 | #if CONFIG(DEBUG_RAM_SETUP) |
| 36 | #define RAM_DEBUG_MESSAGE(x) printk(BIOS_DEBUG, x) |
| 37 | #define RAM_DEBUG_HEX32(x) printk(BIOS_DEBUG, "%08x", x) |
| 38 | #define RAM_DEBUG_HEX8(x) printk(BIOS_DEBUG, "%02x", x) |
| 39 | #else |
| 40 | #define RAM_DEBUG_MESSAGE(x) |
| 41 | #define RAM_DEBUG_HEX32(x) |
| 42 | #define RAM_DEBUG_HEX8(x) |
| 43 | #endif |
| 44 | |
| 45 | #define E7501_SDRAM_MODE (SDRAM_BURST_INTERLEAVED | SDRAM_BURST_4) |
| 46 | #define SPD_ERROR "Error reading SPD info\n" |
| 47 | |
| 48 | #define MCHDEV PCI_DEV(0, 0, 0) |
| 49 | #define RASDEV PCI_DEV(0, 0, 1) |
| 50 | #define AGPDEV PCI_DEV(0, 1, 0) |
| 51 | #define D060DEV PCI_DEV(0, 6, 0) |
| 52 | |
| 53 | // NOTE: This used to be 0x100000. |
| 54 | // That doesn't work on systems where A20M# is asserted, because |
| 55 | // attempts to access 0x1000NN end up accessing 0x0000NN. |
| 56 | #define RCOMP_MMIO ((u8 *)0x200000) |
| 57 | |
| 58 | struct dimm_size { |
| 59 | unsigned long side1; |
| 60 | unsigned long side2; |
| 61 | }; |
| 62 | |
| 63 | static const uint32_t refresh_frequency[] = { |
| 64 | /* Relative frequency (array value) of each E7501 Refresh Mode Select |
| 65 | * (RMS) value (array index) |
| 66 | * 0 == least frequent refresh (longest interval between refreshes) |
| 67 | * [0] disabled -> 0 |
| 68 | * [1] 15.6 usec -> 2 |
| 69 | * [2] 7.8 usec -> 3 |
| 70 | * [3] 64 usec -> 1 |
| 71 | * [4] reserved -> 0 |
| 72 | * [5] reserved -> 0 |
| 73 | * [6] reserved -> 0 |
| 74 | * [7] 64 clocks -> 4 |
| 75 | */ |
| 76 | 0, 2, 3, 1, 0, 0, 0, 4 |
| 77 | }; |
| 78 | |
| 79 | static const uint32_t refresh_rate_map[] = { |
| 80 | /* Map the JEDEC spd refresh rates (array index) to E7501 Refresh Mode |
| 81 | * Select values (array value) |
| 82 | * These are all the rates defined by JESD21-C Appendix D, Rev. 1.0 |
| 83 | * The E7501 supports only 15.6 us (1), 7.8 us (2), 64 us (3), and |
| 84 | * 64 clock (481 ns) (7) refresh. |
| 85 | * [0] == 15.625 us -> 15.6 us |
| 86 | * [1] == 3.9 us -> 481 ns |
| 87 | * [2] == 7.8 us -> 7.8 us |
| 88 | * [3] == 31.3 us -> 15.6 us |
| 89 | * [4] == 62.5 us -> 15.6 us |
| 90 | * [5] == 125 us -> 64 us |
| 91 | */ |
| 92 | 1, 7, 2, 1, 1, 3 |
| 93 | }; |
| 94 | |
| 95 | #define MAX_SPD_REFRESH_RATE (ARRAY_SIZE(refresh_rate_map) - 1) |
| 96 | |
| 97 | // SPD parameters that must match for dual-channel operation |
| 98 | static const uint8_t dual_channel_parameters[] = { |
| 99 | SPD_MEMORY_TYPE, |
| 100 | SPD_MODULE_VOLTAGE, |
| 101 | SPD_NUM_COLUMNS, |
| 102 | SPD_NUM_ROWS, |
| 103 | SPD_NUM_DIMM_BANKS, |
| 104 | SPD_PRIMARY_SDRAM_WIDTH, |
| 105 | SPD_NUM_BANKS_PER_SDRAM |
| 106 | }; |
| 107 | |
| 108 | /* Comments here are remains of e7501 or even 855PM. |
| 109 | * They might be partially (in)correct for e7505. |
| 110 | */ |
| 111 | |
| 112 | /* (DRAM Read Timing Control, if similar to 855PM?) |
| 113 | * 0x80 - 0x81 documented differently for e7505 |
| 114 | * This register has something to do with CAS latencies, |
| 115 | * possibly this is the real chipset control. |
| 116 | * At 0x00 CAS latency 1.5 works. |
| 117 | * At 0x06 CAS latency 2.5 works. |
| 118 | * At 0x01 CAS latency 2.0 works. |
| 119 | * |
| 120 | * This is still undocumented in e7501, but with different values |
| 121 | * CAS 2.0 values taken from Intel BIOS settings, others are a guess |
| 122 | * and may be terribly wrong. Old values preserved as comments until I |
| 123 | * figure this out for sure. |
| 124 | * e7501 docs claim that CAS1.5 is unsupported, so it may or may not |
| 125 | * work at all. |
| 126 | * Steven James 02/06/2003 |
| 127 | * |
| 128 | * NOTE: values now configured in configure_e7501_cas_latency() based |
| 129 | * on SPD info and total number of DIMMs (per Intel) |
| 130 | */ |
| 131 | |
| 132 | /* FDHC - Fixed DRAM Hole Control ??? |
| 133 | * 0x58 undocumented for e7505, memory hole in southbridge configuration? |
| 134 | * [7:7] Hole_Enable |
| 135 | * 0 == No memory Hole |
| 136 | * 1 == Memory Hole from 15MB to 16MB |
| 137 | * [6:0] Reserved |
| 138 | */ |
| 139 | |
| 140 | /* Another Intel undocumented register |
| 141 | * 0x88 - 0x8B |
| 142 | * [31:31] Purpose unknown |
| 143 | * [26:26] Master DLL Reset? |
| 144 | * 0 == Normal operation? |
| 145 | * 1 == Reset? |
| 146 | * [07:07] Periodic memory recalibration? |
| 147 | * 0 == Disabled? |
| 148 | * 1 == Enabled? |
| 149 | * [04:04] Receive FIFO RE-Sync? |
| 150 | * 0 == Normal operation? |
| 151 | * 1 == Reset? |
| 152 | */ |
| 153 | |
| 154 | /* DDR RECOMP tables */ |
| 155 | // Slew table for 2x drive? |
| 156 | static const uint32_t slew_2x[] = { |
| 157 | 0x00000000, 0x76543210, 0xffffeca8, 0xffffffff, |
| 158 | 0x21000000, 0xa8765432, 0xffffffec, 0xffffffff, |
| 159 | }; |
| 160 | |
| 161 | // Pull Up / Pull Down offset table, if analogous to IXP2800? |
| 162 | static const uint32_t pull_updown_offset_table[] = { |
| 163 | 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, |
| 164 | 0x88888888, 0x88888888, 0x88888888, 0x88888888, |
| 165 | }; |
| 166 | |
| 167 | /*----------------------------------------------------------------------------- |
| 168 | Delay functions: |
| 169 | -----------------------------------------------------------------------------*/ |
| 170 | |
| 171 | /* Estimate that SLOW_DOWN_IO takes about 1 us */ |
| 172 | #define SLOW_DOWN_IO inb(0x80) |
| 173 | static void local_udelay(int i) |
| 174 | { |
| 175 | while (i--) { |
| 176 | SLOW_DOWN_IO; |
| 177 | } |
| 178 | } |
| 179 | |
| 180 | /* delay for 200us */ |
| 181 | #define DO_DELAY local_udelay(200) |
| 182 | #define EXTRA_DELAY DO_DELAY |
| 183 | |
| 184 | /*----------------------------------------------------------------------------- |
| 185 | Handle (undocumented) control bits MCHTST and PCI_DEV(0,6,0) |
| 186 | -----------------------------------------------------------------------------*/ |
| 187 | typedef enum { |
| 188 | MCHTST_CMD_0, |
| 189 | D060_ENABLE, |
| 190 | D060_DISABLE, |
| 191 | RCOMP_BAR_ENABLE, |
| 192 | RCOMP_BAR_DISABLE, |
| 193 | } mchtst_cc; |
| 194 | |
| 195 | typedef enum { |
| 196 | D060_CMD_0, |
| 197 | D060_CMD_1, |
| 198 | } d060_cc; |
| 199 | |
| 200 | typedef enum { |
| 201 | RCOMP_HOLD, |
| 202 | RCOMP_RELEASE, |
| 203 | RCOMP_SMR_00, |
| 204 | RCOMP_SMR_01, |
| 205 | } rcomp_smr_cc; |
| 206 | |
| 207 | /** |
| 208 | * MCHTST - 0xF4 - 0xF7 -- Based on similarity to 855PM |
| 209 | * |
| 210 | * [31:31] Purpose unknown |
| 211 | * [30:30] Purpose unknown |
| 212 | * [29:23] Unknown - not used? |
| 213 | * [22:22] System Memory MMR Enable |
| 214 | * 0 == Disable: mem space and BAR at 0x14 are not accessible |
| 215 | * 1 == Enable: mem space and BAR at 0x14 are accessible |
| 216 | * [21:20] Purpose unknown |
| 217 | * [19:02] Unknown - not used? |
| 218 | * [01:01] D6EN (Device #6 enable) |
| 219 | * 0 == Disable |
| 220 | * 1 == Enable |
| 221 | * [00:00] Unknown - not used? |
| 222 | */ |
| 223 | static void mchtest_control(mchtst_cc cmd) |
| 224 | { |
| 225 | uint32_t dword = pci_read_config32(MCHDEV, MCHTST); |
| 226 | switch (cmd) { |
| 227 | case MCHTST_CMD_0: |
| 228 | dword &= ~(3 << 30); |
| 229 | break; |
| 230 | case RCOMP_BAR_ENABLE: |
| 231 | dword |= (1 << 22); |
| 232 | break; |
| 233 | case RCOMP_BAR_DISABLE: |
| 234 | dword &= ~(1 << 22); |
| 235 | break; |
| 236 | case D060_ENABLE: |
| 237 | dword |= (1 << 1); |
| 238 | break; |
| 239 | case D060_DISABLE: |
| 240 | dword &= ~(1 << 1); |
| 241 | break; |
| 242 | }; |
| 243 | pci_write_config32(MCHDEV, MCHTST, dword); |
| 244 | } |
| 245 | |
| 246 | /** |
| 247 | * |
| 248 | */ |
| 249 | static void d060_control(d060_cc cmd) |
| 250 | { |
| 251 | mchtest_control(D060_ENABLE); |
| 252 | uint32_t dword = pci_read_config32(D060DEV, 0xf0); |
| 253 | switch (cmd) { |
| 254 | case D060_CMD_0: |
| 255 | dword |= (1 << 2); |
| 256 | break; |
| 257 | case D060_CMD_1: |
| 258 | dword |= (3 << 27); |
| 259 | break; |
| 260 | } |
| 261 | pci_write_config32(D060DEV, 0xf0, dword); |
| 262 | mchtest_control(D060_DISABLE); |
| 263 | } |
| 264 | |
| 265 | /** |
| 266 | * |
| 267 | */ |
| 268 | static void rcomp_smr_control(rcomp_smr_cc cmd) |
| 269 | { |
| 270 | uint32_t dword = read32(RCOMP_MMIO + SMRCTL); |
| 271 | switch (cmd) { |
| 272 | case RCOMP_HOLD: |
| 273 | dword |= (1 << 9); |
| 274 | break; |
| 275 | case RCOMP_RELEASE: |
| 276 | dword &= ~((1 << 9) | (3 << 0)); |
| 277 | dword |= (1 << 10) | (1 << 0); |
| 278 | break; |
| 279 | case RCOMP_SMR_00: |
| 280 | dword &= ~(1 << 8); |
| 281 | break; |
| 282 | case RCOMP_SMR_01: |
| 283 | dword |= (1 << 10) | (1 << 8); |
| 284 | break; |
| 285 | } |
| 286 | write32(RCOMP_MMIO + SMRCTL, dword); |
| 287 | } |
| 288 | |
| 289 | /*----------------------------------------------------------------------------- |
| 290 | Serial presence detect (SPD) functions: |
| 291 | -----------------------------------------------------------------------------*/ |
| 292 | |
| 293 | static void die_on_spd_error(int spd_return_value) |
| 294 | { |
| 295 | if (spd_return_value < 0) |
| 296 | die("Error reading SPD info\n"); |
| 297 | } |
| 298 | |
| 299 | /** |
| 300 | * Calculate the page size for each physical bank of the DIMM: |
| 301 | * log2(page size) = (# columns) + log2(data width) |
| 302 | * |
| 303 | * NOTE: Page size is the total number of data bits in a row. |
| 304 | * |
| 305 | * @param dimm_socket_address SMBus address of DIMM socket to interrogate. |
| 306 | * @return log2(page size) for each side of the DIMM. |
| 307 | */ |
| 308 | static struct dimm_size sdram_spd_get_page_size(uint16_t dimm_socket_address) |
| 309 | { |
| 310 | uint16_t module_data_width; |
| 311 | int value; |
| 312 | struct dimm_size pgsz; |
| 313 | |
| 314 | pgsz.side1 = 0; |
| 315 | pgsz.side2 = 0; |
| 316 | |
| 317 | // Side 1 |
| 318 | value = smbus_read_byte(dimm_socket_address, SPD_NUM_COLUMNS); |
| 319 | if (value < 0) |
| 320 | goto hw_err; |
| 321 | pgsz.side1 = value & 0xf; // # columns in bank 1 |
| 322 | |
| 323 | /* Get the module data width and convert it to a power of two */ |
| 324 | value = smbus_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_MSB); |
| 325 | if (value < 0) |
| 326 | goto hw_err; |
| 327 | module_data_width = (value & 0xff) << 8; |
| 328 | |
| 329 | value = smbus_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_LSB); |
| 330 | if (value < 0) |
| 331 | goto hw_err; |
| 332 | module_data_width |= (value & 0xff); |
| 333 | |
| 334 | pgsz.side1 += log2(module_data_width); |
| 335 | |
| 336 | /* side two */ |
| 337 | value = smbus_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS); |
| 338 | if (value < 0) |
| 339 | goto hw_err; |
| 340 | if (value > 2) |
| 341 | die("Bad SPD value\n"); |
| 342 | if (value == 2) { |
| 343 | |
| 344 | pgsz.side2 = pgsz.side1; // Assume symmetric banks until we know differently |
| 345 | value = smbus_read_byte(dimm_socket_address, SPD_NUM_COLUMNS); |
| 346 | if (value < 0) |
| 347 | goto hw_err; |
| 348 | if ((value & 0xf0) != 0) { |
| 349 | // Asymmetric banks |
| 350 | pgsz.side2 -= value & 0xf; /* Subtract out columns on side 1 */ |
| 351 | pgsz.side2 += (value >> 4) & 0xf; /* Add in columns on side 2 */ |
| 352 | } |
| 353 | } |
| 354 | |
| 355 | return pgsz; |
| 356 | |
| 357 | hw_err: |
| 358 | die(SPD_ERROR); |
| 359 | return pgsz; // Never reached |
| 360 | } |
| 361 | |
| 362 | /** |
| 363 | * Read the width in bits of each DIMM side's DRAMs via SPD (i.e. 4, 8, 16). |
| 364 | * |
| 365 | * @param dimm_socket_address SMBus address of DIMM socket to interrogate. |
| 366 | * @return Width in bits of each DIMM side's DRAMs. |
| 367 | */ |
| 368 | static struct dimm_size sdram_spd_get_width(uint16_t dimm_socket_address) |
| 369 | { |
| 370 | int value; |
| 371 | struct dimm_size width; |
| 372 | |
| 373 | width.side1 = 0; |
| 374 | width.side2 = 0; |
| 375 | |
| 376 | value = smbus_read_byte(dimm_socket_address, SPD_PRIMARY_SDRAM_WIDTH); |
| 377 | die_on_spd_error(value); |
| 378 | |
| 379 | width.side1 = value & 0x7f; // Mask off bank 2 flag |
| 380 | |
| 381 | if (value & 0x80) { |
| 382 | width.side2 = width.side1 << 1; // Bank 2 exists and is double-width |
| 383 | } else { |
| 384 | // If bank 2 exists, it's the same width as bank 1 |
| 385 | value = smbus_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS); |
| 386 | die_on_spd_error(value); |
| 387 | |
| 388 | if (value == 2) |
| 389 | width.side2 = width.side1; |
| 390 | } |
| 391 | |
| 392 | return width; |
| 393 | } |
| 394 | |
| 395 | /** |
| 396 | * Calculate the log base 2 size in bits of both DIMM sides. |
| 397 | * |
| 398 | * log2(# bits) = (# columns) + log2(data width) + |
| 399 | * (# rows) + log2(banks per SDRAM) |
| 400 | * |
| 401 | * Note that it might be easier to use SPD byte 31 here, it has the DIMM size |
| 402 | * as a multiple of 4MB. The way we do it now we can size both sides of an |
| 403 | * asymmetric DIMM. |
| 404 | * |
| 405 | * @param dimm_socket_address SMBus address of DIMM socket to interrogate. |
| 406 | * @return log2(number of bits) for each side of the DIMM. |
| 407 | */ |
| 408 | static struct dimm_size spd_get_dimm_size(unsigned int dimm_socket_address) |
| 409 | { |
| 410 | int value; |
| 411 | |
| 412 | // Start with log2(page size) |
| 413 | struct dimm_size sz = sdram_spd_get_page_size(dimm_socket_address); |
| 414 | |
| 415 | if (sz.side1 > 0) { |
| 416 | |
| 417 | value = smbus_read_byte(dimm_socket_address, SPD_NUM_ROWS); |
| 418 | die_on_spd_error(value); |
| 419 | |
| 420 | sz.side1 += value & 0xf; |
| 421 | |
| 422 | if (sz.side2 > 0) { |
| 423 | |
| 424 | // Double-sided DIMM |
| 425 | if (value & 0xF0) |
| 426 | sz.side2 += value >> 4; // Asymmetric |
| 427 | else |
| 428 | sz.side2 += value; // Symmetric |
| 429 | } |
| 430 | |
| 431 | value = smbus_read_byte(dimm_socket_address, |
| 432 | SPD_NUM_BANKS_PER_SDRAM); |
| 433 | die_on_spd_error(value); |
| 434 | |
| 435 | value = log2(value); |
| 436 | sz.side1 += value; |
| 437 | if (sz.side2 > 0) |
| 438 | sz.side2 += value; |
| 439 | } |
| 440 | |
| 441 | return sz; |
| 442 | } |
| 443 | |
| 444 | /** |
| 445 | * Determine whether two DIMMs have the same value for an SPD parameter. |
| 446 | * |
| 447 | * @param spd_byte_number The SPD byte number to compare in both DIMMs. |
| 448 | * @param dimm0_address SMBus address of the 1st DIMM socket to interrogate. |
| 449 | * @param dimm1_address SMBus address of the 2nd DIMM socket to interrogate. |
| 450 | * @return 1 if both DIMM sockets report the same value for the specified |
| 451 | * SPD parameter, 0 if the values differed or an error occurred. |
| 452 | */ |
| 453 | static uint8_t are_spd_values_equal(uint8_t spd_byte_number, |
| 454 | uint16_t dimm0_address, |
| 455 | uint16_t dimm1_address) |
| 456 | { |
| 457 | uint8_t bEqual = 0; |
| 458 | int dimm0_value = smbus_read_byte(dimm0_address, spd_byte_number); |
| 459 | int dimm1_value = smbus_read_byte(dimm1_address, spd_byte_number); |
| 460 | |
| 461 | if ((dimm0_value >= 0) && (dimm1_value >= 0) |
| 462 | && (dimm0_value == dimm1_value)) |
| 463 | bEqual = 1; |
| 464 | |
| 465 | return bEqual; |
| 466 | } |
| 467 | |
| 468 | /** |
| 469 | * Scan for compatible DIMMs. |
| 470 | * |
| 471 | * The code in this module only supports dual-channel operation, so we test |
| 472 | * that compatible DIMMs are paired. |
| 473 | * |
| 474 | * @param ctrl PCI addresses of memory controller functions, and SMBus |
| 475 | * addresses of DIMM slots on the mainboard. |
| 476 | * @return A bitmask indicating which of the possible sockets for each channel |
| 477 | * was found to contain a compatible DIMM. |
| 478 | * Bit 0 corresponds to the closest socket for channel 0 |
| 479 | * Bit 1 to the next socket for channel 0 |
| 480 | * ... |
| 481 | * Bit MAX_DIMM_SOCKETS_PER_CHANNEL-1 to the last socket for channel 0 |
| 482 | * Bit MAX_DIMM_SOCKETS_PER_CHANNEL is the closest socket for channel 1 |
| 483 | * ... |
| 484 | * Bit 2*MAX_DIMM_SOCKETS_PER_CHANNEL-1 is the last socket for channel 1 |
| 485 | */ |
| 486 | static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl) |
| 487 | { |
| 488 | int i; |
| 489 | uint8_t dimm_mask = 0; |
| 490 | |
| 491 | // Have to increase size of dimm_mask if this assertion is violated |
| 492 | ASSERT(MAX_DIMM_SOCKETS_PER_CHANNEL <= 4); |
| 493 | |
| 494 | // Find DIMMs we can support on channel 0. |
| 495 | // Then see if the corresponding channel 1 DIMM has the same parameters, |
| 496 | // since we only support dual-channel. |
| 497 | |
| 498 | for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) { |
| 499 | |
| 500 | uint16_t channel0_dimm = ctrl->channel0[i]; |
| 501 | uint16_t channel1_dimm = ctrl->channel1[i]; |
| 502 | uint8_t bDualChannel = 1; |
| 503 | struct dimm_size page_size; |
| 504 | struct dimm_size sdram_width; |
| 505 | int spd_value; |
| 506 | |
| 507 | if (channel0_dimm == 0) |
| 508 | continue; // No such socket on this mainboard |
| 509 | |
| 510 | if (smbus_read_byte(channel0_dimm, SPD_MEMORY_TYPE) != |
| 511 | SPD_MEMORY_TYPE_SDRAM_DDR) |
| 512 | continue; |
| 513 | |
| 514 | if (smbus_read_byte(channel0_dimm, SPD_MODULE_VOLTAGE) != |
| 515 | SPD_VOLTAGE_SSTL2) |
| 516 | continue; // Unsupported voltage |
| 517 | |
| 518 | // E7501 does not support unregistered DIMMs |
| 519 | spd_value = smbus_read_byte(channel0_dimm, SPD_MODULE_ATTRIBUTES); |
| 520 | if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0)) |
| 521 | continue; |
| 522 | |
| 523 | // Must support burst = 4 for dual-channel operation on E7501 |
| 524 | // NOTE: for single-channel, burst = 8 is required |
| 525 | spd_value = smbus_read_byte(channel0_dimm, |
| 526 | SPD_SUPPORTED_BURST_LENGTHS); |
| 527 | if (!(spd_value & SPD_BURST_LENGTH_4) || (spd_value < 0)) |
| 528 | continue; |
| 529 | |
| 530 | page_size = sdram_spd_get_page_size(channel0_dimm); |
| 531 | sdram_width = sdram_spd_get_width(channel0_dimm); |
| 532 | |
| 533 | // Validate DIMM page size |
| 534 | // The E7501 only supports page sizes of 4, 8, 16, or 32 KB per channel |
| 535 | // NOTE: 4 KB = 32 Kb = 2^15 |
| 536 | // 32 KB = 262 Kb = 2^18 |
| 537 | |
| 538 | if ((page_size.side1 < 15) || (page_size.side1 > 18)) |
| 539 | continue; |
| 540 | |
| 541 | // If DIMM is double-sided, verify side2 page size |
| 542 | if (page_size.side2 != 0) { |
| 543 | if ((page_size.side2 < 15) |
| 544 | || (page_size.side2 > 18)) |
| 545 | continue; |
| 546 | } |
| 547 | // Validate SDRAM width |
| 548 | // The E7501 only supports x4 and x8 devices |
| 549 | |
| 550 | if ((sdram_width.side1 != 4) && (sdram_width.side1 != 8)) |
| 551 | continue; |
| 552 | |
| 553 | // If DIMM is double-sided, verify side2 width |
| 554 | if (sdram_width.side2 != 0) { |
| 555 | if ((sdram_width.side2 != 4) |
| 556 | && (sdram_width.side2 != 8)) |
| 557 | continue; |
| 558 | } |
| 559 | |
| 560 | // Channel 0 DIMM looks compatible. |
| 561 | // Now see if it is paired with the proper DIMM on channel 1. |
| 562 | |
| 563 | ASSERT(channel1_dimm != 0); // No such socket on this mainboard?? |
| 564 | |
| 565 | // NOTE: unpopulated DIMMs cause read to fail |
| 566 | spd_value = smbus_read_byte(channel1_dimm, SPD_MODULE_ATTRIBUTES); |
| 567 | if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0)) { |
| 568 | |
| 569 | printk(BIOS_DEBUG, "Skipping un-matched DIMMs - only dual-channel operation supported\n"); |
| 570 | continue; |
| 571 | } |
| 572 | |
| 573 | spd_value = smbus_read_byte(channel1_dimm, |
| 574 | SPD_SUPPORTED_BURST_LENGTHS); |
| 575 | if (!(spd_value & SPD_BURST_LENGTH_4) || (spd_value < 0)) |
| 576 | continue; |
| 577 | |
| 578 | int j; |
| 579 | for (j = 0; j < sizeof(dual_channel_parameters); ++j) { |
| 580 | if (!are_spd_values_equal |
| 581 | (dual_channel_parameters[j], channel0_dimm, |
| 582 | channel1_dimm)) { |
| 583 | |
| 584 | bDualChannel = 0; |
| 585 | break; |
| 586 | } |
| 587 | } |
| 588 | |
| 589 | if (bDualChannel) { |
| 590 | // This DIMM pair is usable |
| 591 | dimm_mask |= 1 << i; |
| 592 | dimm_mask |= 1 << (MAX_DIMM_SOCKETS_PER_CHANNEL + i); |
| 593 | } else |
| 594 | printk(BIOS_DEBUG, "Skipping un-matched DIMMs - only dual-channel operation supported\n"); |
| 595 | } |
| 596 | |
| 597 | return dimm_mask; |
| 598 | } |
| 599 | |
| 600 | /*----------------------------------------------------------------------------- |
| 601 | SDRAM configuration functions: |
| 602 | -----------------------------------------------------------------------------*/ |
| 603 | |
| 604 | /** |
| 605 | * Send the specified command to all DIMMs. |
| 606 | * |
| 607 | * @param command Specifies the command to be sent to the DIMMs. |
| 608 | * @param jedec_mode_bits For the MRS & EMRS commands, bits 0-12 contain the |
| 609 | * register value in JEDEC format. |
| 610 | */ |
| 611 | static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits) |
| 612 | { |
| 613 | uint8_t dimm_start_64M_multiple; |
| 614 | uintptr_t dimm_start_address; |
| 615 | uint32_t dram_controller_mode; |
| 616 | uint8_t i; |
| 617 | |
| 618 | // Configure the RAM command |
| 619 | dram_controller_mode = pci_read_config32(MCHDEV, DRC); |
| 620 | dram_controller_mode &= 0xFFFFFF8F; |
| 621 | dram_controller_mode |= command; |
| 622 | pci_write_config32(MCHDEV, DRC, dram_controller_mode); |
| 623 | |
| 624 | // RAM_COMMAND_NORMAL is an exception. |
| 625 | // It affects only the memory controller and does not need to be "sent" to the DIMMs. |
| 626 | if (command == RAM_COMMAND_NORMAL) { |
| 627 | EXTRA_DELAY; |
| 628 | return; |
| 629 | } |
| 630 | |
| 631 | // NOTE: for mode select commands, some of the location address bits are part of the command |
| 632 | // Map JEDEC mode bits to E7505 |
| 633 | if (command == RAM_COMMAND_MRS) { |
| 634 | // Host address lines [25:18] map to DIMM address lines [7:0] |
| 635 | // Host address lines [17:16] map to DIMM address lines [9:8] |
| 636 | // Host address lines [15:4] map to DIMM address lines [11:0] |
| 637 | dimm_start_address = (jedec_mode_bits & 0x00ff) << 18; |
| 638 | dimm_start_address |= (jedec_mode_bits & 0x0300) << 8; |
| 639 | dimm_start_address |= (jedec_mode_bits & 0x0fff) << 4; |
| 640 | } else if (command == RAM_COMMAND_EMRS) { |
| 641 | // Host address lines [15:4] map to DIMM address lines [11:0] |
| 642 | dimm_start_address = (jedec_mode_bits << 4); |
| 643 | } else { |
| 644 | ASSERT(jedec_mode_bits == 0); |
| 645 | dimm_start_address = 0; |
| 646 | } |
| 647 | |
| 648 | // Send the command to all DIMMs by accessing a memory location within each |
| 649 | |
| 650 | dimm_start_64M_multiple = 0; |
| 651 | |
| 652 | /* FIXME: Only address the number of rows present in the system? |
| 653 | * Seems like rows 4-7 overlap with 0-3. |
| 654 | */ |
| 655 | for (i = 0; i < (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL); ++i) { |
| 656 | |
| 657 | uint8_t dimm_end_64M_multiple = pci_read_config8(MCHDEV, DRB_ROW_0 + i); |
| 658 | |
| 659 | if (dimm_end_64M_multiple > dimm_start_64M_multiple) { |
| 660 | dimm_start_address &= 0x3ffffff; |
| 661 | dimm_start_address |= dimm_start_64M_multiple << 26; |
Elyes Haouas | 421f1ee | 2022-12-03 13:26:05 +0100 | [diff] [blame] | 662 | read32p(dimm_start_address); |
Kyösti Mälkki | 7b73e852 | 2022-11-08 04:43:41 +0000 | [diff] [blame] | 663 | // Set the start of the next DIMM |
| 664 | dimm_start_64M_multiple = dimm_end_64M_multiple; |
| 665 | } |
| 666 | } |
| 667 | EXTRA_DELAY; |
| 668 | } |
| 669 | |
| 670 | /** |
| 671 | * Set the mode register of all DIMMs. |
| 672 | * |
| 673 | * The proper CAS# latency setting is added to the mode bits specified |
| 674 | * by the caller. |
| 675 | * |
| 676 | * @param jedec_mode_bits For the MRS & EMRS commands, bits 0-12 contain the |
| 677 | * register value in JEDEC format. |
| 678 | */ |
| 679 | static void set_ram_mode(uint16_t jedec_mode_bits) |
| 680 | { |
| 681 | ASSERT(!(jedec_mode_bits & SDRAM_CAS_MASK)); |
| 682 | |
| 683 | uint32_t dram_cas_latency = |
| 684 | pci_read_config32(MCHDEV, DRT) & DRT_CAS_MASK; |
| 685 | |
| 686 | switch (dram_cas_latency) { |
| 687 | case DRT_CAS_2_5: |
| 688 | jedec_mode_bits |= SDRAM_CAS_2_5; |
| 689 | break; |
| 690 | |
| 691 | case DRT_CAS_2_0: |
| 692 | jedec_mode_bits |= SDRAM_CAS_2_0; |
| 693 | break; |
| 694 | |
| 695 | default: |
| 696 | BUG(); |
| 697 | break; |
| 698 | } |
| 699 | |
| 700 | do_ram_command(RAM_COMMAND_MRS, jedec_mode_bits); |
| 701 | } |
| 702 | |
| 703 | /*----------------------------------------------------------------------------- |
| 704 | DIMM-independent configuration functions: |
| 705 | -----------------------------------------------------------------------------*/ |
| 706 | |
| 707 | /** |
| 708 | * Configure the E7501's DRAM Row Boundary (DRB) registers for the memory |
| 709 | * present in the specified DIMM. |
| 710 | * |
| 711 | * @param dimm_log2_num_bits Specifies log2(number of bits) for each side of |
| 712 | * the DIMM. |
| 713 | * @param total_dram_64M_multiple Total DRAM in the system (as a multiple of |
| 714 | * 64 MB) for DIMMs < dimm_index. |
| 715 | * @param dimm_index Which DIMM pair is being processed |
| 716 | * (0..MAX_DIMM_SOCKETS_PER_CHANNEL). |
| 717 | * @return New multiple of 64 MB total DRAM in the system. |
| 718 | */ |
| 719 | static uint8_t configure_dimm_row_boundaries(struct dimm_size dimm_log2_num_bits, uint8_t total_dram_64M_multiple, unsigned int dimm_index) |
| 720 | { |
| 721 | int i; |
| 722 | |
| 723 | ASSERT(dimm_index < MAX_DIMM_SOCKETS_PER_CHANNEL); |
| 724 | |
| 725 | // DIMM sides must be at least 32 MB |
| 726 | ASSERT(dimm_log2_num_bits.side1 >= 28); |
| 727 | ASSERT((dimm_log2_num_bits.side2 == 0) |
| 728 | || (dimm_log2_num_bits.side2 >= 28)); |
| 729 | |
| 730 | // In dual-channel mode, we are called only once for each pair of DIMMs. |
| 731 | // Each time we process twice the capacity of a single DIMM. |
| 732 | |
| 733 | // Convert single DIMM capacity to paired DIMM capacity |
| 734 | // (multiply by two ==> add 1 to log2) |
| 735 | dimm_log2_num_bits.side1++; |
| 736 | if (dimm_log2_num_bits.side2 > 0) |
| 737 | dimm_log2_num_bits.side2++; |
| 738 | |
| 739 | // Add the capacity of side 1 this DIMM pair (as a multiple of 64 MB) |
| 740 | // to the total capacity of the system |
| 741 | // NOTE: 64 MB == 512 Mb, and log2(512 Mb) == 29 |
| 742 | |
| 743 | total_dram_64M_multiple += (1 << (dimm_log2_num_bits.side1 - 29)); |
| 744 | |
| 745 | // Configure the boundary address for the row on side 1 |
| 746 | pci_write_config8(MCHDEV, DRB_ROW_0 + (dimm_index << 1), |
| 747 | total_dram_64M_multiple); |
| 748 | |
| 749 | // If the DIMMs are double-sided, add the capacity of side 2 this DIMM pair |
| 750 | // (as a multiple of 64 MB) to the total capacity of the system |
| 751 | if (dimm_log2_num_bits.side2 >= 29) |
| 752 | total_dram_64M_multiple += |
| 753 | (1 << (dimm_log2_num_bits.side2 - 29)); |
| 754 | |
| 755 | // Configure the boundary address for the row (if any) on side 2 |
| 756 | pci_write_config8(MCHDEV, DRB_ROW_1 + (dimm_index << 1), |
| 757 | total_dram_64M_multiple); |
| 758 | |
| 759 | // Update boundaries for rows subsequent to these. |
| 760 | // These settings will be overridden by a subsequent call if a populated physical slot exists |
| 761 | |
| 762 | for (i = dimm_index + 1; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) { |
| 763 | pci_write_config8(MCHDEV, DRB_ROW_0 + (i << 1), |
| 764 | total_dram_64M_multiple); |
| 765 | pci_write_config8(MCHDEV, DRB_ROW_1 + (i << 1), |
| 766 | total_dram_64M_multiple); |
| 767 | } |
| 768 | |
| 769 | return total_dram_64M_multiple; |
| 770 | } |
| 771 | |
| 772 | /** |
| 773 | * Set the E7501's DRAM row boundary addresses & its Top Of Low Memory (TOLM). |
| 774 | * |
| 775 | * If necessary, set up a remap window so we don't waste DRAM that ordinarily |
| 776 | * would lie behind addresses reserved for memory-mapped I/O. |
| 777 | * |
| 778 | * @param ctrl PCI addresses of memory controller functions, and SMBus |
| 779 | * addresses of DIMM slots on the mainboard. |
| 780 | * @param dimm_mask Bitmask of populated DIMMs, see spd_get_supported_dimms(). |
| 781 | */ |
| 782 | static void configure_e7501_ram_addresses(const struct mem_controller |
| 783 | *ctrl, uint8_t dimm_mask) |
| 784 | { |
| 785 | int i; |
| 786 | uint8_t total_dram_64M_multiple = 0; |
| 787 | uint64_t tolm, tom; |
| 788 | uint16_t reg; |
| 789 | |
| 790 | /* FIXME: Is there standard presence detect bit somewhere. */ |
| 791 | const int agp_slot_disabled = 1; |
| 792 | |
| 793 | /* Start with disabled remap range. */ |
| 794 | uint16_t remapbase_r = 0x3ff; |
| 795 | uint16_t remaplimit_r = 0; |
| 796 | |
| 797 | // Configure the E7501's DRAM row boundaries |
| 798 | // Start by zeroing out the temporary initial configuration |
| 799 | pci_write_config32(MCHDEV, DRB_ROW_0, 0); |
| 800 | pci_write_config32(MCHDEV, DRB_ROW_4, 0); |
| 801 | |
| 802 | for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) { |
| 803 | |
| 804 | uint16_t dimm_socket_address = ctrl->channel0[i]; |
| 805 | struct dimm_size sz; |
| 806 | |
| 807 | if (!(dimm_mask & (1 << i))) |
| 808 | continue; // This DIMM not present |
| 809 | |
| 810 | sz = spd_get_dimm_size(dimm_socket_address); |
| 811 | |
| 812 | RAM_DEBUG_MESSAGE("dimm size ="); |
| 813 | RAM_DEBUG_HEX32((u32)sz.side1); |
| 814 | RAM_DEBUG_MESSAGE(" "); |
| 815 | RAM_DEBUG_HEX32((u32)sz.side2); |
| 816 | RAM_DEBUG_MESSAGE("\n"); |
| 817 | |
| 818 | if (sz.side1 == 0) |
| 819 | die("Bad SPD value\n"); |
| 820 | |
| 821 | total_dram_64M_multiple = |
| 822 | configure_dimm_row_boundaries(sz, total_dram_64M_multiple, i); |
| 823 | } |
| 824 | |
| 825 | tom = total_dram_64M_multiple * 64ULL * MiB; |
| 826 | |
| 827 | /* Reserve MMIO space. */ |
| 828 | tolm = 4ULL * GiB - 512 * MiB; |
| 829 | if (agp_slot_disabled) { |
| 830 | /* Reduce apertures to 2 x 4 MiB. */ |
| 831 | pci_write_config8(MCHDEV, APSIZE, 0x3F); |
| 832 | pci_write_config16(AGPDEV, APSIZE1, 0x3F); |
| 833 | } else { |
| 834 | /* Add MMIO reserve for 2 x 256 MiB apertures. */ |
| 835 | tolm -= 512 * MiB; |
| 836 | } |
| 837 | tolm = MIN(tolm, tom); |
| 838 | |
| 839 | /* The PCI memory hole overlaps memory setup the remap window. */ |
| 840 | if (tolm < tom) { |
| 841 | uint64_t remapbase = MAX(tom, 4ULL * GiB); |
| 842 | uint64_t remaplimit = remapbase + (4ULL * GiB - tolm); |
| 843 | |
| 844 | remapbase_r = remapbase / (64 * MiB); |
| 845 | remaplimit_r = remaplimit / (64 * MiB); |
| 846 | |
| 847 | /* Limit register is inclusive. */ |
| 848 | remaplimit_r -= 1; |
| 849 | } |
| 850 | |
| 851 | /* Write the RAM configuration registers, |
| 852 | preserving the reserved bits. */ |
| 853 | reg = pci_read_config16(MCHDEV, TOLM) & 0x7ff; |
| 854 | reg |= (tolm / (128 * MiB)) << 11; |
| 855 | pci_write_config16(MCHDEV, TOLM, reg); |
| 856 | |
| 857 | reg = pci_read_config16(MCHDEV, REMAPBASE) & 0xfc00; |
| 858 | reg |= remapbase_r; |
| 859 | pci_write_config16(MCHDEV, REMAPBASE, reg); |
| 860 | |
| 861 | reg = pci_read_config16(MCHDEV, REMAPLIMIT) & 0xfc00; |
| 862 | reg |= remaplimit_r; |
| 863 | pci_write_config16(MCHDEV, REMAPLIMIT, reg); |
| 864 | } |
| 865 | |
| 866 | /** |
| 867 | * Program the DRAM Timing register (DRT) of the E7501 (except for CAS# |
| 868 | * latency, which is assumed to have been programmed already), based on the |
| 869 | * parameters of the various installed DIMMs. |
| 870 | * |
| 871 | * @param ctrl PCI addresses of memory controller functions, and SMBus |
| 872 | * addresses of DIMM slots on the mainboard. |
| 873 | * @param dimm_mask Bitmask of populated DIMMs, see spd_get_supported_dimms(). |
| 874 | */ |
| 875 | static void configure_e7501_dram_timing(const struct mem_controller *ctrl, |
| 876 | uint8_t dimm_mask) |
| 877 | { |
| 878 | int i; |
| 879 | uint32_t dram_timing; |
| 880 | int value; |
| 881 | uint8_t slowest_row_precharge = 0; |
| 882 | uint8_t slowest_ras_cas_delay = 0; |
| 883 | uint8_t slowest_active_to_precharge_delay = 0; |
| 884 | uint32_t current_cas_latency = |
| 885 | pci_read_config32(MCHDEV, DRT) & DRT_CAS_MASK; |
| 886 | |
| 887 | // CAS# latency must be programmed beforehand |
| 888 | ASSERT((current_cas_latency == DRT_CAS_2_0) |
| 889 | || (current_cas_latency == DRT_CAS_2_5)); |
| 890 | |
| 891 | // Each timing parameter is determined by the slowest DIMM |
| 892 | |
| 893 | for (i = 0; i < MAX_DIMM_SOCKETS; i++) { |
| 894 | uint16_t dimm_socket_address; |
| 895 | |
| 896 | if (!(dimm_mask & (1 << i))) |
| 897 | continue; // This DIMM not present |
| 898 | |
| 899 | if (i < MAX_DIMM_SOCKETS_PER_CHANNEL) |
| 900 | dimm_socket_address = ctrl->channel0[i]; |
| 901 | else |
| 902 | dimm_socket_address = |
| 903 | ctrl->channel1[i - MAX_DIMM_SOCKETS_PER_CHANNEL]; |
| 904 | |
| 905 | value = smbus_read_byte(dimm_socket_address, |
| 906 | SPD_MIN_ROW_PRECHARGE_TIME); |
| 907 | if (value < 0) |
| 908 | goto hw_err; |
| 909 | if (value > slowest_row_precharge) |
| 910 | slowest_row_precharge = value; |
| 911 | |
| 912 | value = smbus_read_byte(dimm_socket_address, |
| 913 | SPD_MIN_RAS_TO_CAS_DELAY); |
| 914 | if (value < 0) |
| 915 | goto hw_err; |
| 916 | if (value > slowest_ras_cas_delay) |
| 917 | slowest_ras_cas_delay = value; |
| 918 | |
| 919 | value = smbus_read_byte(dimm_socket_address, |
| 920 | SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY); |
| 921 | if (value < 0) |
| 922 | goto hw_err; |
| 923 | if (value > slowest_active_to_precharge_delay) |
| 924 | slowest_active_to_precharge_delay = value; |
| 925 | } |
| 926 | |
| 927 | // NOTE for timing parameters: |
| 928 | // At 133 MHz, 1 clock == 7.52 ns |
| 929 | |
| 930 | /* Read the initial state */ |
| 931 | dram_timing = pci_read_config32(MCHDEV, DRT); |
| 932 | |
| 933 | /* Trp */ |
| 934 | |
| 935 | // E7501 supports only 2 or 3 clocks for tRP |
| 936 | if (slowest_row_precharge > ((22 << 2) | (2 << 0))) |
| 937 | die("unsupported DIMM tRP"); // > 22.5 ns: 4 or more clocks |
| 938 | else if (slowest_row_precharge > (15 << 2)) |
| 939 | dram_timing &= ~(1 << 0); // > 15.0 ns: 3 clocks |
| 940 | else |
| 941 | dram_timing |= (1 << 0); // <= 15.0 ns: 2 clocks |
| 942 | |
| 943 | /* Trcd */ |
| 944 | |
| 945 | // E7501 supports only 2 or 3 clocks for tRCD |
| 946 | // Use the same value for both read & write |
| 947 | dram_timing &= ~((1 << 3) | (3 << 1)); |
| 948 | if (slowest_ras_cas_delay > ((22 << 2) | (2 << 0))) |
| 949 | die("unsupported DIMM tRCD"); // > 22.5 ns: 4 or more clocks |
| 950 | else if (slowest_ras_cas_delay > (15 << 2)) |
| 951 | dram_timing |= (2 << 1); // > 15.0 ns: 3 clocks |
| 952 | else |
| 953 | dram_timing |= ((1 << 3) | (3 << 1)); // <= 15.0 ns: 2 clocks |
| 954 | |
| 955 | /* Tras */ |
| 956 | |
| 957 | // E7501 supports only 5, 6, or 7 clocks for tRAS |
| 958 | // 5 clocks ~= 37.6 ns, 6 clocks ~= 45.1 ns, 7 clocks ~= 52.6 ns |
| 959 | dram_timing &= ~(3 << 9); |
| 960 | |
| 961 | if (slowest_active_to_precharge_delay > 52) |
| 962 | die("unsupported DIMM tRAS"); // > 52 ns: 8 or more clocks |
| 963 | else if (slowest_active_to_precharge_delay > 45) |
| 964 | dram_timing |= (0 << 9); // 46-52 ns: 7 clocks |
| 965 | else if (slowest_active_to_precharge_delay > 37) |
| 966 | dram_timing |= (1 << 9); // 38-45 ns: 6 clocks |
| 967 | else |
| 968 | dram_timing |= (2 << 9); // < 38 ns: 5 clocks |
| 969 | |
| 970 | /* Trd */ |
| 971 | |
| 972 | /* Set to a 7 clock read delay. This is for 133MHz |
| 973 | * with a CAS latency of 2.5 if 2.0 a 6 clock |
| 974 | * delay is good */ |
| 975 | |
| 976 | dram_timing &= ~(7 << 24); // 7 clocks |
| 977 | if (current_cas_latency == DRT_CAS_2_0) |
| 978 | dram_timing |= (1 << 24); // 6 clocks |
| 979 | |
| 980 | /* |
| 981 | * Back to Back Read-Write Turn Around |
| 982 | */ |
| 983 | /* Set to a 5 clock back to back read to write turn around. |
| 984 | * 4 is a good delay if the CAS latency is 2.0 */ |
| 985 | |
| 986 | dram_timing &= ~(1 << 28); // 5 clocks |
| 987 | if (current_cas_latency == DRT_CAS_2_0) |
| 988 | dram_timing |= (1 << 28); // 4 clocks |
| 989 | |
| 990 | pci_write_config32(MCHDEV, DRT, dram_timing); |
| 991 | |
| 992 | return; |
| 993 | |
| 994 | hw_err: |
| 995 | die(SPD_ERROR); |
| 996 | } |
| 997 | |
| 998 | /** |
| 999 | * Determine the shortest CAS# latency that the E7501 and all DIMMs have in |
| 1000 | * common, and program the E7501 to use it. |
| 1001 | * |
| 1002 | * @param ctrl PCI addresses of memory controller functions, and SMBus |
| 1003 | * addresses of DIMM slots on the mainboard. |
| 1004 | * @param dimm_mask Bitmask of populated DIMMs, spd_get_supported_dimms(). |
| 1005 | */ |
| 1006 | static void configure_e7501_cas_latency(const struct mem_controller *ctrl, |
| 1007 | uint8_t dimm_mask) |
| 1008 | { |
| 1009 | int i; |
| 1010 | int value; |
| 1011 | uint32_t dram_timing; |
| 1012 | uint16_t dram_read_timing; |
| 1013 | uint32_t dword; |
| 1014 | |
| 1015 | // CAS# latency bitmasks in SPD_ACCEPTABLE_CAS_LATENCIES format |
| 1016 | // NOTE: E7501 supports only 2.0 and 2.5 |
| 1017 | uint32_t system_compatible_cas_latencies = |
| 1018 | SPD_CAS_LATENCY_2_0 | SPD_CAS_LATENCY_2_5; |
| 1019 | uint32_t current_cas_latency; |
| 1020 | uint32_t dimm_compatible_cas_latencies; |
| 1021 | |
| 1022 | for (i = 0; i < MAX_DIMM_SOCKETS; i++) { |
| 1023 | |
| 1024 | uint16_t dimm_socket_address; |
| 1025 | |
| 1026 | if (!(dimm_mask & (1 << i))) |
| 1027 | continue; // This DIMM not usable |
| 1028 | |
| 1029 | if (i < MAX_DIMM_SOCKETS_PER_CHANNEL) |
| 1030 | dimm_socket_address = ctrl->channel0[i]; |
| 1031 | else |
| 1032 | dimm_socket_address = |
| 1033 | ctrl->channel1[i - MAX_DIMM_SOCKETS_PER_CHANNEL]; |
| 1034 | |
| 1035 | value = smbus_read_byte(dimm_socket_address, |
| 1036 | SPD_ACCEPTABLE_CAS_LATENCIES); |
| 1037 | if (value < 0) |
| 1038 | goto hw_err; |
| 1039 | |
| 1040 | dimm_compatible_cas_latencies = value & 0x7f; // Start with all supported by DIMM |
| 1041 | current_cas_latency = 1 << log2(dimm_compatible_cas_latencies); // Max supported by DIMM |
| 1042 | |
| 1043 | // Can we support the highest CAS# latency? |
| 1044 | |
| 1045 | value = smbus_read_byte(dimm_socket_address, |
| 1046 | SPD_MIN_CYCLE_TIME_AT_CAS_MAX); |
| 1047 | if (value < 0) |
| 1048 | goto hw_err; |
| 1049 | |
| 1050 | // NOTE: At 133 MHz, 1 clock == 7.52 ns |
| 1051 | if (value > 0x75) { |
| 1052 | // Our bus is too fast for this CAS# latency |
| 1053 | // Remove it from the bitmask of those supported by the DIMM that are compatible |
| 1054 | dimm_compatible_cas_latencies &= ~current_cas_latency; |
| 1055 | } |
| 1056 | // Can we support the next-highest CAS# latency (max - 0.5)? |
| 1057 | |
| 1058 | current_cas_latency >>= 1; |
| 1059 | if (current_cas_latency != 0) { |
| 1060 | value = smbus_read_byte(dimm_socket_address, |
| 1061 | SPD_SDRAM_CYCLE_TIME_2ND); |
| 1062 | if (value < 0) |
| 1063 | goto hw_err; |
| 1064 | if (value > 0x75) |
| 1065 | dimm_compatible_cas_latencies &= |
| 1066 | ~current_cas_latency; |
| 1067 | } |
| 1068 | // Can we support the next-highest CAS# latency (max - 1.0)? |
| 1069 | current_cas_latency >>= 1; |
| 1070 | if (current_cas_latency != 0) { |
| 1071 | value = smbus_read_byte(dimm_socket_address, |
| 1072 | SPD_SDRAM_CYCLE_TIME_3RD); |
| 1073 | if (value < 0) |
| 1074 | goto hw_err; |
| 1075 | if (value > 0x75) |
| 1076 | dimm_compatible_cas_latencies &= |
| 1077 | ~current_cas_latency; |
| 1078 | } |
| 1079 | // Restrict the system to CAS# latencies compatible with this DIMM |
| 1080 | system_compatible_cas_latencies &= |
| 1081 | dimm_compatible_cas_latencies; |
| 1082 | |
| 1083 | /* go to the next DIMM */ |
| 1084 | } |
| 1085 | |
| 1086 | /* After all of the arduous calculation setup with the fastest |
| 1087 | * cas latency I can use. |
| 1088 | */ |
| 1089 | |
| 1090 | dram_timing = pci_read_config32(MCHDEV, DRT); |
| 1091 | dram_timing &= ~(DRT_CAS_MASK); |
| 1092 | |
| 1093 | dram_read_timing = |
| 1094 | pci_read_config16(MCHDEV, DRDCTL); |
| 1095 | dram_read_timing &= 0xF000; |
| 1096 | |
| 1097 | if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_0) { |
| 1098 | dram_timing |= DRT_CAS_2_0; |
| 1099 | dram_read_timing |= 0x0222; |
| 1100 | } else if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_5) { |
| 1101 | |
| 1102 | uint32_t dram_row_attributes = |
| 1103 | pci_read_config32(MCHDEV, DRA); |
| 1104 | |
| 1105 | dram_timing |= DRT_CAS_2_5; |
| 1106 | |
| 1107 | // At CAS# 2.5, DRAM Read Timing (if that's what it its) appears to need a slightly |
| 1108 | // different value if all DIMM slots are populated |
| 1109 | |
| 1110 | if ((dram_row_attributes & 0xff) |
| 1111 | && (dram_row_attributes & 0xff00) |
| 1112 | && (dram_row_attributes & 0xff0000) |
| 1113 | && (dram_row_attributes & 0xff000000)) { |
| 1114 | |
| 1115 | // All slots populated |
| 1116 | dram_read_timing |= 0x0882; |
| 1117 | } else { |
| 1118 | // Some unpopulated slots |
| 1119 | dram_read_timing |= 0x0662; |
| 1120 | } |
| 1121 | } else |
| 1122 | die("No CAS# latencies compatible with all DIMMs!!\n"); |
| 1123 | |
| 1124 | pci_write_config32(MCHDEV, DRT, dram_timing); |
| 1125 | |
| 1126 | /* set master DLL reset */ |
| 1127 | dword = pci_read_config32(MCHDEV, 0x88); |
| 1128 | dword |= (1 << 26); |
| 1129 | pci_write_config32(MCHDEV, 0x88, dword); |
| 1130 | /* patch try register 88 is undocumented tnz */ |
| 1131 | dword &= 0x0ca17fff; |
| 1132 | dword |= 0xd14a5000; |
| 1133 | pci_write_config32(MCHDEV, 0x88, dword); |
| 1134 | |
| 1135 | pci_write_config16(MCHDEV, DRDCTL, |
| 1136 | dram_read_timing); |
| 1137 | |
| 1138 | /* clear master DLL reset */ |
| 1139 | dword = pci_read_config32(MCHDEV, 0x88); |
| 1140 | dword &= ~(1 << 26); |
| 1141 | pci_write_config32(MCHDEV, 0x88, dword); |
| 1142 | |
| 1143 | return; |
| 1144 | |
| 1145 | hw_err: |
| 1146 | die(SPD_ERROR); |
| 1147 | } |
| 1148 | |
| 1149 | /** |
| 1150 | * Configure the refresh interval so that we refresh no more often than |
| 1151 | * required by the "most needy" DIMM. Also disable ECC if any of the DIMMs |
| 1152 | * don't support it. |
| 1153 | * |
| 1154 | * @param ctrl PCI addresses of memory controller functions, and SMBus |
| 1155 | * addresses of DIMM slots on the mainboard. |
| 1156 | * @param dimm_mask Bitmask of populated DIMMs, spd_get_supported_dimms(). |
| 1157 | */ |
| 1158 | static void configure_e7501_dram_controller_mode(const struct mem_controller *ctrl, |
| 1159 | uint8_t dimm_mask) |
| 1160 | { |
| 1161 | int i; |
| 1162 | |
| 1163 | // Initial settings |
| 1164 | uint32_t controller_mode = pci_read_config32(MCHDEV, DRC); |
| 1165 | uint32_t system_refresh_mode = (controller_mode >> 8) & 7; |
| 1166 | |
| 1167 | // Code below assumes that most aggressive settings are in |
| 1168 | // force when we are called, either via E7501 reset defaults |
| 1169 | // or by sdram_set_registers(): |
| 1170 | // - ECC enabled |
| 1171 | // - No refresh |
| 1172 | |
| 1173 | ASSERT((controller_mode & (3 << 20)) == (2 << 20)); // ECC |
| 1174 | ASSERT(!(controller_mode & (7 << 8))); // Refresh |
| 1175 | |
| 1176 | /* Walk through _all_ dimms and find the least-common denominator for: |
| 1177 | * - ECC support |
| 1178 | * - refresh rates |
| 1179 | */ |
| 1180 | |
| 1181 | for (i = 0; i < MAX_DIMM_SOCKETS; i++) { |
| 1182 | |
| 1183 | uint32_t dimm_refresh_mode; |
| 1184 | int value; |
| 1185 | uint16_t dimm_socket_address; |
| 1186 | |
| 1187 | if (!(dimm_mask & (1 << i))) { |
| 1188 | continue; // This DIMM not usable |
| 1189 | } |
| 1190 | |
| 1191 | if (i < MAX_DIMM_SOCKETS_PER_CHANNEL) |
| 1192 | dimm_socket_address = ctrl->channel0[i]; |
| 1193 | else |
| 1194 | dimm_socket_address = |
| 1195 | ctrl->channel1[i - |
| 1196 | MAX_DIMM_SOCKETS_PER_CHANNEL]; |
| 1197 | |
| 1198 | // Disable ECC mode if any one of the DIMMs does not support ECC |
| 1199 | // SJM: Should we just die here? E7501 datasheet says non-ECC DIMMs aren't supported. |
| 1200 | |
| 1201 | value = smbus_read_byte(dimm_socket_address, |
| 1202 | SPD_DIMM_CONFIG_TYPE); |
| 1203 | die_on_spd_error(value); |
| 1204 | if (value != ERROR_SCHEME_ECC) { |
| 1205 | controller_mode &= ~(3 << 20); |
| 1206 | } |
| 1207 | |
| 1208 | value = smbus_read_byte(dimm_socket_address, SPD_REFRESH); |
| 1209 | die_on_spd_error(value); |
| 1210 | value &= 0x7f; // Mask off self-refresh bit |
| 1211 | if (value > MAX_SPD_REFRESH_RATE) { |
| 1212 | printk(BIOS_ERR, "unsupported refresh rate\n"); |
| 1213 | continue; |
| 1214 | } |
| 1215 | // Get the appropriate E7501 refresh mode for this DIMM |
| 1216 | dimm_refresh_mode = refresh_rate_map[value]; |
| 1217 | if (dimm_refresh_mode > 7) { |
| 1218 | printk(BIOS_ERR, "unsupported refresh rate\n"); |
| 1219 | continue; |
| 1220 | } |
| 1221 | // If this DIMM requires more frequent refresh than others, |
| 1222 | // update the system setting |
| 1223 | if (refresh_frequency[dimm_refresh_mode] > |
| 1224 | refresh_frequency[system_refresh_mode]) |
| 1225 | system_refresh_mode = dimm_refresh_mode; |
| 1226 | |
| 1227 | /* go to the next DIMM */ |
| 1228 | } |
| 1229 | |
| 1230 | controller_mode |= (system_refresh_mode << 8); |
| 1231 | |
| 1232 | // Configure the E7501 |
| 1233 | pci_write_config32(MCHDEV, DRC, controller_mode); |
| 1234 | } |
| 1235 | |
| 1236 | /** |
| 1237 | * Configure the E7501's DRAM Row Attributes (DRA) registers based on DIMM |
| 1238 | * parameters read via SPD. This tells the controller the width of the SDRAM |
| 1239 | * chips on each DIMM side (x4 or x8) and the page size of each DIMM side |
| 1240 | * (4, 8, 16, or 32 KB). |
| 1241 | * |
| 1242 | * @param ctrl PCI addresses of memory controller functions, and SMBus |
| 1243 | * addresses of DIMM slots on the mainboard. |
| 1244 | * @param dimm_mask Bitmask of populated DIMMs, spd_get_supported_dimms(). |
| 1245 | */ |
| 1246 | static void configure_e7501_row_attributes(const struct mem_controller |
| 1247 | *ctrl, uint8_t dimm_mask) |
| 1248 | { |
| 1249 | int i; |
| 1250 | uint32_t row_attributes = 0; |
| 1251 | |
| 1252 | for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) { |
| 1253 | |
| 1254 | uint16_t dimm_socket_address = ctrl->channel0[i]; |
| 1255 | struct dimm_size page_size; |
| 1256 | struct dimm_size sdram_width; |
| 1257 | |
| 1258 | if (!(dimm_mask & (1 << i))) |
| 1259 | continue; // This DIMM not usable |
| 1260 | |
| 1261 | // Get the relevant parameters via SPD |
| 1262 | page_size = sdram_spd_get_page_size(dimm_socket_address); |
| 1263 | sdram_width = sdram_spd_get_width(dimm_socket_address); |
| 1264 | |
| 1265 | // Update the DRAM Row Attributes. |
| 1266 | // Page size is encoded as log2(page size in bits) - log2(8 Kb) |
| 1267 | // NOTE: 8 Kb = 2^13 |
| 1268 | row_attributes |= (page_size.side1 - 13) << (i << 3); // Side 1 of each DIMM is an EVEN row |
| 1269 | |
| 1270 | if (sdram_width.side2 > 0) |
| 1271 | row_attributes |= (page_size.side2 - 13) << ((i << 3) + 4); // Side 2 is ODD |
| 1272 | |
| 1273 | // Set x4 flags if appropriate |
| 1274 | if (sdram_width.side1 == 4) { |
| 1275 | row_attributes |= 0x08 << (i << 3); |
| 1276 | } |
| 1277 | |
| 1278 | if (sdram_width.side2 == 4) { |
| 1279 | row_attributes |= 0x08 << ((i << 3) + 4); |
| 1280 | } |
| 1281 | |
| 1282 | /* go to the next DIMM */ |
| 1283 | } |
| 1284 | |
| 1285 | /* Write the new row attributes register */ |
| 1286 | pci_write_config32(MCHDEV, DRA, row_attributes); |
| 1287 | } |
| 1288 | |
| 1289 | /* |
| 1290 | * Enable clock signals for populated DIMM sockets and disable them for |
| 1291 | * unpopulated sockets (to reduce EMI). |
| 1292 | * |
| 1293 | * @param dimm_mask Bitmask of populated DIMMs, see spd_get_supported_dimms(). |
| 1294 | */ |
| 1295 | static void enable_e7501_clocks(uint8_t dimm_mask) |
| 1296 | { |
| 1297 | int i; |
| 1298 | uint8_t clock_disable = pci_read_config8(MCHDEV, CKDIS); |
| 1299 | |
| 1300 | pci_write_config8(MCHDEV, 0x8e, 0xb0); |
| 1301 | |
| 1302 | for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) { |
| 1303 | |
| 1304 | uint8_t socket_mask = 1 << i; |
| 1305 | |
| 1306 | if (dimm_mask & socket_mask) |
| 1307 | clock_disable &= ~socket_mask; // DIMM present, enable clock |
| 1308 | else |
| 1309 | clock_disable |= socket_mask; // DIMM absent, disable clock |
| 1310 | } |
| 1311 | |
| 1312 | pci_write_config8(MCHDEV, CKDIS, clock_disable); |
| 1313 | } |
| 1314 | |
| 1315 | /* DIMM-dependent configuration functions */ |
| 1316 | |
| 1317 | /** |
| 1318 | * DDR Receive FIFO RE-Sync (?) |
| 1319 | */ |
| 1320 | static void RAM_RESET_DDR_PTR(void) |
| 1321 | { |
| 1322 | uint8_t byte; |
| 1323 | byte = pci_read_config8(MCHDEV, 0x88); |
| 1324 | byte |= (1 << 4); |
| 1325 | pci_write_config8(MCHDEV, 0x88, byte); |
| 1326 | |
| 1327 | byte = pci_read_config8(MCHDEV, 0x88); |
| 1328 | byte &= ~(1 << 4); |
| 1329 | pci_write_config8(MCHDEV, 0x88, byte); |
| 1330 | } |
| 1331 | |
| 1332 | /** |
| 1333 | * Copy 64 bytes from one location to another. |
| 1334 | * |
| 1335 | * @param src_addr TODO |
| 1336 | * @param dst_addr TODO |
| 1337 | */ |
| 1338 | static void write_8dwords(const uint32_t *src_addr, u8 *dst_addr) |
| 1339 | { |
| 1340 | int i; |
| 1341 | for (i = 0; i < 8; i++) { |
| 1342 | write32(dst_addr, *src_addr); |
| 1343 | src_addr++; |
| 1344 | dst_addr += sizeof(uint32_t); |
| 1345 | } |
| 1346 | } |
| 1347 | |
| 1348 | /** |
| 1349 | * Set the E7501's (undocumented) RCOMP registers. |
| 1350 | * |
| 1351 | * Per the 855PM datasheet and IXP2800 HW Initialization Reference Manual, |
| 1352 | * RCOMP registers appear to affect drive strength, pullup/pulldown offset, |
| 1353 | * and slew rate of various signal groups. |
| 1354 | * |
| 1355 | * Comments below are conjecture based on apparent similarity between the |
| 1356 | * E7501 and these two chips. |
| 1357 | */ |
| 1358 | static void rcomp_copy_registers(void) |
| 1359 | { |
| 1360 | uint32_t dword; |
| 1361 | uint8_t strength_control; |
| 1362 | |
| 1363 | RAM_DEBUG_MESSAGE("Setting RCOMP registers.\n"); |
| 1364 | |
| 1365 | /* Begin to write the RCOMP registers */ |
| 1366 | write8(RCOMP_MMIO + 0x2c, 0x0); |
| 1367 | |
| 1368 | // Set CMD and DQ/DQS strength to 2x (?) |
| 1369 | strength_control = read8(RCOMP_MMIO + DQCMDSTR) & 0x88; |
| 1370 | strength_control |= 0x40; |
| 1371 | write8(RCOMP_MMIO + DQCMDSTR, strength_control); |
| 1372 | write_8dwords(slew_2x, RCOMP_MMIO + 0x80); |
| 1373 | write16(RCOMP_MMIO + 0x42, 0); |
| 1374 | |
| 1375 | // Set CMD and DQ/DQS strength to 2x (?) |
| 1376 | strength_control = read8(RCOMP_MMIO + DQCMDSTR) & 0xF8; |
| 1377 | strength_control |= 0x04; |
| 1378 | write8(RCOMP_MMIO + DQCMDSTR, strength_control); |
| 1379 | write_8dwords(slew_2x, RCOMP_MMIO + 0x60); |
| 1380 | write16(RCOMP_MMIO + 0x40, 0); |
| 1381 | |
| 1382 | // Set RCVEnOut# strength to 2x (?) |
| 1383 | strength_control = read8(RCOMP_MMIO + RCVENSTR) & 0xF8; |
| 1384 | strength_control |= 0x04; |
| 1385 | write8(RCOMP_MMIO + RCVENSTR, strength_control); |
| 1386 | write_8dwords(slew_2x, RCOMP_MMIO + 0x1c0); |
| 1387 | write16(RCOMP_MMIO + 0x50, 0); |
| 1388 | |
| 1389 | // Set CS# strength for x4 SDRAM to 2x (?) |
| 1390 | strength_control = read8(RCOMP_MMIO + CSBSTR) & 0x88; |
| 1391 | strength_control |= 0x04; |
| 1392 | write8(RCOMP_MMIO + CSBSTR, strength_control); |
| 1393 | write_8dwords(slew_2x, RCOMP_MMIO + 0x140); |
| 1394 | write16(RCOMP_MMIO + 0x48, 0); |
| 1395 | |
| 1396 | // Set CS# strength for x4 SDRAM to 2x (?) |
| 1397 | strength_control = read8(RCOMP_MMIO + CSBSTR) & 0x8F; |
| 1398 | strength_control |= 0x40; |
| 1399 | write8(RCOMP_MMIO + CSBSTR, strength_control); |
| 1400 | write_8dwords(slew_2x, RCOMP_MMIO + 0x160); |
| 1401 | write16(RCOMP_MMIO + 0x4a, 0); |
| 1402 | |
| 1403 | // Set CKE strength for x4 SDRAM to 2x (?) |
| 1404 | strength_control = read8(RCOMP_MMIO + CKESTR) & 0x88; |
| 1405 | strength_control |= 0x04; |
| 1406 | write8(RCOMP_MMIO + CKESTR, strength_control); |
| 1407 | write_8dwords(slew_2x, RCOMP_MMIO + 0xa0); |
| 1408 | write16(RCOMP_MMIO + 0x44, 0); |
| 1409 | |
| 1410 | // Set CKE strength for x4 SDRAM to 2x (?) |
| 1411 | strength_control = read8(RCOMP_MMIO + CKESTR) & 0x8F; |
| 1412 | strength_control |= 0x40; |
| 1413 | write8(RCOMP_MMIO + CKESTR, strength_control); |
| 1414 | write_8dwords(slew_2x, RCOMP_MMIO + 0xc0); |
| 1415 | write16(RCOMP_MMIO + 0x46, 0); |
| 1416 | |
| 1417 | // Set CK strength for x4 SDRAM to 1x (?) |
| 1418 | strength_control = read8(RCOMP_MMIO + CKSTR) & 0x88; |
| 1419 | strength_control |= 0x01; |
| 1420 | write8(RCOMP_MMIO + CKSTR, strength_control); |
| 1421 | write_8dwords(pull_updown_offset_table, RCOMP_MMIO + 0x180); |
| 1422 | write16(RCOMP_MMIO + 0x4c, 0); |
| 1423 | |
| 1424 | // Set CK strength for x4 SDRAM to 1x (?) |
| 1425 | strength_control = read8(RCOMP_MMIO + CKSTR) & 0x8F; |
| 1426 | strength_control |= 0x10; |
| 1427 | write8(RCOMP_MMIO + CKSTR, strength_control); |
| 1428 | write_8dwords(pull_updown_offset_table, RCOMP_MMIO + 0x1a0); |
| 1429 | write16(RCOMP_MMIO + 0x4e, 0); |
| 1430 | |
| 1431 | dword = read32(RCOMP_MMIO + 0x400); |
| 1432 | dword &= 0x7f7fffff; |
| 1433 | write32(RCOMP_MMIO + 0x400, dword); |
| 1434 | |
| 1435 | dword = read32(RCOMP_MMIO + 0x408); |
| 1436 | dword &= 0x7f7fffff; |
| 1437 | write32(RCOMP_MMIO + 0x408, dword); |
| 1438 | } |
| 1439 | |
| 1440 | static void ram_set_rcomp_regs(void) |
| 1441 | { |
| 1442 | /* Set the RCOMP MMIO base address */ |
| 1443 | mchtest_control(RCOMP_BAR_ENABLE); |
| 1444 | pci_write_config32(MCHDEV, SMRBASE, (uintptr_t)RCOMP_MMIO); |
| 1445 | |
| 1446 | /* Block RCOMP updates while we configure the registers */ |
| 1447 | rcomp_smr_control(RCOMP_HOLD); |
| 1448 | rcomp_copy_registers(); |
| 1449 | d060_control(D060_CMD_0); |
| 1450 | mchtest_control(MCHTST_CMD_0); |
| 1451 | |
| 1452 | uint8_t revision = pci_read_config8(MCHDEV, 0x08); |
| 1453 | if (revision >= 3) { |
| 1454 | rcomp_smr_control(RCOMP_SMR_00); |
| 1455 | rcomp_smr_control(RCOMP_SMR_01); |
| 1456 | } |
| 1457 | rcomp_smr_control(RCOMP_RELEASE); |
| 1458 | |
| 1459 | /* Wait 40 usec */ |
| 1460 | SLOW_DOWN_IO; |
| 1461 | |
| 1462 | /* Clear the RCOMP MMIO base address */ |
| 1463 | pci_write_config32(MCHDEV, SMRBASE, 0); |
| 1464 | mchtest_control(RCOMP_BAR_DISABLE); |
| 1465 | } |
| 1466 | |
| 1467 | /*----------------------------------------------------------------------------- |
| 1468 | Public interface: |
| 1469 | -----------------------------------------------------------------------------*/ |
| 1470 | |
| 1471 | /** |
| 1472 | * Go through the JEDEC initialization sequence for all DIMMs, then enable |
| 1473 | * refresh and initialize ECC and memory to zero. Upon exit, SDRAM is up |
| 1474 | * and running. |
| 1475 | * |
| 1476 | * @param ctrl PCI addresses of memory controller functions, and SMBus |
| 1477 | * addresses of DIMM slots on the mainboard. |
| 1478 | */ |
| 1479 | static void sdram_enable(const struct mem_controller *ctrl) |
| 1480 | { |
| 1481 | uint8_t dimm_mask = pci_read_config16(MCHDEV, SKPD); |
| 1482 | uint32_t dram_controller_mode; |
| 1483 | |
| 1484 | if (dimm_mask == 0) |
| 1485 | return; |
| 1486 | |
| 1487 | /* 1 & 2 Power up and start clocks */ |
| 1488 | RAM_DEBUG_MESSAGE("Ram Enable 1\n"); |
| 1489 | RAM_DEBUG_MESSAGE("Ram Enable 2\n"); |
| 1490 | |
| 1491 | /* A 200us delay is needed */ |
| 1492 | DO_DELAY; EXTRA_DELAY; |
| 1493 | |
| 1494 | /* 3. Apply NOP */ |
| 1495 | RAM_DEBUG_MESSAGE("Ram Enable 3\n"); |
| 1496 | do_ram_command(RAM_COMMAND_NOP, 0); |
| 1497 | |
| 1498 | /* 4 Precharge all */ |
| 1499 | RAM_DEBUG_MESSAGE("Ram Enable 4\n"); |
| 1500 | do_ram_command(RAM_COMMAND_PRECHARGE, 0); |
| 1501 | /* wait until the all banks idle state... */ |
| 1502 | |
| 1503 | /* 5. Issue EMRS to enable DLL */ |
| 1504 | RAM_DEBUG_MESSAGE("Ram Enable 5\n"); |
| 1505 | do_ram_command(RAM_COMMAND_EMRS, |
| 1506 | SDRAM_EXTMODE_DLL_ENABLE | |
| 1507 | SDRAM_EXTMODE_DRIVE_NORMAL); |
| 1508 | |
| 1509 | /* 6. Reset DLL */ |
| 1510 | RAM_DEBUG_MESSAGE("Ram Enable 6\n"); |
| 1511 | set_ram_mode(E7501_SDRAM_MODE | SDRAM_MODE_DLL_RESET); |
| 1512 | EXTRA_DELAY; |
| 1513 | /* Ensure a 200us delay between the DLL reset in step 6 and the final |
| 1514 | * mode register set in step 9. |
| 1515 | * Infineon needs this before any other command is sent to the ram. |
| 1516 | */ |
| 1517 | DO_DELAY; EXTRA_DELAY; |
| 1518 | |
| 1519 | /* 7 Precharge all */ |
| 1520 | RAM_DEBUG_MESSAGE("Ram Enable 7\n"); |
| 1521 | do_ram_command(RAM_COMMAND_PRECHARGE, 0); |
| 1522 | |
| 1523 | /* 8 Now we need 2 AUTO REFRESH / CBR cycles to be performed */ |
| 1524 | /* And for good luck 6 more CBRs */ |
| 1525 | RAM_DEBUG_MESSAGE("Ram Enable 8\n"); |
| 1526 | int i; |
| 1527 | for (i = 0; i < 8; i++) |
| 1528 | do_ram_command(RAM_COMMAND_CBR, 0); |
| 1529 | |
| 1530 | /* 9 mode register set */ |
| 1531 | RAM_DEBUG_MESSAGE("Ram Enable 9\n"); |
| 1532 | set_ram_mode(E7501_SDRAM_MODE | SDRAM_MODE_NORMAL); |
| 1533 | |
| 1534 | /* 10 DDR Receive FIFO RE-Sync */ |
| 1535 | RAM_DEBUG_MESSAGE("Ram Enable 10\n"); |
| 1536 | RAM_RESET_DDR_PTR(); |
| 1537 | EXTRA_DELAY; |
| 1538 | |
| 1539 | /* 11 normal operation */ |
| 1540 | RAM_DEBUG_MESSAGE("Ram Enable 11\n"); |
| 1541 | do_ram_command(RAM_COMMAND_NORMAL, 0); |
| 1542 | |
| 1543 | // Reconfigure the row boundaries and Top of Low Memory |
| 1544 | // to match the true size of the DIMMs |
| 1545 | configure_e7501_ram_addresses(ctrl, dimm_mask); |
| 1546 | |
| 1547 | /* Finally enable refresh */ |
| 1548 | dram_controller_mode = pci_read_config32(MCHDEV, DRC); |
| 1549 | dram_controller_mode |= (1 << 29); |
| 1550 | pci_write_config32(MCHDEV, DRC, dram_controller_mode); |
| 1551 | EXTRA_DELAY; |
| 1552 | } |
| 1553 | |
| 1554 | /** |
| 1555 | * @param ctrl PCI addresses of memory controller functions, and SMBus |
| 1556 | * addresses of DIMM slots on the mainboard. |
| 1557 | */ |
| 1558 | static void sdram_post_ecc(const struct mem_controller *ctrl) |
| 1559 | { |
| 1560 | /* Fast CS# Enable. */ |
| 1561 | uint32_t dram_controller_mode = pci_read_config32(MCHDEV, DRC); |
| 1562 | dram_controller_mode = pci_read_config32(MCHDEV, DRC); |
| 1563 | dram_controller_mode |= (1 << 17); |
| 1564 | pci_write_config32(MCHDEV, DRC, dram_controller_mode); |
| 1565 | } |
| 1566 | |
| 1567 | /** |
| 1568 | * Configure SDRAM controller parameters that depend on characteristics of the |
| 1569 | * DIMMs installed in the system. These characteristics are read from the |
| 1570 | * DIMMs via the standard Serial Presence Detect (SPD) interface. |
| 1571 | * |
| 1572 | * @param ctrl PCI addresses of memory controller functions, and SMBus |
| 1573 | * addresses of DIMM slots on the mainboard. |
| 1574 | */ |
| 1575 | static void sdram_set_spd_registers(const struct mem_controller *ctrl) |
| 1576 | { |
| 1577 | uint8_t dimm_mask; |
| 1578 | |
| 1579 | RAM_DEBUG_MESSAGE("Reading SPD data...\n"); |
| 1580 | |
| 1581 | dimm_mask = spd_get_supported_dimms(ctrl); |
| 1582 | |
| 1583 | if (dimm_mask == 0) { |
| 1584 | printk(BIOS_DEBUG, "No usable memory for this controller\n"); |
| 1585 | } else { |
| 1586 | enable_e7501_clocks(dimm_mask); |
| 1587 | |
| 1588 | RAM_DEBUG_MESSAGE("setting based on SPD data...\n"); |
| 1589 | |
| 1590 | configure_e7501_row_attributes(ctrl, dimm_mask); |
| 1591 | configure_e7501_dram_controller_mode(ctrl, dimm_mask); |
| 1592 | configure_e7501_cas_latency(ctrl, dimm_mask); |
| 1593 | RAM_RESET_DDR_PTR(); |
| 1594 | |
| 1595 | configure_e7501_dram_timing(ctrl, dimm_mask); |
| 1596 | DO_DELAY; |
| 1597 | RAM_DEBUG_MESSAGE("done\n"); |
| 1598 | } |
| 1599 | |
| 1600 | /* NOTE: configure_e7501_ram_addresses() is NOT called here. |
| 1601 | * We want to keep the default 64 MB/row mapping until sdram_enable() is called, |
| 1602 | * even though the default mapping is almost certainly incorrect. |
| 1603 | * The default mapping makes it easy to initialize all of the DIMMs |
| 1604 | * even if the total system memory is > 4 GB. |
| 1605 | * |
| 1606 | * Save the dimm_mask for when sdram_enable is called, so it can call |
| 1607 | * configure_e7501_ram_addresses() without having to regenerate the bitmask |
| 1608 | * of usable DIMMs. |
| 1609 | */ |
| 1610 | pci_write_config16(MCHDEV, SKPD, dimm_mask); |
| 1611 | } |
| 1612 | |
| 1613 | /** |
| 1614 | * Do basic RAM setup that does NOT depend on serial presence detect |
| 1615 | * information (i.e. independent of DIMM specifics). |
| 1616 | * |
| 1617 | * @param ctrl PCI addresses of memory controller functions, and SMBus |
| 1618 | * addresses of DIMM slots on the mainboard. |
| 1619 | */ |
| 1620 | static void sdram_set_registers(const struct mem_controller *ctrl) |
| 1621 | { |
| 1622 | uint32_t dword; |
| 1623 | uint16_t word; |
| 1624 | uint8_t byte; |
| 1625 | |
| 1626 | ram_set_rcomp_regs(); |
| 1627 | |
| 1628 | /* Enable 0:0.1, 0:2.1 */ |
| 1629 | word = pci_read_config16(MCHDEV, DVNP); |
| 1630 | word &= ~0x05; |
| 1631 | pci_write_config16(MCHDEV, DVNP, word); |
| 1632 | |
| 1633 | /* Disable high-memory remap (power-on defaults, really) */ |
| 1634 | pci_write_config16(MCHDEV, REMAPBASE, 0x03ff); |
| 1635 | pci_write_config16(MCHDEV, REMAPLIMIT, 0x0); |
| 1636 | |
| 1637 | /* Disable legacy MMIO (0xC0000-0xEFFFF is DRAM) */ |
| 1638 | int i; |
| 1639 | pci_write_config8(MCHDEV, PAM_0, 0x30); |
| 1640 | for (i = 1; i <= 6; i++) |
| 1641 | pci_write_config8(MCHDEV, PAM_0 + i, 0x33); |
| 1642 | |
| 1643 | /* Conservatively say each row has 64MB of ram, we will fix this up later |
| 1644 | * Initial TOLM 8 rows 64MB each (1<<3 * 1<<26) >> 16 = 1<<13 |
| 1645 | * |
| 1646 | * FIXME: Hard-coded limit to first four rows to prevent overlap! |
| 1647 | */ |
| 1648 | pci_write_config32(MCHDEV, DRB_ROW_0, 0x04030201); |
| 1649 | pci_write_config32(MCHDEV, DRB_ROW_4, 0x04040404); |
| 1650 | //pci_write_config32(MCHDEV, DRB_ROW_4, 0x08070605); |
| 1651 | pci_write_config16(MCHDEV, TOLM, (1<<13)); |
| 1652 | |
| 1653 | /* DIMM clocks off */ |
| 1654 | pci_write_config8(MCHDEV, CKDIS, 0xff); |
| 1655 | |
| 1656 | /* reset row attributes */ |
| 1657 | pci_write_config32(MCHDEV, DRA, 0x0); |
| 1658 | |
| 1659 | // The only things we need to set here are DRAM idle timer, Back-to-Back Read Turnaround, and |
| 1660 | // Back-to-Back Write-Read Turnaround. All others are configured based on SPD. |
| 1661 | dword = pci_read_config32(MCHDEV, DRT); |
| 1662 | dword &= 0xC7F8FFFF; |
| 1663 | dword |= (0x28<<24)|(0x03<<16); |
| 1664 | pci_write_config32(MCHDEV, DRT, dword); |
| 1665 | |
| 1666 | dword = pci_read_config32(MCHDEV, DRC); |
| 1667 | dword &= 0xffcef8f7; |
| 1668 | dword |= 0x00210008; |
| 1669 | pci_write_config32(MCHDEV, DRC, dword); |
| 1670 | |
| 1671 | /* Undocumented */ |
| 1672 | pci_write_config8(MCHDEV, 0x88, 0x80); |
| 1673 | |
| 1674 | /* Undocumented. Set much later in vendor BIOS. */ |
| 1675 | byte = pci_read_config8(MCHDEV, 0xd9); |
| 1676 | byte &= ~0x60; |
| 1677 | pci_write_config8(MCHDEV, 0xd9, byte); |
| 1678 | |
| 1679 | uint8_t revision = pci_read_config8(MCHDEV, 0x08); |
| 1680 | if (revision >= 3) |
| 1681 | d060_control(D060_CMD_1); |
| 1682 | } |
| 1683 | |
| 1684 | static int e7505_mch_is_ready(void) |
| 1685 | { |
| 1686 | uint32_t dword = pci_read_config32(MCHDEV, DRC); |
| 1687 | return !!(dword & DRC_DONE); |
| 1688 | } |
| 1689 | |
Kyösti Mälkki | 560c3f5 | 2022-01-18 04:25:48 +0200 | [diff] [blame] | 1690 | #define HOST_BRIDGE PCI_DEV(0, 0, 0) |
| 1691 | |
Kyösti Mälkki | 7b73e852 | 2022-11-08 04:43:41 +0000 | [diff] [blame] | 1692 | void sdram_initialize(void) |
| 1693 | { |
| 1694 | static const struct mem_controller memctrl[] = { |
| 1695 | { |
| 1696 | .d0 = PCI_DEV(0, 0, 0), |
| 1697 | .d0f1 = PCI_DEV(0, 0, 1), |
| 1698 | .channel0 = { 0x50, 0x52, 0, 0 }, |
| 1699 | .channel1 = { 0x51, 0x53, 0, 0 }, |
| 1700 | }, |
| 1701 | }; |
| 1702 | |
| 1703 | /* If this is a warm boot, some initialisation can be skipped */ |
| 1704 | if (!e7505_mch_is_ready()) { |
| 1705 | |
| 1706 | /* The real MCH initialisation. */ |
| 1707 | timestamp_add_now(TS_INITRAM_START); |
| 1708 | |
| 1709 | sdram_set_registers(memctrl); |
| 1710 | sdram_set_spd_registers(memctrl); |
| 1711 | sdram_enable(memctrl); |
| 1712 | |
| 1713 | /* Hook for post ECC scrub settings and debug. */ |
| 1714 | sdram_post_ecc(memctrl); |
| 1715 | |
| 1716 | timestamp_add_now(TS_INITRAM_END); |
| 1717 | } |
| 1718 | |
Kyösti Mälkki | 560c3f5 | 2022-01-18 04:25:48 +0200 | [diff] [blame] | 1719 | |
| 1720 | if (CONFIG(SMM_TSEG)) |
| 1721 | pci_write_config8(HOST_BRIDGE, ESMRAMC, TSEG_SZ_1M | T_EN); |
| 1722 | |
Kyösti Mälkki | 7b73e852 | 2022-11-08 04:43:41 +0000 | [diff] [blame] | 1723 | printk(BIOS_DEBUG, "SDRAM is up.\n"); |
| 1724 | } |