Jeremy Soller | fdaccd8 | 2021-10-27 15:45:41 -0600 | [diff] [blame] | 1 | chip soc/intel/cannonlake |
| 2 | register "common_soc_config" = "{ |
| 3 | // Touchpad I2C bus |
| 4 | .i2c[0] = { |
| 5 | .speed = I2C_SPEED_FAST, |
| 6 | .rise_time_ns = 80, |
| 7 | .fall_time_ns = 110, |
| 8 | }, |
| 9 | }" |
| 10 | |
| 11 | # CPU (soc/intel/cannonlake/cpu.c) |
| 12 | # Power limit |
| 13 | register "power_limits_config" = "{ |
| 14 | .tdp_pl1_override = 125, |
| 15 | .tdp_pl2_override = 160, |
| 16 | }" |
| 17 | |
| 18 | # Enable Enhanced Intel SpeedStep |
| 19 | register "eist_enable" = "1" |
| 20 | |
| 21 | # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) |
| 22 | register "enable_c6dram" = "1" |
| 23 | |
| 24 | # FSP Silicon (soc/intel/cannonlake/fsp_params.c) |
| 25 | # Serial I/O |
| 26 | register "SerialIoDevMode" = "{ |
| 27 | [PchSerialIoIndexI2C0] = PchSerialIoPci, // Touchpad I2C bus |
| 28 | [PchSerialIoIndexUART2] = PchSerialIoSkipInit, // Debug console |
| 29 | }" |
| 30 | |
| 31 | # Misc |
| 32 | register "AcousticNoiseMitigation" = "1" |
| 33 | |
| 34 | # Power |
| 35 | register "PchPmSlpS3MinAssert" = "3" # 50ms |
| 36 | register "PchPmSlpS4MinAssert" = "1" # 1s |
| 37 | register "PchPmSlpSusMinAssert" = "4" # 4s |
| 38 | register "PchPmSlpAMinAssert" = "4" # 2s |
| 39 | |
| 40 | # Thermal |
| 41 | register "tcc_offset" = "13" |
| 42 | |
| 43 | # PM Util (soc/intel/cannonlake/pmutil.c) |
| 44 | # GPE configuration |
| 45 | # Note that GPE events called out in ASL code rely on this |
| 46 | # route. i.e. If this route changes then the affected GPE |
| 47 | # offset bits also need to be changed. |
| 48 | register "gpe0_dw0" = "PMC_GPP_K" |
| 49 | register "gpe0_dw1" = "PMC_GPP_G" |
| 50 | register "gpe0_dw2" = "PMC_GPP_E" |
| 51 | |
| 52 | # Actual device tree |
Arthur Heymans | 69cd729 | 2022-11-07 13:52:11 +0100 | [diff] [blame^] | 53 | device cpu_cluster 0 on end |
Jeremy Soller | fdaccd8 | 2021-10-27 15:45:41 -0600 | [diff] [blame] | 54 | |
| 55 | device domain 0 on |
| 56 | subsystemid 0x1558 0x7714 inherit |
| 57 | device pci 00.0 on end # Host Bridge |
| 58 | device pci 01.0 on # GPU Port |
| 59 | # PCI Express Graphics #0 x16, Clock 7 (NVIDIA GPU) |
| 60 | register "PcieClkSrcUsage[7]" = "0x40" |
| 61 | register "PcieClkSrcClkReq[7]" = "7" |
| 62 | |
| 63 | device pci 00.0 on end # VGA controller |
| 64 | device pci 00.1 on end # Audio device |
| 65 | device pci 00.2 on end # USB xHCI Host controller |
| 66 | device pci 00.3 on end # USB Type-C UCSI controller |
| 67 | end |
| 68 | # TODO: is this enough to disable iGPU? |
| 69 | device pci 02.0 off end # Integrated Graphics Device |
| 70 | device pci 04.0 on end # SA Thermal device |
| 71 | device pci 12.0 on end # Thermal Subsystem |
| 72 | device pci 12.5 off end # UFS SCS |
| 73 | device pci 12.6 off end # GSPI #2 |
| 74 | device pci 13.0 off end # Integrated Sensor Hub |
| 75 | device pci 14.0 on # USB xHCI |
| 76 | # USB2 |
| 77 | register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3_2 |
| 78 | register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB 3_1 |
| 79 | register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB 3_4 |
| 80 | register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB 3_3 |
| 81 | register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Per-key RGB |
| 82 | register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB Type-C |
| 83 | register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # XFI |
| 84 | register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera |
| 85 | register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Light guide |
| 86 | register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint |
| 87 | register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth |
| 88 | # USB3 |
| 89 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3_2 |
| 90 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # ANX7440 |
| 91 | register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3_4 |
| 92 | register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3_3 |
| 93 | end |
| 94 | device pci 14.2 on end # Shared SRAM |
| 95 | device pci 14.3 on # CNVi wifi |
| 96 | chip drivers/wifi/generic |
| 97 | register "wake" = "PME_B0_EN_BIT" |
| 98 | device generic 0 on end |
| 99 | end |
| 100 | end |
| 101 | device pci 14.5 off end # SDCard |
| 102 | device pci 15.0 on # I2C #0 |
| 103 | chip drivers/i2c/hid |
Tim Crawford | fc9f882 | 2022-07-08 10:38:03 -0600 | [diff] [blame] | 104 | register "generic.hid" = ""SYNA1202"" |
Jeremy Soller | fdaccd8 | 2021-10-27 15:45:41 -0600 | [diff] [blame] | 105 | register "generic.desc" = ""Synaptics Touchpad"" |
Tim Crawford | aa8b1f8 | 2022-01-24 09:04:26 -0700 | [diff] [blame] | 106 | register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" |
Tim Crawford | 57fecef | 2022-07-24 17:09:16 -0600 | [diff] [blame] | 107 | register "generic.detect" = "1" |
Jeremy Soller | fdaccd8 | 2021-10-27 15:45:41 -0600 | [diff] [blame] | 108 | register "hid_desc_reg_offset" = "0x20" |
| 109 | device i2c 2c on end |
| 110 | end |
| 111 | end |
| 112 | device pci 15.1 off end # I2C #1 |
| 113 | device pci 15.2 off end # I2C #2 |
| 114 | device pci 15.3 off end # I2C #3 |
| 115 | device pci 16.0 on end # Management Engine Interface 1 |
| 116 | device pci 16.1 off end # Management Engine Interface 2 |
| 117 | device pci 16.2 off end # Management Engine IDE-R |
| 118 | device pci 16.3 off end # Management Engine KT Redirection |
| 119 | device pci 16.4 off end # Management Engine Interface 3 |
| 120 | device pci 16.5 off end # Management Engine Interface 4 |
| 121 | device pci 17.0 on # SATA |
| 122 | register "SataPortsEnable[1]" = "1" # SATA1A (SSD) |
| 123 | register "SataPortsEnable[3]" = "1" # SATA3 (M.2_SATA3) |
| 124 | register "SataPortsEnable[4]" = "1" # SATA4 (SSD2) |
| 125 | end |
| 126 | device pci 19.2 off end # UART #2 |
| 127 | device pci 1a.0 off end # eMMC |
| 128 | device pci 1b.0 on # PCI Express Port 17 |
| 129 | # PCI Express root port #17 x4, Clock 14 (SSD2) |
| 130 | register "PcieRpEnable[16]" = "1" |
| 131 | register "PcieRpLtrEnable[16]" = "1" |
| 132 | register "PcieClkSrcUsage[14]" = "16" |
| 133 | register "PcieClkSrcClkReq[14]" = "14" |
| 134 | end |
| 135 | device pci 1b.1 off end # PCI Express Port 18 |
| 136 | device pci 1b.2 off end # PCI Express Port 19 |
| 137 | device pci 1b.3 off end # PCI Express Port 20 |
| 138 | device pci 1b.4 on # PCI Express Port 21 |
| 139 | # PCI Express root port #21 x4, Clock 15 (SSD3) |
| 140 | register "PcieRpEnable[20]" = "1" |
| 141 | register "PcieRpLtrEnable[20]" = "1" |
| 142 | register "PcieClkSrcUsage[15]" = "20" |
| 143 | register "PcieClkSrcClkReq[15]" = "15" |
| 144 | end |
| 145 | device pci 1b.5 off end # PCI Express Port 22 |
| 146 | device pci 1b.6 off end # PCI Express Port 23 |
| 147 | device pci 1b.7 off end # PCI Express Port 24 |
| 148 | device pci 1c.0 on # PCI Express Port 1 |
| 149 | # PCI Express root port #1 x4, Clock 6 (Thunderbolt) |
| 150 | register "PcieRpEnable[0]" = "1" |
| 151 | register "PcieRpLtrEnable[0]" = "1" |
| 152 | register "PcieRpHotPlug[0]" = "1" |
| 153 | register "PcieClkSrcUsage[6]" = "PCIE_CLK_RP0" # 0 is converted to PCIE_CLK_NOTUSED |
| 154 | register "PcieClkSrcClkReq[6]" = "6" |
| 155 | end |
| 156 | device pci 1c.1 off end # PCI Express Port 2 |
| 157 | device pci 1c.2 off end # PCI Express Port 3 |
| 158 | device pci 1c.3 off end # PCI Express Port 4 |
| 159 | device pci 1c.4 on # PCI Express Port 5 |
| 160 | # PCI Express root port #5 x4, Clock 10 (USB 3.2) |
| 161 | register "PcieRpEnable[4]" = "1" |
| 162 | register "PcieRpLtrEnable[4]" = "1" |
| 163 | register "PcieClkSrcUsage[10]" = "4" |
| 164 | register "PcieClkSrcClkReq[10]" = "10" |
| 165 | end |
| 166 | device pci 1c.5 off end # PCI Express Port 6 |
| 167 | device pci 1c.6 off end # PCI Express Port 7 |
| 168 | device pci 1c.7 off end # PCI Express Port 8 |
| 169 | device pci 1d.0 on # PCI Express Port 9 |
| 170 | # PCI Express root port #9 x4, Clock 8 (SSD) |
| 171 | register "PcieRpEnable[8]" = "1" |
| 172 | register "PcieRpLtrEnable[8]" = "1" |
| 173 | register "PcieClkSrcUsage[8]" = "8" |
| 174 | register "PcieClkSrcClkReq[8]" = "8" |
| 175 | end |
| 176 | device pci 1d.1 off end # PCI Express Port 10 |
| 177 | device pci 1d.2 off end # PCI Express Port 11 |
| 178 | device pci 1d.3 off end # PCI Express Port 12 |
| 179 | device pci 1d.4 on # PCI Express Port 13 |
| 180 | # PCI Express root port #13 x1, Clock 0 (WLAN) |
| 181 | register "PcieRpEnable[12]" = "1" |
| 182 | register "PcieRpLtrEnable[12]" = "1" |
| 183 | register "PcieClkSrcUsage[0]" = "12" |
| 184 | register "PcieClkSrcClkReq[0]" = "0" |
| 185 | end |
| 186 | device pci 1d.5 on # PCI Express Port 14 |
| 187 | # PCI Express root port #14 x1, Clock 1 (GLAN) |
| 188 | register "PcieRpEnable[13]" = "1" |
| 189 | register "PcieRpLtrEnable[13]" = "1" |
| 190 | register "PcieClkSrcUsage[1]" = "13" |
| 191 | register "PcieClkSrcClkReq[1]" = "1" |
| 192 | end |
| 193 | device pci 1d.6 on # PCI Express Port 15 |
| 194 | # PCI Express root port #15 x1, Clock 4 (Card Reader) |
| 195 | register "PcieRpEnable[14]" = "1" |
| 196 | register "PcieRpLtrEnable[14]" = "1" |
| 197 | register "PcieClkSrcUsage[4]" = "14" |
| 198 | register "PcieClkSrcClkReq[4]" = "4" |
| 199 | end |
| 200 | device pci 1d.7 off end # PCI Express Port 16 |
| 201 | device pci 1e.0 off end # UART #0 |
| 202 | device pci 1e.1 off end # UART #1 |
| 203 | device pci 1e.2 off end # GSPI #0 |
| 204 | device pci 1e.3 off end # GSPI #1 |
| 205 | device pci 1f.0 on # LPC Interface |
| 206 | register "gen1_dec" = "0x00040069" |
| 207 | register "gen2_dec" = "0x00fc0e01" |
| 208 | register "gen3_dec" = "0x00fc0f01" |
| 209 | chip drivers/pc80/tpm |
| 210 | device pnp 0c31.0 on end |
| 211 | end |
| 212 | end |
| 213 | device pci 1f.1 off end # P2SB |
| 214 | device pci 1f.2 hidden end # Power Management Controller |
| 215 | device pci 1f.3 on # Intel HDA |
| 216 | register "PchHdaAudioLinkHda" = "1" |
| 217 | end |
| 218 | device pci 1f.4 on end # SMBus |
| 219 | device pci 1f.5 on end # PCH SPI |
| 220 | device pci 1f.6 off end # GbE |
| 221 | end |
| 222 | end |