blob: 9a71015ae71fa246fa4156a4da7bfb071109830c [file] [log] [blame]
Sean Rhodese96ade62021-10-18 21:07:20 +01001chip soc/intel/cannonlake
2 # CPU
3 # Enable Enhanced Intel SpeedStep
4 register "eist_enable" = "1"
5
6 # Graphics
7 # IGD Displays
8 register "panel_cfg" = "{
9 .up_delay_ms = 0, // T3
10 .backlight_on_delay_ms = 0, // T7
11 .backlight_off_delay_ms = 0, // T9
12 .down_delay_ms = 0, // T10
13 .cycle_delay_ms = 500, // T12
14 .backlight_pwm_hz = 200, // PWM
15 }"
16
17 # FSP Memory
18 register "enable_c6dram" = "1"
19 register "SaGv" = "SaGv_Enabled"
20
21 # FSP Silicon
22 # Serial I/O
23 register "SerialIoDevMode" = "{
24 [PchSerialIoIndexI2C0] = PchSerialIoPci,
25 [PchSerialIoIndexI2C4] = PchSerialIoSkipInit,
26 [PchSerialIoIndexUART2] = PchSerialIoSkipInit,
27 }"
28
29 # Power
30 register "PchPmSlpS3MinAssert" = "2" # 50ms
31 register "PchPmSlpS4MinAssert" = "3" # 1s
32 register "PchPmSlpSusMinAssert" = "3" # 500ms
33 register "PchPmSlpAMinAssert" = "3" # 2s
34
Sean Rhodese96ade62021-10-18 21:07:20 +010035 # PM Util
36 # GPE configuration
37 # Note that GPE events called out in ASL code rely on this
38 # route. i.e. If this route changes then the affected GPE
39 # offset bits also need to be changed.
40 # sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
41 register "gpe0_dw0" = "PMC_GPP_B"
42 register "gpe0_dw1" = "PMC_GPP_C"
43 register "gpe0_dw2" = "PMC_GPP_E"
44
45 # PCIe Clock
46 register "PcieClkSrcClkReq[0]" = "PCIE_CLK_NOTUSED"
47 register "PcieClkSrcClkReq[2]" = "PCIE_CLK_NOTUSED"
48 register "PcieClkSrcClkReq[3]" = "PCIE_CLK_NOTUSED"
49 register "PcieClkSrcClkReq[4]" = "PCIE_CLK_NOTUSED"
50 register "PcieClkSrcClkReq[5]" = "PCIE_CLK_NOTUSED"
51
52# Actual device tree.
Arthur Heymans69cd7292022-11-07 13:52:11 +010053 device cpu_cluster 0 on end
Sean Rhodese96ade62021-10-18 21:07:20 +010054
55 device domain 0 on
56 device pci 00.0 on end # Host Bridge
57 device pci 02.0 on end # Integrated Graphics Device
58 device pci 04.0 on # SA Thermal Device
59 register "Device4Enable" = "1"
60 end
61 device pci 12.0 off end # Thermal Subsystem
62 device pci 12.5 off end # UFS SCS
63 device pci 12.6 off end # GSPI #2
64 device pci 14.0 on # USB xHCI
Sean Rhodese96ade62021-10-18 21:07:20 +010065 # Motherboard USB Type C
66 register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"
Sean Rhodes840915b2022-05-26 20:46:35 +010067 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"
68
Sean Rhodese96ade62021-10-18 21:07:20 +010069 # Motherboard USB 3.0
70 register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"
Sean Rhodes840915b2022-05-26 20:46:35 +010071 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"
72
Sean Rhodese96ade62021-10-18 21:07:20 +010073 # Daughterboard SD Card
74 register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"
Sean Rhodes840915b2022-05-26 20:46:35 +010075
Sean Rhodese96ade62021-10-18 21:07:20 +010076 # Daughterboard USB 3.0
77 register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"
Sean Rhodes840915b2022-05-26 20:46:35 +010078 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"
79
Sean Rhodes2eb2dce2022-05-26 20:56:14 +010080 # Webcam
81 register "usb2_ports[CONFIG_CCD_PORT]" = "USB2_PORT_MID(OC_SKIP)"
Sean Rhodes840915b2022-05-26 20:46:35 +010082
Sean Rhodese96ade62021-10-18 21:07:20 +010083 # Internal Bluetooth
84 register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"
Sean Rhodese96ade62021-10-18 21:07:20 +010085 end
86 device pci 14.1 off end # USB xDCI (OTG)
Sean Rhodes558eafd2022-09-07 16:31:10 +010087 device pci 14.2 on end # SRAM
Sean Rhodese96ade62021-10-18 21:07:20 +010088 device pci 14.3 on # CNVi
89 chip drivers/wifi/generic
90 register "wake" = "GPE0_PME_B0"
91 device generic 0 on end
92 end
93 end
94 device pci 14.5 off end # SDCard
95 device pci 15.0 on # I2C0
96 chip drivers/i2c/hid
97 register "generic.hid" = ""STAR0001""
98 register "generic.desc" = ""Touchpad""
99 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)"
Matt DeVillier2cf52d82022-09-01 15:09:24 -0500100 register "generic.detect" = "1"
Sean Rhodese96ade62021-10-18 21:07:20 +0100101 register "hid_desc_reg_offset" = "0x20"
102 device i2c 2c on end
103 end
104 end
105 device pci 15.1 off end # I2C1
106 device pci 15.2 off end # I2C2
107 device pci 15.3 off end # I2C3
108 device pci 16.0 on end # Management Engine Interface 1
109 device pci 16.1 off end # Management Engine Interface 2
110 device pci 16.2 off end # Management Engine IDE-R
111 device pci 16.3 off end # Management Engine KT Redirection
112 device pci 16.4 off end # Management Engine Interface 3
113 device pci 16.5 off end # Management Engine Interface 4
114 device pci 17.0 on # SATA
115 register "SataSalpSupport" = "1"
116 # Port 1
117 register "SataPortsEnable[1]" = "1"
118 register "SataPortsDevSlp[1]" = "1"
119 end
120 device pci 19.0 on end # I2C4
121 device pci 19.1 off end # I2C5
122 device pci 19.2 on end # UART #2
123 device pci 1a.0 off end # eMMC
124 device pci 1c.0 off end # PCI Express Port 1
125 device pci 1c.1 off end # PCI Express Port 2
126 device pci 1c.2 off end # PCI Express Port 3
127 device pci 1c.3 off end # PCI Express Port 4
128 device pci 1c.4 off end # PCI Express Port 5
129 device pci 1c.5 off end # PCI Express Port 6
130 device pci 1c.6 off end # PCI Express Port 7
131 device pci 1c.7 off end # PCI Express Port 8
132 device pci 1d.0 on # PCI Express Port 9 (SSD x4)
133 register "PcieRpSlotImplemented[8]" = "1"
134 register "PcieRpEnable[8]" = "1"
135 register "PcieRpLtrEnable[8]" = "1"
136 register "PcieClkSrcUsage[1]" = "0x08"
137 register "PcieClkSrcClkReq[1]" = "1"
138 smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
139 end
140 device pci 1d.1 off end # PCI Express Port 10
141 device pci 1d.2 off end # PCI Express Port 11
142 device pci 1d.3 off end # PCI Express Port 12
143 device pci 1e.0 off end # UART #0
144 device pci 1e.1 off end # UART #1
145 device pci 1e.2 off end # GSPI #0
146 device pci 1e.3 off end # GSPI #1
147 device pci 1f.0 on # LPC Interface
148 register "gen1_dec" = "0x000c0681"
149 register "gen2_dec" = "0x000c1641"
150 register "gen3_dec" = "0x00fc0201"
151 register "gen4_dec" = "0x000c0081"
152
153 chip ec/starlabs/merlin
154 # Port pair 4Eh/4Fh
155 device pnp 4e.00 on end # IO Interface
156 device pnp 4e.01 off end # Com 1
157 device pnp 4e.02 off end # Com 2
158 device pnp 4e.04 off end # System Wake-Up
159 device pnp 4e.05 off end # PS/2 Mouse
160 device pnp 4e.06 on # PS/2 Keyboard
161 io 0x60 = 0x0060
162 io 0x62 = 0x0064
163 irq 0x70 = 1
164 end
165 device pnp 4e.0a off end # Consumer IR
166 device pnp 4e.0f off end # Shared Memory/Flash Interface
167 device pnp 4e.10 off end # RTC-like Timer
168 device pnp 4e.11 off end # Power Management Channel 1
169 device pnp 4e.12 off end # Power Management Channel 2
170 device pnp 4e.13 off end # Serial Peripheral Interface
171 device pnp 4e.14 off end # Platform EC Interface
172 device pnp 4e.17 off end # Power Management Channel 3
173 device pnp 4e.18 off end # Power Management Channel 4
174 device pnp 4e.19 off end # Power Management Channel 5
175 end
176 end
Sean Rhodes60fb9352022-09-07 16:29:54 +0100177 device pci 1f.1 on end # P2SB
Sean Rhodese96ade62021-10-18 21:07:20 +0100178 device pci 1f.2 hidden end # Power Management Controller
179 device pci 1f.3 on # Intel HDA
Sean Rhodese96ade62021-10-18 21:07:20 +0100180 register "PchHdaAudioLinkHda" = "1"
181 end
182 device pci 1f.4 on end # SMBus
183 device pci 1f.5 on end # PCH SPI
184 device pci 1f.6 off end # GbE
185 end
186 chip drivers/crb
187 device mmio 0xfed40000 on end
188 end
189end