| Frans Hendriks | ed52e3d | 2019-07-15 08:48:55 +0200 | [diff] [blame] | 1 | chip soc/intel/braswell |
| 2 | |
| 3 | ############################################################ |
| 4 | # Set the parameters for MemoryInit |
| 5 | ############################################################ |
| 6 | |
| Frans Hendriks | ed52e3d | 2019-07-15 08:48:55 +0200 | [diff] [blame] | 7 | register "PcdMrcInitSpdAddr1" = "0xa0" |
| 8 | register "PcdMrcInitSpdAddr2" = "0xa2" |
| Frans Hendriks | 8d98d80 | 2019-12-09 10:02:26 +0100 | [diff] [blame] | 9 | register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_32MB" |
| Frans Hendriks | ed52e3d | 2019-07-15 08:48:55 +0200 | [diff] [blame] | 10 | register "PcdDvfsEnable" = "0" |
| 11 | register "PcdCaMirrorEn" = "1" |
| 12 | |
| 13 | ############################################################ |
| 14 | # Set the parameters for SiliconInit |
| 15 | ############################################################ |
| 16 | |
| 17 | register "PcdSdcardMode" = "PCH_DISABLED" |
| 18 | register "PcdEnableHsuart0" = "0" |
| 19 | register "PcdEnableHsuart1" = "0" |
| 20 | register "PcdEnableAzalia" = "1" |
| 21 | register "PcdEnableXhci" = "1" |
| 22 | register "PcdEnableLpe" = "0" |
| 23 | register "PcdEnableDma0" = "0" |
| 24 | register "PcdEnableDma1" = "0" |
| 25 | register "PcdEnableI2C0" = "0" |
| 26 | register "PcdEnableI2C1" = "0" |
| 27 | register "PcdEnableI2C2" = "0" |
| 28 | register "PcdEnableI2C3" = "0" |
| 29 | register "PcdEnableI2C4" = "0" |
| 30 | register "PcdEnableI2C5" = "0" |
| 31 | register "PcdEnableI2C6" = "0" |
| 32 | register "PunitPwrConfigDisable" = "0" # Enable SVID |
| 33 | register "ChvSvidConfig" = "1" |
| 34 | register "PcdEmmcMode" = "PCH_PCI_MODE" |
| Frans Hendriks | ed52e3d | 2019-07-15 08:48:55 +0200 | [diff] [blame] | 35 | register "PcdEnableSata" = "1" |
| 36 | register "Usb2Port0PerPortPeTxiSet" = "7" |
| 37 | register "Usb2Port0PerPortTxiSet" = "5" |
| 38 | register "Usb2Port0IUsbTxEmphasisEn" = "2" |
| 39 | register "Usb2Port0PerPortTxPeHalf" = "1" |
| 40 | register "Usb2Port1PerPortPeTxiSet" = "7" |
| 41 | register "Usb2Port1PerPortTxiSet" = "3" |
| 42 | register "Usb2Port1IUsbTxEmphasisEn" = "2" |
| 43 | register "Usb2Port1PerPortTxPeHalf" = "1" |
| 44 | register "Usb2Port2PerPortPeTxiSet" = "7" |
| 45 | register "Usb2Port2PerPortTxiSet" = "3" |
| 46 | register "Usb2Port2IUsbTxEmphasisEn" = "2" |
| 47 | register "Usb2Port2PerPortTxPeHalf" = "1" |
| 48 | register "Usb2Port3PerPortPeTxiSet" = "7" |
| 49 | register "Usb2Port3PerPortTxiSet" = "3" |
| 50 | register "Usb2Port3IUsbTxEmphasisEn" = "2" |
| 51 | register "Usb2Port3PerPortTxPeHalf" = "1" |
| 52 | register "Usb2Port4PerPortPeTxiSet" = "7" |
| 53 | register "Usb2Port4PerPortTxiSet" = "3" |
| 54 | register "Usb2Port4IUsbTxEmphasisEn" = "2" |
| 55 | register "Usb2Port4PerPortTxPeHalf" = "1" |
| 56 | register "Usb3Lane0Ow2tapgen2deemph3p5" = "0x3a" |
| 57 | register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64" |
| 58 | register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64" |
| 59 | register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a" |
| Frans Hendriks | ed52e3d | 2019-07-15 08:48:55 +0200 | [diff] [blame] | 60 | register "PcdPchSsicEnable" = "1" |
| Frans Hendriks | ed52e3d | 2019-07-15 08:48:55 +0200 | [diff] [blame] | 61 | register "PMIC_I2CBus" = "0" |
| 62 | register "ISPEnable" = "0" # Disable IUNIT |
| 63 | register "ISPPciDevConfig" = "3" |
| 64 | register "PcdSdDetectChk" = "0" # Disable SD card detect |
| 65 | register "DptfDisable" = "1" |
| 66 | |
| 67 | # LPE audio codec settings |
| 68 | register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock |
| 69 | |
| 70 | # Enable devices in PCI mode |
| 71 | register "lpss_acpi_mode" = "0" |
| 72 | register "emmc_acpi_mode" = "0" |
| 73 | register "sd_acpi_mode" = "0" |
| 74 | register "lpe_acpi_mode" = "0" |
| 75 | |
| 76 | # Disable SLP_X stretching after SUS power well fail. |
| 77 | register "disable_slp_x_stretch_sus_fail" = "1" |
| 78 | |
| 79 | # Allow PCIe devices to wake system from suspend |
| 80 | register "pcie_wake_enable" = "1" |
| 81 | |
| Arthur Heymans | 69cd729 | 2022-11-07 13:52:11 +0100 | [diff] [blame^] | 82 | device cpu_cluster 0 on end |
| Frans Hendriks | ed52e3d | 2019-07-15 08:48:55 +0200 | [diff] [blame] | 83 | |
| 84 | device domain 0 on |
| 85 | device pci 00.0 on end # 8086 2280 - SoC router |
| 86 | device pci 02.0 on end # 8086 22B1 - GFX |
| 87 | device pci 0b.0 off end # 8086 22DC - PUNIT/DPTF |
| 88 | device pci 10.0 on end # 8086 2294 - MMC Port |
| 89 | device pci 12.0 on end # 8086 0F16 - SD Port |
| 90 | device pci 13.0 on end # 8086 22a3 - SATA Port |
| 91 | device pci 14.0 on end # 8086 22b5 - USB XHCI - Only 1 USB controller at a time |
| 92 | device pci 18.0 off end # 8086 22c0 - SIO - DMA |
| 93 | device pci 18.1 off end # 8086 22c1 - I2C Port 1 |
| 94 | device pci 18.2 off end # 8086 22c2 - I2C Port 2 |
| 95 | device pci 18.3 off end # 8086 22c3 - I2C Port 3 |
| 96 | device pci 18.4 off end # 8086 22c4 - I2C Port 4 |
| 97 | device pci 18.5 off end # 8086 22c5 - I2C Port 5 |
| 98 | device pci 18.6 off end # 8086 22c6 - I2C Port 6 |
| 99 | device pci 18.7 off end # 8086 22c7 - I2C Port 7 |
| 100 | device pci 1a.0 on end # 8086 2298 - Trusted Execution Engine |
| 101 | device pci 1b.0 on end # 8086 2284 - HD Audio |
| 102 | device pci 1c.0 on end # 8086 0000 - PCIe Root Port 1 |
| 103 | device pci 1c.1 on end # 8086 0000 - PCIe Root Port 2 |
| 104 | device pci 1c.2 on end # 8086 0000 - PCIe Root Port 3 |
| 105 | device pci 1c.3 on end # 8086 0000 - PCIe Root Port 4 |
| 106 | device pci 1e.0 off end # 8086 2286 - SIO - DMA |
| 107 | device pci 1e.3 off end # 8086 228a - HSUART 1 |
| 108 | device pci 1e.4 off end # 8086 228c - HSUART 2 |
| 109 | device pci 1f.0 on end # 8086 229c - LPC bridge |
| 110 | device pci 1f.3 on end # 8086 2292 - SMBus 0 |
| 111 | end |
| 112 | end |