Angel Pons | f5627e8 | 2020-04-05 15:46:52 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Lijian Zhao | ac87a98 | 2017-08-28 17:46:55 -0700 | [diff] [blame] | 2 | |
Subrata Banik | 0baad61 | 2017-11-23 13:58:34 +0530 | [diff] [blame] | 3 | #include <bootstate.h> |
Lijian Zhao | ac87a98 | 2017-08-28 17:46:55 -0700 | [diff] [blame] | 4 | #include <console/console.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 5 | #include <device/mmio.h> |
Lijian Zhao | ac87a98 | 2017-08-28 17:46:55 -0700 | [diff] [blame] | 6 | #include <device/device.h> |
Tim Wawrzynczak | 6d44437 | 2021-07-01 08:42:01 -0600 | [diff] [blame] | 7 | #include <intelblocks/acpi.h> |
Subrata Banik | 0baad61 | 2017-11-23 13:58:34 +0530 | [diff] [blame] | 8 | #include <intelblocks/pmc.h> |
Lijian Zhao | ac87a98 | 2017-08-28 17:46:55 -0700 | [diff] [blame] | 9 | #include <intelblocks/pmclib.h> |
| 10 | #include <intelblocks/rtc.h> |
Lijian Zhao | ac87a98 | 2017-08-28 17:46:55 -0700 | [diff] [blame] | 11 | #include <soc/pci_devs.h> |
| 12 | #include <soc/pm.h> |
Lijian Zhao | ac87a98 | 2017-08-28 17:46:55 -0700 | [diff] [blame] | 13 | |
Elyes HAOUAS | c338507 | 2019-03-21 15:38:06 +0100 | [diff] [blame] | 14 | #include "chip.h" |
| 15 | |
Krzysztof Sywula | 42a66fb | 2019-03-13 16:48:56 -0700 | [diff] [blame] | 16 | static void pm1_enable_pwrbtn_smi(void *unused) |
| 17 | { |
| 18 | /* |
| 19 | * Enable power button SMI only before jumping to payload. This ensures |
| 20 | * that: |
| 21 | * 1. Power button SMI is enabled only after coreboot is done. |
| 22 | * 2. On resume path, power button SMI is not enabled and thus avoids |
| 23 | * any shutdowns because of power button presses due to power button |
| 24 | * press in resume path. |
| 25 | */ |
| 26 | pmc_update_pm1_enable(PWRBTN_EN); |
| 27 | } |
| 28 | |
| 29 | BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, pm1_enable_pwrbtn_smi, NULL); |
| 30 | |
Lijian Zhao | ac87a98 | 2017-08-28 17:46:55 -0700 | [diff] [blame] | 31 | static void config_deep_sX(uint32_t offset, uint32_t mask, int sx, int enable) |
| 32 | { |
| 33 | uint32_t reg; |
| 34 | uint8_t *pmcbase = pmc_mmio_regs(); |
| 35 | |
| 36 | printk(BIOS_DEBUG, "%sabling Deep S%c\n", |
| 37 | enable ? "En" : "Dis", sx + '0'); |
| 38 | reg = read32(pmcbase + offset); |
| 39 | if (enable) |
| 40 | reg |= mask; |
| 41 | else |
| 42 | reg &= ~mask; |
| 43 | write32(pmcbase + offset, reg); |
| 44 | } |
| 45 | |
| 46 | static void config_deep_s5(int on_ac, int on_dc) |
| 47 | { |
| 48 | /* Treat S4 the same as S5. */ |
| 49 | config_deep_sX(S4_PWRGATE_POL, S4AC_GATE_SUS, 4, on_ac); |
| 50 | config_deep_sX(S4_PWRGATE_POL, S4DC_GATE_SUS, 4, on_dc); |
| 51 | config_deep_sX(S5_PWRGATE_POL, S5AC_GATE_SUS, 5, on_ac); |
| 52 | config_deep_sX(S5_PWRGATE_POL, S5DC_GATE_SUS, 5, on_dc); |
| 53 | } |
| 54 | |
| 55 | static void config_deep_s3(int on_ac, int on_dc) |
| 56 | { |
| 57 | config_deep_sX(S3_PWRGATE_POL, S3AC_GATE_SUS, 3, on_ac); |
| 58 | config_deep_sX(S3_PWRGATE_POL, S3DC_GATE_SUS, 3, on_dc); |
| 59 | } |
| 60 | |
| 61 | static void config_deep_sx(uint32_t deepsx_config) |
| 62 | { |
| 63 | uint32_t reg; |
| 64 | uint8_t *pmcbase = pmc_mmio_regs(); |
| 65 | |
| 66 | reg = read32(pmcbase + DSX_CFG); |
| 67 | reg &= ~DSX_CFG_MASK; |
| 68 | reg |= deepsx_config; |
| 69 | write32(pmcbase + DSX_CFG, reg); |
| 70 | } |
| 71 | |
Tim Wawrzynczak | bd5b4aa | 2021-07-01 08:41:48 -0600 | [diff] [blame] | 72 | static void soc_pmc_read_resources(struct device *dev) |
| 73 | { |
| 74 | struct resource *res; |
| 75 | |
| 76 | /* Add the fixed MMIO resource */ |
| 77 | mmio_resource(dev, 0, PCH_PWRM_BASE_ADDRESS / KiB, PCH_PWRM_BASE_SIZE / KiB); |
| 78 | |
| 79 | /* Add the fixed I/O resource */ |
| 80 | res = new_resource(dev, 1); |
| 81 | res->base = (resource_t)ACPI_BASE_ADDRESS; |
| 82 | res->size = (resource_t)ACPI_BASE_SIZE; |
| 83 | res->limit = res->base + res->size - 1; |
| 84 | res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 85 | } |
| 86 | |
Michael Niewöhner | 38bf496 | 2021-09-27 23:55:05 +0200 | [diff] [blame] | 87 | static void soc_pmc_enable(struct device *dev) |
Lijian Zhao | ac87a98 | 2017-08-28 17:46:55 -0700 | [diff] [blame] | 88 | { |
Kyösti Mälkki | d5f645c | 2019-09-28 00:20:27 +0300 | [diff] [blame] | 89 | const config_t *config = config_of_soc(); |
Lijian Zhao | ac87a98 | 2017-08-28 17:46:55 -0700 | [diff] [blame] | 90 | |
| 91 | rtc_init(); |
| 92 | |
Nico Huber | 733c28f | 2019-08-05 19:33:09 +0200 | [diff] [blame] | 93 | pmc_set_power_failure_state(true); |
| 94 | pmc_gpe_init(); |
Lijian Zhao | ac87a98 | 2017-08-28 17:46:55 -0700 | [diff] [blame] | 95 | |
Lijian Zhao | ac87a98 | 2017-08-28 17:46:55 -0700 | [diff] [blame] | 96 | config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc); |
| 97 | config_deep_s5(config->deep_s5_enable_ac, config->deep_s5_enable_dc); |
| 98 | config_deep_sx(config->deep_sx_config); |
| 99 | } |
| 100 | |
Michael Niewöhner | 38bf496 | 2021-09-27 23:55:05 +0200 | [diff] [blame] | 101 | static void soc_pmc_init(struct device *dev) |
Furquan Shaikh | ac8c60e | 2019-02-25 16:01:25 -0800 | [diff] [blame] | 102 | { |
| 103 | /* |
| 104 | * PMC initialization happens earlier for this SoC because FSP-Silicon |
| 105 | * init hides PMC from PCI bus. However, pmc_set_acpi_mode, which |
| 106 | * disables ACPI mode doesn't need to happen that early and can be |
Furquan Shaikh | 67a489f | 2019-02-27 00:59:06 -0800 | [diff] [blame] | 107 | * delayed till typical BS_DEV_INIT. This ensures that ACPI mode |
| 108 | * disabling happens the same way for all SoCs and hence the ordering of |
| 109 | * events is the same. |
Furquan Shaikh | ac8c60e | 2019-02-25 16:01:25 -0800 | [diff] [blame] | 110 | * |
| 111 | * This is important to ensure that the ordering does not break the |
| 112 | * assumptions of any other drivers (e.g. ChromeEC) which could be |
| 113 | * taking different actions based on disabling of ACPI (e.g. flushing of |
| 114 | * all EC hostevent bits). |
Furquan Shaikh | 67a489f | 2019-02-27 00:59:06 -0800 | [diff] [blame] | 115 | * |
Tim Wawrzynczak | bd5b4aa | 2021-07-01 08:41:48 -0600 | [diff] [blame] | 116 | * Because the device is set as `hidden` in the devicetree, enumeration |
| 117 | * is skipped, but the device callbacks are still called as if it were |
| 118 | * found. |
Furquan Shaikh | ac8c60e | 2019-02-25 16:01:25 -0800 | [diff] [blame] | 119 | */ |
| 120 | pmc_set_acpi_mode(); |
| 121 | } |
Furquan Shaikh | 67a489f | 2019-02-27 00:59:06 -0800 | [diff] [blame] | 122 | |
Tim Wawrzynczak | 6d44437 | 2021-07-01 08:42:01 -0600 | [diff] [blame] | 123 | static void pmc_fill_ssdt(const struct device *dev) |
| 124 | { |
| 125 | if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_PEP)) |
| 126 | generate_acpi_power_engine(); |
| 127 | } |
| 128 | |
Tim Wawrzynczak | bd5b4aa | 2021-07-01 08:41:48 -0600 | [diff] [blame] | 129 | struct device_operations pmc_ops = { |
| 130 | .read_resources = soc_pmc_read_resources, |
| 131 | .set_resources = noop_set_resources, |
Michael Niewöhner | 38bf496 | 2021-09-27 23:55:05 +0200 | [diff] [blame] | 132 | .init = soc_pmc_init, |
| 133 | .enable = soc_pmc_enable, |
Tim Wawrzynczak | 6d44437 | 2021-07-01 08:42:01 -0600 | [diff] [blame] | 134 | #if CONFIG(HAVE_ACPI_TABLES) |
| 135 | .acpi_fill_ssdt = pmc_fill_ssdt, |
| 136 | #endif |
Tim Wawrzynczak | bd5b4aa | 2021-07-01 08:41:48 -0600 | [diff] [blame] | 137 | .scan_bus = scan_static_bus, |
| 138 | }; |