Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2013 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <stdlib.h> |
| 21 | #include <string.h> |
| 22 | #include <stddef.h> |
| 23 | #include <delay.h> |
| 24 | #include <console/console.h> |
| 25 | #include <device/device.h> |
| 26 | #include <cbmem.h> |
| 27 | #include <arch/cache.h> |
| 28 | #include "fimd.h" |
| 29 | #include "dp-core.h" |
| 30 | #include "cpu.h" |
| 31 | #include "clk.h" |
Stefan Reinauer | 3a0d0d8 | 2013-06-20 16:13:19 -0700 | [diff] [blame] | 32 | #include "usb.h" |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 33 | #include "chip.h" |
| 34 | |
| 35 | #define RAM_BASE_KB (CONFIG_SYS_SDRAM_BASE >> 10) |
| 36 | #define RAM_SIZE_KB (CONFIG_DRAM_SIZE_MB << 10UL) |
| 37 | |
| 38 | static unsigned int cpu_id; |
| 39 | static unsigned int cpu_rev; |
| 40 | |
| 41 | static void set_cpu_id(void) |
| 42 | { |
| 43 | cpu_id = readl((void *)EXYNOS_PRO_ID); |
| 44 | cpu_id = (0xC000 | ((cpu_id & 0x00FFF000) >> 12)); |
| 45 | |
| 46 | /* |
| 47 | * 0xC200: EXYNOS4210 EVT0 |
| 48 | * 0xC210: EXYNOS4210 EVT1 |
| 49 | */ |
| 50 | if (cpu_id == 0xC200) { |
| 51 | cpu_id |= 0x10; |
| 52 | cpu_rev = 0; |
| 53 | } else if (cpu_id == 0xC210) { |
| 54 | cpu_rev = 1; |
| 55 | } |
| 56 | } |
| 57 | |
| 58 | /* we distinguish a display port device from a raw graphics device |
| 59 | * because there are dramatic differences in startup depending on |
| 60 | * graphics usage. To make startup fast and easier to understand and |
| 61 | * debug we explicitly name this common case. The alternate approach, |
| 62 | * involving lots of machine and callbacks, is hard to debug and |
| 63 | * verify. |
| 64 | */ |
| 65 | static void exynos_displayport_init(device_t dev) |
| 66 | { |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 67 | struct cpu_samsung_exynos5420_config *conf = dev->chip_info; |
| 68 | /* put these on the stack. If, at some point, we want to move |
| 69 | * this code to a pre-ram stage, it will be much easier. |
| 70 | */ |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 71 | struct exynos5_fimd_panel panel; |
| 72 | unsigned long int fb_size; |
| 73 | u32 lcdbase; |
| 74 | |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 75 | memset(&panel, 0, sizeof(panel)); |
| 76 | |
| 77 | panel.is_dp = 1; /* Display I/F is eDP */ |
| 78 | /* while it is true that we did a memset to zero, |
| 79 | * we leave some 'set to zero' entries here to make |
| 80 | * it clear what's going on. Graphics is confusing. |
| 81 | */ |
| 82 | panel.is_mipi = 0; |
| 83 | panel.fixvclk = 0; |
| 84 | panel.ivclk = 0; |
| 85 | panel.clkval_f = conf->clkval_f; |
| 86 | panel.upper_margin = conf->upper_margin; |
| 87 | panel.lower_margin = conf->lower_margin; |
| 88 | panel.vsync = conf->vsync; |
| 89 | panel.left_margin = conf->left_margin; |
| 90 | panel.right_margin = conf->right_margin; |
| 91 | panel.hsync = conf->hsync; |
| 92 | panel.xres = conf->xres; |
| 93 | panel.yres = conf->yres; |
| 94 | |
Stefan Reinauer | f175191 | 2013-05-20 15:17:44 -0700 | [diff] [blame] | 95 | /* The size is a magic number from hardware. */ |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 96 | fb_size = conf->xres * conf->yres * (conf->bpp / 8); |
Stefan Reinauer | f175191 | 2013-05-20 15:17:44 -0700 | [diff] [blame] | 97 | lcdbase = (uintptr_t)cbmem_add(CBMEM_ID_CONSOLE, fb_size); |
| 98 | printk(BIOS_SPEW, "LCD framebuffer base is %p\n", (void *)(lcdbase)); |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 99 | |
Stefan Reinauer | 2d81125 | 2013-05-20 15:24:13 -0700 | [diff] [blame] | 100 | memset((void *)lcdbase, 0, fb_size); /* clear the framebuffer */ |
| 101 | |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 102 | /* |
| 103 | * We need to clean and invalidate the framebuffer region and disable |
| 104 | * caching as well. We assume that our dcache <--> memory address |
| 105 | * space is identity-mapped in 1MB chunks, so align accordingly. |
| 106 | * |
| 107 | * Note: We may want to do something clever to ensure the framebuffer |
| 108 | * region is aligned such that we don't change dcache policy for other |
| 109 | * stuff inadvertantly. |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 110 | */ |
| 111 | uint32_t lower = ALIGN_DOWN(lcdbase, MiB); |
Stefan Reinauer | f175191 | 2013-05-20 15:17:44 -0700 | [diff] [blame] | 112 | uint32_t upper = ALIGN_UP(lcdbase + fb_size, MiB); |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 113 | dcache_clean_invalidate_by_mva(lower, upper - lower); |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 114 | mmu_config_range(lower/MiB, (upper - lower)/MiB, DCACHE_OFF); |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 115 | |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 116 | mmio_resource(dev, 1, lcdbase/KiB, (fb_size + KiB - 1)/KiB); |
| 117 | printk(BIOS_DEBUG, |
| 118 | "Initializing Exynos VGA, base %p\n", (void *)lcdbase); |
Allen Martin | 681d17e | 2013-09-26 11:13:01 -0700 | [diff] [blame^] | 119 | lcd_ctrl_init(fb_size, &panel, (void *)lcdbase); |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 120 | } |
| 121 | |
Stefan Reinauer | 3a0d0d8 | 2013-06-20 16:13:19 -0700 | [diff] [blame] | 122 | static void cpu_enable(device_t dev) |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 123 | { |
| 124 | exynos_displayport_init(dev); |
Stefan Reinauer | 3a0d0d8 | 2013-06-20 16:13:19 -0700 | [diff] [blame] | 125 | |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 126 | ram_resource(dev, 0, RAM_BASE_KB, RAM_SIZE_KB); |
| 127 | |
| 128 | set_cpu_id(); |
| 129 | |
Stefan Reinauer | 3a0d0d8 | 2013-06-20 16:13:19 -0700 | [diff] [blame] | 130 | } |
| 131 | |
| 132 | static void cpu_init(device_t dev) |
| 133 | { |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 134 | printk(BIOS_INFO, "CPU: S5P%X @ %ldMHz\n", |
| 135 | cpu_id, get_arm_clk() / (1024*1024)); |
Stefan Reinauer | 3a0d0d8 | 2013-06-20 16:13:19 -0700 | [diff] [blame] | 136 | |
| 137 | usb_init(dev); |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 138 | } |
| 139 | |
| 140 | static void cpu_noop(device_t dev) |
| 141 | { |
| 142 | } |
| 143 | |
| 144 | static struct device_operations cpu_ops = { |
| 145 | .read_resources = cpu_noop, |
| 146 | .set_resources = cpu_noop, |
Stefan Reinauer | 3a0d0d8 | 2013-06-20 16:13:19 -0700 | [diff] [blame] | 147 | .enable_resources = cpu_enable, |
| 148 | .init = cpu_init, |
Gabe Black | 607c0b6 | 2013-05-16 05:45:57 -0700 | [diff] [blame] | 149 | .scan_bus = 0, |
| 150 | }; |
| 151 | |
| 152 | static void enable_exynos5420_dev(device_t dev) |
| 153 | { |
| 154 | dev->ops = &cpu_ops; |
| 155 | } |
| 156 | |
| 157 | struct chip_operations cpu_samsung_exynos5420_ops = { |
| 158 | CHIP_NAME("CPU Samsung Exynos 5420") |
| 159 | .enable_dev = enable_exynos5420_dev, |
| 160 | }; |
| 161 | |
| 162 | void exynos5420_config_l2_cache(void) |
| 163 | { |
| 164 | uint32_t val; |
| 165 | |
| 166 | /* |
| 167 | * Bit 9 - L2 tag RAM setup (1 cycle) |
| 168 | * Bits 8:6 - L2 tag RAM latency (3 cycles) |
| 169 | * Bit 5 - L2 data RAM setup (1 cycle) |
| 170 | * Bits 2:0 - L2 data RAM latency (3 cycles) |
| 171 | */ |
| 172 | val = (1 << 9) | (0x2 << 6) | (1 << 5) | (0x2); |
| 173 | write_l2ctlr(val); |
| 174 | } |