| Stefan Reinauer | 67fed69 | 2009-11-05 12:38:34 +0000 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2009 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #ifndef PC80_I8254_H |
| 21 | #define PC80_I8254_H |
| 22 | |
| 23 | /* Ports for the 8254 timer chip */ |
| 24 | #define TIMER0_PORT 0x40 |
| 25 | #define TIMER1_PORT 0x41 |
| 26 | #define TIMER2_PORT 0x42 |
| 27 | #define TIMER_MODE_PORT 0x43 |
| 28 | |
| 29 | /* Meaning of the mode bits */ |
| 30 | #define TIMER0_SEL 0x00 |
| 31 | #define TIMER1_SEL 0x40 |
| 32 | #define TIMER2_SEL 0x80 |
| 33 | #define READBACK_SEL 0xC0 |
| 34 | |
| 35 | #define LATCH_COUNT 0x00 |
| 36 | #define LOBYTE_ACCESS 0x10 |
| 37 | #define HIBYTE_ACCESS 0x20 |
| 38 | #define WORD_ACCESS 0x30 |
| 39 | |
| 40 | #define MODE0 0x00 |
| 41 | #define MODE1 0x02 |
| 42 | #define MODE2 0x04 |
| 43 | #define MODE3 0x06 |
| 44 | #define MODE4 0x08 |
| 45 | #define MODE5 0x0A |
| 46 | |
| 47 | #define BINARY_COUNT 0x00 |
| 48 | #define BCD_COUNT 0x01 |
| 49 | |
| 50 | /* Timers tick over at this rate */ |
| 51 | #define TICKS_PER_MS 1193 |
| 52 | |
| 53 | /* Parallel Peripheral Controller Port B */ |
| 54 | #define PPC_PORTB 0x61 |
| 55 | |
| 56 | /* Meaning of the port bits */ |
| 57 | #define PPCB_T2OUT 0x20 /* Bit 5 */ |
| 58 | #define PPCB_SPKR 0x02 /* Bit 1 */ |
| 59 | #define PPCB_T2GATE 0x01 /* Bit 0 */ |
| 60 | |
| 61 | #endif |