Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 2 | |
| 3 | #include <types.h> |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 4 | #include <console/console.h> |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 5 | #include <cpu/x86/smm.h> |
| 6 | #include <device/pci_def.h> |
Arthur Heymans | aade90e | 2018-01-25 00:33:45 +0100 | [diff] [blame] | 7 | #include <southbridge/intel/common/pmutil.h> |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 8 | #include "i82801ix.h" |
| 9 | |
Kyösti Mälkki | 661ad46 | 2020-12-29 06:26:21 +0200 | [diff] [blame] | 10 | #include <soc/nvs.h> |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 11 | |
Kyösti Mälkki | 894f6f8 | 2022-01-29 14:05:58 +0200 | [diff] [blame] | 12 | #if CONFIG(SMM_LEGACY_ASEG) |
Kyösti Mälkki | 239abaf | 2020-06-28 12:12:01 +0300 | [diff] [blame] | 13 | /* For qemu/x86-q35 to build properly. */ |
| 14 | struct global_nvs *gnvs; |
| 15 | #endif |
| 16 | |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 17 | int southbridge_io_trap_handler(int smif) |
| 18 | { |
| 19 | switch (smif) { |
| 20 | case 0x32: |
| 21 | printk(BIOS_DEBUG, "OS Init\n"); |
| 22 | /* gnvs->smif: |
| 23 | * On success, the IO Trap Handler returns 0 |
| 24 | * On failure, the IO Trap Handler returns a value != 0 |
| 25 | */ |
| 26 | gnvs->smif = 0; |
| 27 | return 1; /* IO trap handled */ |
| 28 | } |
| 29 | |
| 30 | /* Not handled */ |
| 31 | return 0; |
| 32 | } |
| 33 | |
Arthur Heymans | aade90e | 2018-01-25 00:33:45 +0100 | [diff] [blame] | 34 | void southbridge_smi_monitor(void) |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 35 | { |
| 36 | #define IOTRAP(x) (trap_sts & (1 << x)) |
| 37 | u32 trap_sts, trap_cycle; |
| 38 | u32 data, mask = 0; |
| 39 | int i; |
| 40 | |
| 41 | trap_sts = RCBA32(0x1e00); // TRSR - Trap Status Register |
| 42 | RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR |
| 43 | |
| 44 | trap_cycle = RCBA32(0x1e10); |
| 45 | for (i=16; i<20; i++) { |
| 46 | if (trap_cycle & (1 << i)) |
| 47 | mask |= (0xff << ((i - 16) << 3)); |
| 48 | } |
| 49 | |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 50 | /* IOTRAP(3) SMI function call */ |
| 51 | if (IOTRAP(3)) { |
| 52 | if (gnvs && gnvs->smif) |
| 53 | io_trap_handler(gnvs->smif); // call function smif |
| 54 | return; |
| 55 | } |
| 56 | |
| 57 | /* IOTRAP(2) currently unused |
| 58 | * IOTRAP(1) currently unused */ |
| 59 | |
| 60 | /* IOTRAP(0) SMIC */ |
| 61 | if (IOTRAP(0)) { |
| 62 | if (!(trap_cycle & (1 << 24))) { // It's a write |
| 63 | printk(BIOS_DEBUG, "SMI1 command\n"); |
| 64 | data = RCBA32(0x1e18); |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 65 | } |
| 66 | // Fall through to debug |
| 67 | } |
| 68 | |
| 69 | printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); |
Elyes HAOUAS | 70d79a4 | 2016-08-21 18:36:06 +0200 | [diff] [blame] | 70 | for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 71 | printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); |
| 72 | printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); |
| 73 | printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); |
| 74 | |
| 75 | if (!(trap_cycle & (1 << 24))) { |
| 76 | /* Write Cycle */ |
| 77 | data = RCBA32(0x1e18); |
| 78 | printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", data); |
| 79 | } |
| 80 | #undef IOTRAP |
| 81 | } |
| 82 | |
Arthur Heymans | aade90e | 2018-01-25 00:33:45 +0100 | [diff] [blame] | 83 | void southbridge_finalize_all(void) |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 84 | { |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 85 | } |