Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 3 | #include <amdblocks/acpi.h> |
| 4 | #include <amdblocks/acpimmio.h> |
| 5 | #include <amdblocks/amd_pci_util.h> |
| 6 | #include <amdblocks/gpio.h> |
Robert Zieba | b3b27f7 | 2022-10-03 14:50:55 -0600 | [diff] [blame] | 7 | #include <amdblocks/pci_clk_req.h> |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 8 | #include <amdblocks/smi.h> |
| 9 | #include <assert.h> |
| 10 | #include <bootstate.h> |
| 11 | #include <cpu/x86/smm.h> |
| 12 | #include <amdblocks/i2c.h> |
| 13 | #include <soc/amd_pci_int_defs.h> |
| 14 | #include <soc/iomap.h> |
| 15 | #include <soc/i2c.h> |
| 16 | #include <soc/smi.h> |
| 17 | #include <soc/southbridge.h> |
| 18 | #include "chip.h" |
| 19 | |
| 20 | /* |
| 21 | * Table of APIC register index and associated IRQ name. Using IDX_XXX_NAME |
| 22 | * provides a visible association with the index, therefore helping |
| 23 | * maintainability of table. If a new index/name is defined in |
| 24 | * amd_pci_int_defs.h, just add the pair at the end of this table. |
| 25 | * Order is not important. |
| 26 | */ |
Elyes Haouas | 2476942 | 2023-01-12 06:21:42 +0100 | [diff] [blame] | 27 | static const struct irq_idx_name irq_association[] = { |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 28 | { PIRQ_A, "INTA#" }, |
| 29 | { PIRQ_B, "INTB#" }, |
| 30 | { PIRQ_C, "INTC#" }, |
| 31 | { PIRQ_D, "INTD#" }, |
| 32 | { PIRQ_E, "INTE#" }, |
| 33 | { PIRQ_F, "INTF#/GENINT2" }, |
| 34 | { PIRQ_G, "INTG#" }, |
| 35 | { PIRQ_H, "INTH#" }, |
| 36 | { PIRQ_MISC, "Misc" }, |
| 37 | { PIRQ_MISC0, "Misc0" }, |
| 38 | { PIRQ_HPET_L, "HPET_L" }, |
| 39 | { PIRQ_HPET_H, "HPET_H" }, |
| 40 | { PIRQ_SIRQA, "Ser IRQ INTA" }, |
| 41 | { PIRQ_SIRQB, "Ser IRQ INTB" }, |
| 42 | { PIRQ_SIRQC, "Ser IRQ INTC" }, |
| 43 | { PIRQ_SIRQD, "Ser IRQ INTD" }, |
| 44 | { PIRQ_SCI, "SCI" }, |
| 45 | { PIRQ_SMBUS, "SMBUS" }, |
| 46 | { PIRQ_ASF, "ASF" }, |
| 47 | { PIRQ_PMON, "PerMon" }, |
| 48 | { PIRQ_SD, "SD" }, |
| 49 | { PIRQ_SDIO, "SDIO" }, |
| 50 | { PIRQ_CIR, "CIR" }, |
| 51 | { PIRQ_GPIOA, "GPIOa" }, |
| 52 | { PIRQ_GPIOB, "GPIOb" }, |
| 53 | { PIRQ_GPIOC, "GPIOc" }, |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 54 | { PIRQ_EMMC, "eMMC" }, |
| 55 | { PIRQ_GPP0, "GPP0" }, |
| 56 | { PIRQ_GPP1, "GPP1" }, |
| 57 | { PIRQ_GPP2, "GPP2" }, |
| 58 | { PIRQ_GPP3, "GPP3" }, |
| 59 | { PIRQ_GPIO, "GPIO" }, |
| 60 | { PIRQ_I2C0, "I2C0" }, |
| 61 | { PIRQ_I2C1, "I2C1" }, |
| 62 | { PIRQ_I2C2, "I2C2" }, |
| 63 | { PIRQ_I2C3, "I2C3" }, |
| 64 | { PIRQ_UART0, "UART0" }, |
| 65 | { PIRQ_UART1, "UART1" }, |
| 66 | { PIRQ_I2C4, "I2C4" }, |
Felix Held | 2f478b8 | 2022-01-11 17:05:11 +0100 | [diff] [blame] | 67 | { PIRQ_UART4, "UART4" }, |
| 68 | { PIRQ_UART2, "UART2" }, |
| 69 | { PIRQ_UART3, "UART3" }, |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 70 | }; |
| 71 | |
| 72 | const struct irq_idx_name *sb_get_apic_reg_association(size_t *size) |
| 73 | { |
| 74 | *size = ARRAY_SIZE(irq_association); |
| 75 | return irq_association; |
| 76 | } |
| 77 | |
| 78 | static void fch_clk_output_48Mhz(void) |
| 79 | { |
| 80 | uint32_t ctrl = misc_read32(MISC_CLK_CNTL0); |
| 81 | /* Enable BP_X48M0 Clock Output */ |
| 82 | ctrl |= BP_X48M0_OUTPUT_EN; |
| 83 | /* Disable clock output in S0i3 */ |
| 84 | ctrl |= BP_X48M0_S0I3_DIS; |
| 85 | misc_write32(MISC_CLK_CNTL0, ctrl); |
| 86 | } |
| 87 | |
| 88 | static void fch_init_acpi_ports(void) |
| 89 | { |
| 90 | u32 reg; |
| 91 | |
| 92 | /* We use some of these ports in SMM regardless of whether or not |
| 93 | * ACPI tables are generated. Enable these ports indiscriminately. |
| 94 | */ |
| 95 | |
| 96 | pm_write16(PM_EVT_BLK, ACPI_PM_EVT_BLK); |
| 97 | pm_write16(PM1_CNT_BLK, ACPI_PM1_CNT_BLK); |
| 98 | pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK); |
| 99 | pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK); |
| 100 | |
| 101 | if (CONFIG(HAVE_SMI_HANDLER)) { |
| 102 | /* APMC - SMI Command Port */ |
| 103 | pm_write16(PM_ACPI_SMI_CMD, APM_CNT); |
| 104 | configure_smi(SMITYPE_SMI_CMD_PORT, SMI_MODE_SMI); |
| 105 | |
| 106 | /* SMI on SlpTyp requires sending SMI before completion |
| 107 | response of the I/O write. */ |
| 108 | reg = pm_read32(PM_PCI_CTRL); |
| 109 | reg |= FORCE_SLPSTATE_RETRY; |
| 110 | pm_write32(PM_PCI_CTRL, reg); |
| 111 | |
| 112 | /* Disable SlpTyp feature */ |
| 113 | reg = pm_read8(PM_RST_CTRL1); |
| 114 | reg &= ~SLPTYPE_CONTROL_EN; |
| 115 | pm_write8(PM_RST_CTRL1, reg); |
| 116 | |
| 117 | configure_smi(SMITYPE_SLP_TYP, SMI_MODE_SMI); |
| 118 | } else { |
| 119 | pm_write16(PM_ACPI_SMI_CMD, 0); |
| 120 | } |
| 121 | |
| 122 | /* Decode ACPI registers and enable standard features */ |
| 123 | pm_write8(PM_ACPI_CONF, PM_ACPI_DECODE_STD | |
| 124 | PM_ACPI_GLOBAL_EN | |
| 125 | PM_ACPI_RTC_EN_EN | |
| 126 | PM_ACPI_TIMER_EN_EN); |
| 127 | } |
| 128 | |
Martin Roth | 67efe44 | 2023-01-27 17:25:51 -0700 | [diff] [blame^] | 129 | static void fch_init_resets(void) |
| 130 | { |
| 131 | pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | TOGGLE_ALL_PWR_GOOD); |
| 132 | } |
| 133 | |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 134 | /* configure the general purpose PCIe clock outputs according to the devicetree settings */ |
| 135 | static void gpp_clk_setup(void) |
| 136 | { |
Robert Zieba | b3b27f7 | 2022-10-03 14:50:55 -0600 | [diff] [blame] | 137 | struct soc_amd_mendocino_config *cfg = config_of_soc(); |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 138 | |
| 139 | /* look-up table to be able to iterate over the PCIe clock output settings */ |
| 140 | const uint8_t gpp_clk_shift_lut[GPP_CLK_OUTPUT_COUNT] = { |
| 141 | GPP_CLK0_REQ_SHIFT, |
| 142 | GPP_CLK1_REQ_SHIFT, |
| 143 | GPP_CLK2_REQ_SHIFT, |
| 144 | GPP_CLK3_REQ_SHIFT, |
| 145 | GPP_CLK4_REQ_SHIFT, |
| 146 | GPP_CLK5_REQ_SHIFT, |
| 147 | GPP_CLK6_REQ_SHIFT, |
| 148 | }; |
| 149 | |
| 150 | uint32_t gpp_clk_ctl = misc_read32(GPP_CLK_CNTRL); |
| 151 | |
Robert Zieba | b3b27f7 | 2022-10-03 14:50:55 -0600 | [diff] [blame] | 152 | pcie_gpp_dxio_update_clk_req_config(&cfg->gpp_clk_config[0], |
| 153 | ARRAY_SIZE(cfg->gpp_clk_config)); |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 154 | for (int i = 0; i < GPP_CLK_OUTPUT_COUNT; i++) { |
| 155 | gpp_clk_ctl &= ~GPP_CLK_REQ_MASK(gpp_clk_shift_lut[i]); |
| 156 | /* |
| 157 | * The remapping of values is done so that the default of the enum used for the |
| 158 | * devicetree settings is the clock being enabled, so that a missing devicetree |
| 159 | * configuration for this will result in an always active clock and not an |
Felix Held | a05f518 | 2022-06-10 21:04:36 +0200 | [diff] [blame] | 160 | * inactive PCIe clock output. Only the configuration for the clock outputs |
| 161 | * available on the package is provided via the devicetree; the rest is |
| 162 | * switched off unconditionally. |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 163 | */ |
Felix Held | a05f518 | 2022-06-10 21:04:36 +0200 | [diff] [blame] | 164 | switch (i < GPP_CLK_OUTPUT_AVAILABLE ? cfg->gpp_clk_config[i] : GPP_CLK_OFF) { |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 165 | case GPP_CLK_REQ: |
| 166 | gpp_clk_ctl |= GPP_CLK_REQ_EXT(gpp_clk_shift_lut[i]); |
| 167 | break; |
| 168 | case GPP_CLK_OFF: |
| 169 | gpp_clk_ctl |= GPP_CLK_REQ_OFF(gpp_clk_shift_lut[i]); |
| 170 | break; |
| 171 | case GPP_CLK_ON: |
| 172 | default: |
| 173 | gpp_clk_ctl |= GPP_CLK_REQ_ON(gpp_clk_shift_lut[i]); |
| 174 | } |
| 175 | } |
| 176 | |
| 177 | misc_write32(GPP_CLK_CNTRL, gpp_clk_ctl); |
| 178 | } |
| 179 | |
| 180 | static void cgpll_clock_gate_init(void) |
| 181 | { |
| 182 | uint32_t t; |
| 183 | |
| 184 | t = misc_read32(MISC_CLKGATEDCNTL); |
| 185 | t |= ALINKCLK_GATEOFFEN; |
| 186 | t |= BLINKCLK_GATEOFFEN; |
Felix Held | 3046948 | 2022-08-01 17:37:46 +0200 | [diff] [blame] | 187 | t |= XTAL_PAD_S0I3_TURNOFF_EN; |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 188 | t |= XTAL_PAD_S3_TURNOFF_EN; |
| 189 | t |= XTAL_PAD_S5_TURNOFF_EN; |
| 190 | misc_write32(MISC_CLKGATEDCNTL, t); |
| 191 | |
| 192 | t = misc_read32(MISC_CGPLL_CONFIGURATION0); |
| 193 | t |= USB_PHY_CMCLK_S3_DIS; |
| 194 | t |= USB_PHY_CMCLK_S0I3_DIS; |
| 195 | t |= USB_PHY_CMCLK_S5_DIS; |
| 196 | misc_write32(MISC_CGPLL_CONFIGURATION0, t); |
| 197 | |
| 198 | t = pm_read32(PM_ISACONTROL); |
| 199 | t |= ABCLKGATEEN; |
| 200 | pm_write32(PM_ISACONTROL, t); |
| 201 | } |
| 202 | |
| 203 | void fch_init(void *chip_info) |
| 204 | { |
Martin Roth | 67efe44 | 2023-01-27 17:25:51 -0700 | [diff] [blame^] | 205 | fch_init_resets(); |
Felix Held | 3c44c62 | 2022-01-10 20:57:29 +0100 | [diff] [blame] | 206 | i2c_soc_init(); |
| 207 | fch_init_acpi_ports(); |
| 208 | |
| 209 | acpi_pm_gpe_add_events_print_events(); |
| 210 | gpio_add_events(); |
| 211 | |
| 212 | gpp_clk_setup(); |
| 213 | fch_clk_output_48Mhz(); |
| 214 | cgpll_clock_gate_init(); |
| 215 | } |
| 216 | |
| 217 | void fch_final(void *chip_info) |
| 218 | { |
| 219 | } |
| 220 | |
| 221 | static void set_pci_irqs(void *unused) |
| 222 | { |
| 223 | /* Write PCI_INTR regs 0xC00/0xC01 */ |
| 224 | write_pci_int_table(); |
| 225 | |
| 226 | /* pirq_data is consumed by `write_pci_cfg_irqs` */ |
| 227 | populate_pirq_data(); |
| 228 | |
| 229 | /* Write IRQs for all devicetree enabled devices */ |
| 230 | write_pci_cfg_irqs(); |
| 231 | } |
| 232 | |
| 233 | /* |
| 234 | * Hook this function into the PCI state machine |
| 235 | * on entry into BS_DEV_ENABLE. |
| 236 | */ |
| 237 | BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); |