Andrey Petrov | 57799dc | 2016-02-09 17:02:57 -0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2015 Intel Corp. |
| 5 | * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.) |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
Martin Roth | ebabfad | 2016-04-10 11:09:16 -0600 | [diff] [blame] | 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Andrey Petrov | 57799dc | 2016-02-09 17:02:57 -0800 | [diff] [blame] | 16 | */ |
| 17 | |
Aaron Durbin | c370fe3 | 2016-02-11 16:08:49 -0600 | [diff] [blame] | 18 | #include <assert.h> |
Aaron Durbin | fc6a9f2 | 2016-05-12 15:55:43 -0500 | [diff] [blame] | 19 | #include <gpio.h> |
Andrey Petrov | 57799dc | 2016-02-09 17:02:57 -0800 | [diff] [blame] | 20 | #include <soc/gpio.h> |
| 21 | #include <soc/iosf.h> |
Aaron Durbin | b72c67b | 2016-07-12 17:32:52 -0500 | [diff] [blame] | 22 | #include <soc/itss.h> |
Shaunak Saha | 5b6c5a5 | 2016-06-07 02:06:28 -0700 | [diff] [blame] | 23 | #include <soc/pm.h> |
Andrey Petrov | 57799dc | 2016-02-09 17:02:57 -0800 | [diff] [blame] | 24 | |
| 25 | /* This list must be in order, from highest pad numbers, to lowest pad numbers*/ |
| 26 | static const struct pad_community { |
| 27 | uint16_t first_pad; |
| 28 | uint8_t port; |
| 29 | } gpio_communities[] = { |
| 30 | { |
| 31 | .port = GPIO_SOUTHWEST, |
| 32 | .first_pad = SW_OFFSET, |
| 33 | }, { |
| 34 | .port = GPIO_WEST, |
| 35 | .first_pad = W_OFFSET, |
| 36 | }, { |
| 37 | .port = GPIO_NORTHWEST, |
| 38 | .first_pad = NW_OFFSET, |
| 39 | }, { |
| 40 | .port = GPIO_NORTH, |
Aaron Durbin | c65b8f1 | 2016-02-11 16:05:50 -0600 | [diff] [blame] | 41 | .first_pad = N_OFFSET, |
Andrey Petrov | 57799dc | 2016-02-09 17:02:57 -0800 | [diff] [blame] | 42 | } |
| 43 | }; |
| 44 | |
| 45 | static const struct pad_community *gpio_get_community(uint16_t pad) |
| 46 | { |
| 47 | const struct pad_community *map = gpio_communities; |
| 48 | |
Aaron Durbin | c370fe3 | 2016-02-11 16:08:49 -0600 | [diff] [blame] | 49 | assert(pad < TOTAL_PADS); |
| 50 | |
Andrey Petrov | 57799dc | 2016-02-09 17:02:57 -0800 | [diff] [blame] | 51 | while (map->first_pad > pad) |
| 52 | map++; |
| 53 | |
| 54 | return map; |
| 55 | } |
| 56 | |
Aaron Durbin | b72c67b | 2016-07-12 17:32:52 -0500 | [diff] [blame] | 57 | static void gpio_configure_itss(const struct pad_config *cfg, |
| 58 | uint16_t port, uint16_t pad_cfg_offset) |
| 59 | { |
| 60 | int irq; |
| 61 | |
| 62 | /* Set up ITSS polarity if pad is routed to APIC. |
| 63 | * |
| 64 | * The ITSS takes only active high interrupt signals. Therefore, |
| 65 | * if the pad configuration indicates an inversion assume the |
| 66 | * intent is for the ITSS polarity. Before forwarding on the |
| 67 | * request to the APIC there's an inversion setting for how the |
| 68 | * signal is forwarded to the APIC. Honor the inversion setting |
| 69 | * in the GPIO pad configuration so that a hardware active low |
| 70 | * signal looks that way to the APIC (double inversion). |
| 71 | */ |
| 72 | if (!(cfg->config0 & PAD_CFG0_ROUTE_IOAPIC)) |
| 73 | return; |
| 74 | |
| 75 | irq = iosf_read(port, pad_cfg_offset + sizeof(uint32_t)); |
| 76 | irq &= PAD_CFG1_IRQ_MASK; |
| 77 | if (!irq) { |
| 78 | printk(BIOS_ERR, "GPIO %u doesn't support APIC routing,\n", |
| 79 | cfg->pad); |
| 80 | return; |
| 81 | } |
| 82 | |
| 83 | itss_set_irq_polarity(irq, !!(cfg->config0 & PAD_CFG0_RX_POL_INVERT)); |
| 84 | } |
| 85 | |
Andrey Petrov | 57799dc | 2016-02-09 17:02:57 -0800 | [diff] [blame] | 86 | void gpio_configure_pad(const struct pad_config *cfg) |
| 87 | { |
Shankar, Vaibhav | 67d1697 | 2016-07-13 14:00:08 -0700 | [diff] [blame^] | 88 | uint32_t dw1; |
Andrey Petrov | 57799dc | 2016-02-09 17:02:57 -0800 | [diff] [blame] | 89 | const struct pad_community *comm = gpio_get_community(cfg->pad); |
| 90 | uint16_t config_offset = PAD_CFG_OFFSET(cfg->pad - comm->first_pad); |
Shankar, Vaibhav | 67d1697 | 2016-07-13 14:00:08 -0700 | [diff] [blame^] | 91 | |
| 92 | /* Iostandby bits are tentatively stored in [3:0] bits (RO) of config1. |
| 93 | * dw1 is used to extract the bits of Iostandby. |
| 94 | * This is done to preserve config1 size as unit16 in gpio.h. |
| 95 | */ |
| 96 | dw1 = cfg->config1 & ~PAD_CFG1_IOSSTATE_MASK; |
| 97 | dw1 |= (cfg->config1 & PAD_CFG1_IOSSTATE_MASK) << PAD_CFG1_IOSSTATE_SHIFT; |
| 98 | |
Andrey Petrov | 57799dc | 2016-02-09 17:02:57 -0800 | [diff] [blame] | 99 | iosf_write(comm->port, config_offset, cfg->config0); |
Shankar, Vaibhav | 67d1697 | 2016-07-13 14:00:08 -0700 | [diff] [blame^] | 100 | iosf_write(comm->port, config_offset + sizeof(uint32_t), dw1); |
Aaron Durbin | b72c67b | 2016-07-12 17:32:52 -0500 | [diff] [blame] | 101 | |
| 102 | gpio_configure_itss(cfg, comm->port, config_offset); |
Andrey Petrov | 57799dc | 2016-02-09 17:02:57 -0800 | [diff] [blame] | 103 | } |
| 104 | |
| 105 | void gpio_configure_pads(const struct pad_config *cfg, size_t num_pads) |
| 106 | { |
| 107 | uint32_t i; |
| 108 | |
| 109 | for (i = 0; i < num_pads; i++) |
| 110 | gpio_configure_pad(cfg + i); |
| 111 | } |
Aaron Durbin | fc6a9f2 | 2016-05-12 15:55:43 -0500 | [diff] [blame] | 112 | |
| 113 | void gpio_input_pulldown(gpio_t gpio) |
| 114 | { |
Aaron Durbin | a790f1b | 2016-07-06 22:41:24 -0500 | [diff] [blame] | 115 | struct pad_config cfg = PAD_CFG_GPI(gpio, DN_20K, DEEP); |
Aaron Durbin | fc6a9f2 | 2016-05-12 15:55:43 -0500 | [diff] [blame] | 116 | gpio_configure_pad(&cfg); |
| 117 | } |
| 118 | |
| 119 | void gpio_input_pullup(gpio_t gpio) |
| 120 | { |
Aaron Durbin | a790f1b | 2016-07-06 22:41:24 -0500 | [diff] [blame] | 121 | struct pad_config cfg = PAD_CFG_GPI(gpio, UP_20K, DEEP); |
Aaron Durbin | fc6a9f2 | 2016-05-12 15:55:43 -0500 | [diff] [blame] | 122 | gpio_configure_pad(&cfg); |
| 123 | } |
| 124 | |
| 125 | void gpio_input(gpio_t gpio) |
| 126 | { |
| 127 | struct pad_config cfg = PAD_CFG_GPI(gpio, NONE, DEEP); |
| 128 | gpio_configure_pad(&cfg); |
| 129 | } |
| 130 | |
| 131 | void gpio_output(gpio_t gpio, int value) |
| 132 | { |
| 133 | struct pad_config cfg = PAD_CFG_GPO(gpio, value, DEEP); |
| 134 | gpio_configure_pad(&cfg); |
| 135 | } |
| 136 | |
| 137 | int gpio_get(gpio_t gpio_num) |
| 138 | { |
| 139 | uint32_t reg; |
| 140 | const struct pad_community *comm = gpio_get_community(gpio_num); |
| 141 | uint16_t config_offset = PAD_CFG_OFFSET(gpio_num - comm->first_pad); |
| 142 | |
| 143 | reg = iosf_read(comm->port, config_offset); |
| 144 | |
| 145 | return !!(reg & PAD_CFG0_RX_STATE); |
| 146 | } |
| 147 | |
| 148 | void gpio_set(gpio_t gpio_num, int value) |
| 149 | { |
| 150 | uint32_t reg; |
| 151 | const struct pad_community *comm = gpio_get_community(gpio_num); |
| 152 | uint16_t config_offset = PAD_CFG_OFFSET(gpio_num - comm->first_pad); |
| 153 | |
| 154 | reg = iosf_read(comm->port, config_offset); |
| 155 | reg &= ~PAD_CFG0_TX_STATE; |
| 156 | reg |= !!value & PAD_CFG0_TX_STATE; |
| 157 | iosf_write(comm->port, config_offset, reg); |
| 158 | } |
Duncan Laurie | 2e63c2a | 2016-05-16 15:32:30 -0700 | [diff] [blame] | 159 | |
| 160 | const char *gpio_acpi_path(gpio_t gpio_num) |
| 161 | { |
| 162 | const struct pad_community *comm = gpio_get_community(gpio_num); |
| 163 | |
| 164 | switch (comm->port) { |
| 165 | case GPIO_NORTH: |
| 166 | return "\\_SB.GPO0"; |
| 167 | case GPIO_NORTHWEST: |
| 168 | return "\\_SB.GPO1"; |
| 169 | case GPIO_WEST: |
| 170 | return "\\_SB.GPO2"; |
| 171 | case GPIO_SOUTHWEST: |
| 172 | return "\\_SB.GPO3"; |
| 173 | } |
| 174 | |
| 175 | return NULL; |
| 176 | } |
Duncan Laurie | d25dd99 | 2016-06-29 10:47:48 -0700 | [diff] [blame] | 177 | |
| 178 | uint16_t gpio_acpi_pin(gpio_t gpio_num) |
| 179 | { |
| 180 | const struct pad_community *comm = gpio_get_community(gpio_num); |
| 181 | |
| 182 | switch (comm->port) { |
| 183 | case GPIO_NORTH: |
| 184 | return PAD_N(gpio_num); |
| 185 | case GPIO_NORTHWEST: |
| 186 | return PAD_NW(gpio_num); |
| 187 | case GPIO_WEST: |
| 188 | return PAD_W(gpio_num); |
| 189 | case GPIO_SOUTHWEST: |
| 190 | return PAD_SW(gpio_num); |
| 191 | } |
| 192 | |
| 193 | return gpio_num; |
| 194 | } |
Shaunak Saha | 5b6c5a5 | 2016-06-07 02:06:28 -0700 | [diff] [blame] | 195 | |
| 196 | /* Helper function to map PMC register groups to tier1 sci groups */ |
| 197 | static int pmc_gpe_route_to_gpio(int route) |
| 198 | { |
| 199 | switch(route) { |
| 200 | case PMC_GPE_SW_31_0: |
| 201 | return GPIO_GPE_SW_31_0; |
| 202 | case PMC_GPE_SW_63_32: |
| 203 | return GPIO_GPE_SW_63_32; |
| 204 | case PMC_GPE_NW_31_0: |
| 205 | return GPIO_GPE_NW_31_0; |
| 206 | case PMC_GPE_NW_63_32: |
| 207 | return GPIO_GPE_NW_63_32; |
| 208 | case PMC_GPE_NW_95_64: |
| 209 | return GPIO_GPE_NW_95_64; |
| 210 | case PMC_GPE_N_31_0: |
| 211 | return GPIO_GPE_N_31_0; |
| 212 | case PMC_GPE_N_63_32: |
| 213 | return GPIO_GPE_N_63_32; |
| 214 | case PMC_GPE_W_31_0: |
| 215 | return GPIO_GPE_W_31_0; |
| 216 | default: |
| 217 | return -1; |
| 218 | } |
| 219 | } |
| 220 | |
| 221 | void gpio_route_gpe(uint8_t gpe0b, uint8_t gpe0c, uint8_t gpe0d) |
| 222 | { |
| 223 | int i; |
| 224 | uint32_t misccfg_mask; |
| 225 | uint32_t misccfg_value; |
| 226 | uint32_t value; |
| 227 | |
| 228 | /* Get the group here for community specific MISCCFG register. |
| 229 | * If any of these returns -1 then there is some error in devicetree |
| 230 | * where the group is probably hardcoded and does not comply with the |
| 231 | * PMC group defines. So we return from here and MISCFG is set to |
| 232 | * default. |
| 233 | */ |
| 234 | gpe0b = pmc_gpe_route_to_gpio(gpe0b); |
| 235 | if(gpe0b == -1) |
| 236 | return; |
| 237 | gpe0c = pmc_gpe_route_to_gpio(gpe0c); |
| 238 | if(gpe0c == -1) |
| 239 | return; |
| 240 | gpe0d = pmc_gpe_route_to_gpio(gpe0d); |
| 241 | if(gpe0d == -1) |
| 242 | return; |
| 243 | |
| 244 | misccfg_value = gpe0b << MISCCFG_GPE0_DW0_SHIFT; |
| 245 | misccfg_value |= gpe0c << MISCCFG_GPE0_DW1_SHIFT; |
| 246 | misccfg_value |= gpe0d << MISCCFG_GPE0_DW2_SHIFT; |
| 247 | |
| 248 | /* Program GPIO_MISCCFG */ |
| 249 | misccfg_mask = ~(MISCCFG_GPE0_DW2_MASK | |
| 250 | MISCCFG_GPE0_DW1_MASK | |
| 251 | MISCCFG_GPE0_DW0_MASK); |
| 252 | |
| 253 | for (i = 0; i < ARRAY_SIZE(gpio_communities); i++) { |
| 254 | const struct pad_community *comm = &gpio_communities[i]; |
| 255 | |
| 256 | value = iosf_read(comm->port, GPIO_MISCCFG); |
| 257 | value &= misccfg_mask; |
| 258 | value |= misccfg_value; |
| 259 | iosf_write(comm->port, GPIO_MISCCFG, value); |
| 260 | } |
| 261 | } |