Angel Pons | 32859fc | 2020-04-02 23:48:27 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Naresh G Solanki | 335781a | 2016-10-26 19:43:14 +0530 | [diff] [blame] | 3 | |
| 4 | #ifndef SPD_BIN_H |
| 5 | #define SPD_BIN_H |
| 6 | |
Naresh G Solanki | 335781a | 2016-10-26 19:43:14 +0530 | [diff] [blame] | 7 | #include <stdint.h> |
| 8 | #include <commonlib/region.h> |
| 9 | |
| 10 | #define SPD_PAGE_LEN 256 |
| 11 | #define SPD_PAGE_LEN_DDR4 512 |
| 12 | #define SPD_PAGE_0 (0x6C >> 1) |
| 13 | #define SPD_PAGE_1 (0x6E >> 1) |
| 14 | #define SPD_DRAM_TYPE 2 |
| 15 | #define SPD_DRAM_DDR3 0x0B |
| 16 | #define SPD_DRAM_LPDDR3_INTEL 0xF1 |
| 17 | #define SPD_DRAM_LPDDR3_JEDEC 0x0F |
| 18 | #define SPD_DRAM_DDR4 0x0C |
Eric Lai | d0ee870 | 2020-03-06 21:18:30 +0800 | [diff] [blame] | 19 | #define SPD_DRAM_LPDDR4 0x10 |
Eric Lai | cb1e386 | 2020-03-13 17:16:20 +0800 | [diff] [blame] | 20 | #define SPD_DRAM_LPDDR4X 0x11 |
| 21 | #define SPD_DRAM_DDR5 0x12 |
| 22 | #define SPD_DRAM_LPDDR5 0x13 |
Naresh G Solanki | 335781a | 2016-10-26 19:43:14 +0530 | [diff] [blame] | 23 | #define SPD_DENSITY_BANKS 4 |
| 24 | #define SPD_ADDRESSING 5 |
Eric Lai | aa8d772 | 2019-09-02 15:01:56 +0800 | [diff] [blame] | 25 | #define DDR3_ORGANIZATION 7 |
| 26 | #define DDR3_BUS_DEV_WIDTH 8 |
| 27 | #define DDR4_ORGANIZATION 12 |
| 28 | #define DDR4_BUS_DEV_WIDTH 13 |
Naresh G Solanki | 335781a | 2016-10-26 19:43:14 +0530 | [diff] [blame] | 29 | #define DDR3_SPD_PART_OFF 128 |
| 30 | #define DDR3_SPD_PART_LEN 18 |
| 31 | #define LPDDR3_SPD_PART_OFF 128 |
| 32 | #define LPDDR3_SPD_PART_LEN 18 |
| 33 | #define DDR4_SPD_PART_OFF 329 |
| 34 | #define DDR4_SPD_PART_LEN 20 |
Naresh G Solanki | 335781a | 2016-10-26 19:43:14 +0530 | [diff] [blame] | 35 | |
| 36 | struct spd_block { |
Nico Huber | 5f9c673 | 2017-06-28 16:42:51 +0200 | [diff] [blame] | 37 | u8 addr_map[CONFIG_DIMM_MAX]; /* 7 bit I2C addresses */ |
Naresh G Solanki | 335781a | 2016-10-26 19:43:14 +0530 | [diff] [blame] | 38 | u8 *spd_array[CONFIG_DIMM_MAX]; |
| 39 | /* Length of each dimm */ |
| 40 | u16 len; |
| 41 | }; |
| 42 | |
| 43 | void print_spd_info(uint8_t spd[]); |
| 44 | /* Return 0 on success & -1 on failure */ |
| 45 | int get_spd_cbfs_rdev(struct region_device *spd_rdev, u8 spd_index); |
| 46 | void dump_spd_info(struct spd_block *blk); |
| 47 | void get_spd_smbus(struct spd_block *blk); |
| 48 | |
Patrick Georgi | 0e3c59e | 2017-01-28 15:59:25 +0100 | [diff] [blame] | 49 | /* expects SPD size to be 128 bytes, reads from "spd.bin" in CBFS and |
| 50 | verifies the checksum. Only available if CONFIG_DIMM_SPD_SIZE == 128. */ |
| 51 | int read_ddr3_spd_from_cbfs(u8 *buf, int idx); |
Naresh G Solanki | 335781a | 2016-10-26 19:43:14 +0530 | [diff] [blame] | 52 | #endif |