Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 2 | |
| 3 | #include <console/console.h> |
| 4 | #include <device/device.h> |
| 5 | #include <device/pci.h> |
Kyösti Mälkki | df128a5 | 2019-09-21 18:35:37 +0300 | [diff] [blame] | 6 | #include <device/pci_def.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 7 | #include <device/pci_ops.h> |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 8 | #include <device/pciexp.h> |
| 9 | #include <device/pci_ids.h> |
Vladimir Serbinenko | 36fa5b8 | 2014-10-28 23:43:20 +0100 | [diff] [blame] | 10 | #include <southbridge/intel/common/pciehp.h> |
| 11 | #include "chip.h" |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 12 | |
| 13 | static void pci_init(struct device *dev) |
| 14 | { |
| 15 | u16 reg16; |
| 16 | u32 reg32; |
Vladimir Serbinenko | 36fa5b8 | 2014-10-28 23:43:20 +0100 | [diff] [blame] | 17 | struct southbridge_intel_i82801ix_config *config = dev->chip_info; |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 18 | |
| 19 | printk(BIOS_DEBUG, "Initializing ICH9 PCIe root port.\n"); |
| 20 | |
| 21 | /* Enable Bus Master */ |
Elyes HAOUAS | b9d2e22 | 2020-04-28 10:25:12 +0200 | [diff] [blame] | 22 | pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 23 | |
| 24 | /* Set Cache Line Size to 0x10 */ |
| 25 | // This has no effect but the OS might expect it |
| 26 | pci_write_config8(dev, 0x0c, 0x10); |
| 27 | |
Kyösti Mälkki | df128a5 | 2019-09-21 18:35:37 +0300 | [diff] [blame] | 28 | reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL); |
| 29 | reg16 &= ~PCI_BRIDGE_CTL_PARITY; |
| 30 | reg16 |= PCI_BRIDGE_CTL_NO_ISA; |
| 31 | pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16); |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 32 | |
| 33 | /* Enable IO xAPIC on this PCIe port */ |
| 34 | reg32 = pci_read_config32(dev, 0xd8); |
| 35 | reg32 |= (1 << 7); |
| 36 | pci_write_config32(dev, 0xd8, reg32); |
| 37 | |
| 38 | /* Enable Backbone Clock Gating */ |
| 39 | reg32 = pci_read_config32(dev, 0xe1); |
| 40 | reg32 |= (1 << 3) | (1 << 2) | (1 << 1) | (1 << 0); |
| 41 | pci_write_config32(dev, 0xe1, reg32); |
| 42 | |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 43 | /* Set VC0 transaction class */ |
Kyösti Mälkki | 9b143e1 | 2013-07-26 08:35:09 +0300 | [diff] [blame] | 44 | reg32 = pci_read_config32(dev, 0x114); |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 45 | reg32 &= 0xffffff00; |
| 46 | reg32 |= 1; |
Kyösti Mälkki | 9b143e1 | 2013-07-26 08:35:09 +0300 | [diff] [blame] | 47 | pci_write_config32(dev, 0x114, reg32); |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 48 | |
| 49 | /* Mask completion timeouts */ |
Kyösti Mälkki | 9b143e1 | 2013-07-26 08:35:09 +0300 | [diff] [blame] | 50 | reg32 = pci_read_config32(dev, 0x148); |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 51 | reg32 |= (1 << 14); |
Kyösti Mälkki | 9b143e1 | 2013-07-26 08:35:09 +0300 | [diff] [blame] | 52 | pci_write_config32(dev, 0x148, reg32); |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 53 | |
| 54 | /* Lock R/WO Correctable Error Mask. */ |
Kyösti Mälkki | 9b143e1 | 2013-07-26 08:35:09 +0300 | [diff] [blame] | 55 | pci_write_config32(dev, 0x154, pci_read_config32(dev, 0x154)); |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 56 | |
| 57 | /* Clear errors in status registers */ |
| 58 | reg16 = pci_read_config16(dev, 0x06); |
| 59 | pci_write_config16(dev, 0x06, reg16); |
| 60 | reg16 = pci_read_config16(dev, 0x1e); |
| 61 | pci_write_config16(dev, 0x1e, reg16); |
| 62 | |
| 63 | /* Get configured ASPM state */ |
| 64 | const enum aspm_type apmc = pci_read_config32(dev, 0x50) & 3; |
| 65 | |
| 66 | /* If both L0s and L1 enabled then set root port 0xE8[1]=1 */ |
| 67 | if (apmc == PCIE_ASPM_BOTH) { |
| 68 | reg32 = pci_read_config32(dev, 0xe8); |
| 69 | reg32 |= (1 << 1); |
| 70 | pci_write_config32(dev, 0xe8, reg32); |
| 71 | } |
Vladimir Serbinenko | 36fa5b8 | 2014-10-28 23:43:20 +0100 | [diff] [blame] | 72 | |
| 73 | /* Enable expresscard hotplug events. */ |
| 74 | if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) { |
| 75 | pci_write_config32(dev, 0xd8, |
| 76 | pci_read_config32(dev, 0xd8) |
| 77 | | (1 << 30)); |
| 78 | pci_write_config16(dev, 0x42, 0x142); |
| 79 | } |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 80 | } |
| 81 | |
Elyes HAOUAS | 8aa5073 | 2018-05-13 13:34:58 +0200 | [diff] [blame] | 82 | static void pch_pciexp_scan_bridge(struct device *dev) |
Vladimir Serbinenko | 36fa5b8 | 2014-10-28 23:43:20 +0100 | [diff] [blame] | 83 | { |
Vladimir Serbinenko | 36fa5b8 | 2014-10-28 23:43:20 +0100 | [diff] [blame] | 84 | struct southbridge_intel_i82801ix_config *config = dev->chip_info; |
| 85 | |
| 86 | /* Normal PCIe Scan */ |
Kyösti Mälkki | 580e722 | 2015-03-19 21:04:23 +0200 | [diff] [blame] | 87 | pciexp_scan_bridge(dev); |
Vladimir Serbinenko | 36fa5b8 | 2014-10-28 23:43:20 +0100 | [diff] [blame] | 88 | |
| 89 | if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) { |
| 90 | intel_acpi_pcie_hotplug_scan_slot(dev->link_list); |
| 91 | } |
Vladimir Serbinenko | 36fa5b8 | 2014-10-28 23:43:20 +0100 | [diff] [blame] | 92 | } |
| 93 | |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 94 | static struct device_operations device_ops = { |
| 95 | .read_resources = pci_bus_read_resources, |
| 96 | .set_resources = pci_dev_set_resources, |
| 97 | .enable_resources = pci_bus_enable_resources, |
| 98 | .init = pci_init, |
Vladimir Serbinenko | 36fa5b8 | 2014-10-28 23:43:20 +0100 | [diff] [blame] | 99 | .scan_bus = pch_pciexp_scan_bridge, |
Angel Pons | 1fc0edd | 2020-05-31 00:03:28 +0200 | [diff] [blame] | 100 | .ops_pci = &pci_dev_ops_pci, |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 101 | }; |
| 102 | |
| 103 | /* 82801Ix (ICH9DH/ICH9DO/ICH9R/ICH9/ICH9M-E/ICH9M) */ |
| 104 | static const unsigned short pci_device_ids[] = { |
Felix Singer | 7f8b0cd8 | 2019-11-10 11:04:08 +0100 | [diff] [blame] | 105 | PCI_DEVICE_ID_INTEL_82801IB_PCIE1, /* Port 1 */ |
| 106 | PCI_DEVICE_ID_INTEL_82801IB_PCIE2, /* Port 2 */ |
| 107 | PCI_DEVICE_ID_INTEL_82801IB_PCIE3, /* Port 3 */ |
| 108 | PCI_DEVICE_ID_INTEL_82801IB_PCIE4, /* Port 4 */ |
| 109 | PCI_DEVICE_ID_INTEL_82801IB_PCIE5, /* Port 5 */ |
| 110 | PCI_DEVICE_ID_INTEL_82801IB_PCIE6, /* Port 6 */ |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 111 | 0 |
| 112 | }; |
| 113 | static const struct pci_driver ich9_pcie __pci_driver = { |
| 114 | .ops = &device_ops, |
| 115 | .vendor = PCI_VENDOR_ID_INTEL, |
| 116 | .devices = pci_device_ids, |
| 117 | }; |