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review.coreboot.org / coreboot / 66b0d55d326540e400ad3fa5130666dbd03b9694 / . / src / soc / mediatek / mt8173 / mt6391.c
blob: ec7fabc5549fd74644f9278c491e74b280f4ea8a [file] [log] [blame]
henryc.chen31ae3142015-07-31 17:10:52 +0800[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2015 MediaTek Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
henryc.chen31ae3142015-07-31 17:10:52 +0800[diff] [blame]14 */
Biao Huang0dd83152015-09-03 17:39:12 +0800[diff] [blame]15#include <arch/io.h>
henryc.chen31ae3142015-07-31 17:10:52 +0800[diff] [blame]16#include <assert.h>
17#include <console/console.h>
18#include <delay.h>
Biao Huang0dd83152015-09-03 17:39:12 +0800[diff] [blame]19#include <soc/addressmap.h>
henryc.chen31ae3142015-07-31 17:10:52 +0800[diff] [blame]20#include <soc/mt6391.h>
21#include <soc/pmic_wrap.h>
Biao Huang0dd83152015-09-03 17:39:12 +0800[diff] [blame]22#include <types.h>
henryc.chen31ae3142015-07-31 17:10:52 +0800[diff] [blame]23
24#if CONFIG_DEBUG_PMIC
25#define DEBUG_PMIC(level, x...) printk(level, x)
26#else
27#define DEBUG_PMIC(level, x...)
28#endif
29
30u32 mt6391_read(u16 reg, u32 mask, u32 shift)
31{
32 u16 rdata;
33
34 pwrap_wacs2(0, reg, 0, &rdata, 1);
35 rdata &= (mask << shift);
36 rdata = (rdata >> shift);
37
38 DEBUG_PMIC(BIOS_INFO, "[%s] Reg[%#x]=%#x\n",
39 __func__, reg, rdata);
40 return rdata;
41}
42
43void mt6391_write(u16 reg, u16 val, u32 mask, u32 shift)
44{
45 u16 rdata;
46 u16 old_rdata, new_rdata;
47
48 pwrap_wacs2(0, reg, 0, &rdata, 1);
49 old_rdata = rdata;
50
51 rdata &= ~(mask << shift);
52 rdata |= (val << shift);
53 new_rdata = rdata;
54
55 pwrap_wacs2(1, reg, rdata, &rdata, 1);
56
57 DEBUG_PMIC(BIOS_INFO, "[%s] write Reg[%#x]=%#x -> %#x\n",
58 __func__, reg, old_rdata, new_rdata);
59 return;
60}
61
Yidi Lina622f282016-01-29 17:25:03 +0800[diff] [blame]62int mt6391_configure_ca53_voltage(int uv)
63{
64 /* target voltage = 700mv + 6.25mv * buck_val */
65 u16 buck_val = (uv - 700000) / 6250;
66 u16 current_val = mt6391_read(PMIC_RG_VCA15_CON12, 0x7f, 0x0);
67
68 assert(buck_val < (1 << 8));
69 mt6391_write(PMIC_RG_VCA15_CON9, buck_val, 0x7f, 0x0);
70 mt6391_write(PMIC_RG_VCA15_CON10, buck_val, 0x7f, 0x0);
71
72 /* For buck delay, default slew rate is 6.25mv/0.5us */
73 if (buck_val > current_val)
74 return ((buck_val - current_val) / 2) ;
75 else
76 return 0;
77}
78
Koro Chen64a6b922015-07-31 17:11:04 +0800[diff] [blame]79static void mt6391_configure_vcama(enum ldo_voltage vsel)
80{
81 /* 2'b00: 1.5V
82 * 2'b01: 1.8V
83 * 2'b10: 2.5V
84 * 2'b11: 2.8V
85 */
86 mt6391_write(PMIC_RG_ANALDO_CON6, vsel - 2, PMIC_RG_VCAMA_VOSEL_MASK,
87 PMIC_RG_VCAMA_VOSEL_SHIFT);
88 mt6391_write(PMIC_RG_ANALDO_CON2, 1, PMIC_RG_VCAMA_EN_MASK,
89 PMIC_RG_VCAMA_EN_SHIFT);
90}
91
henryc.chen31ae3142015-07-31 17:10:52 +0800[diff] [blame]92void mt6391_configure_ldo(enum ldo_power ldo, enum ldo_voltage vsel)
93{
94 u16 addr;
95 switch (ldo) {
96 case LDO_VCAMD:
97 assert(vsel != 0);
98 if (vsel == LDO_1P22)
99 vsel = 0;
100 break;
Jitao Shi8ea218b2016-01-11 19:24:37 +0800[diff] [blame]101 case LDO_VGP2:
henryc.chen31ae3142015-07-31 17:10:52 +0800[diff] [blame]102 assert(vsel != 1);
103 if (vsel == LDO_1P0)
104 vsel = 1;
105 break;
106 case LDO_VGP5:
107 assert(vsel != 7);
108 if (vsel == LDO_2P0)
109 vsel = 7;
110 break;
Koro Chen64a6b922015-07-31 17:11:04 +0800[diff] [blame]111 case LDO_VCAMA:
112 assert(vsel > LDO_1P3 && vsel < LDO_3P0);
113 mt6391_configure_vcama(vsel);
114 return;
henryc.chen31ae3142015-07-31 17:10:52 +0800[diff] [blame]115 default:
116 break;
117 }
118 assert(vsel < LDO_NUM_VOLTAGES);
119
120 if (ldo == LDO_VGP6)
121 addr = PMIC_RG_DIGLDO_CON33;
122 else
123 addr = PMIC_RG_DIGLDO_CON19 + ldo * 2;
124
125 mt6391_write(addr, vsel, 0x7, 5);
126 mt6391_write(PMIC_RG_DIGLDO_CON5 + ldo * 2, 1, 1, 15);
127
128}
129
130void mt6391_enable_reset_when_ap_resets(void)
131{
132 /* Enable AP watchdog reset */
133 mt6391_write(PMIC_RG_TOP_RST_MISC, 0x0, 0x1, 0);
134}
135
136static void mt6391_init_setting(void)
137{
138 /* Enable PMIC RST function (depends on main chip RST function) */
139 /*
140 * state1: RG_SYSRSTB_EN = 1, RG_STRUP_MAN_RST_EN=1, RG_RST_PART_SEL=1
141 * state2: RG_SYSRSTB_EN = 1, RG_STRUP_MAN_RST_EN=0, RG_RST_PART_SEL=1
142 * state3: RG_SYSRSTB_EN = 1, RG_STRUP_MAN_RST_EN=x, RG_RST_PART_SEL=0
143 */
144 mt6391_write(PMIC_RG_TOP_RST_MISC, 0x1, 0x1, 1);
145 mt6391_write(PMIC_RG_TOP_RST_MISC, 0x0, 0x1, 2);
146 mt6391_write(PMIC_RG_TOP_RST_MISC, 0x1, 0x1, 4);
147
148 /* Disable AP watchdog reset */
149 mt6391_write(PMIC_RG_TOP_RST_MISC, 0x1, 0x1, 0);
150
151 /* Enable CA15 by default for different PMIC behavior */
152 mt6391_write(PMIC_RG_VCA15_CON7, 0x1, 0x1, 0);
153 mt6391_write(PMIC_RG_VSRMCA15_CON7, 0x1, 0x1, 0);
154 mt6391_write(PMIC_RG_VPCA7_CON7, 0x1, 0x1, 0);
155 udelay(200); /* delay for Buck ready */
156
157 /* [3:3]: RG_PWMOC_CK_PDN; For OC protection */
158 mt6391_write(PMIC_RG_TOP_CKPDN, 0x0, 0x1, 3);
159 /* [9:9]: RG_SRCVOLT_HW_AUTO_EN; */
160 mt6391_write(PMIC_RG_TOP_CKCON1, 0x1, 0x1, 9);
161 /* [8:8]: RG_OSC_SEL_AUTO; */
162 mt6391_write(PMIC_RG_TOP_CKCON1, 0x1, 0x1, 8);
163 /* [6:6]: RG_SMPS_DIV2_SRC_AUTOFF_DIS; */
164 mt6391_write(PMIC_RG_TOP_CKCON1, 0x1, 0x1, 6);
165 /* [5:5]: RG_SMPS_AUTOFF_DIS; */
166 mt6391_write(PMIC_RG_TOP_CKCON1, 0x1, 0x1, 5);
167 /* [7:7]: VDRM_DEG_EN; */
168 mt6391_write(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 7);
169 /* [6:6]: VSRMCA7_DEG_EN; */
170 mt6391_write(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 6);
171 /* [5:5]: VPCA7_DEG_EN; */
172 mt6391_write(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 5);
173 /* [4:4]: VIO18_DEG_EN; */
174 mt6391_write(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 4);
175 /* [3:3]: VGPU_DEG_EN; For OC protection */
176 mt6391_write(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 3);
177 /* [2:2]: VCORE_DEG_EN; */
178 mt6391_write(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 2);
179 /* [1:1]: VSRMCA15_DEG_EN; */
180 mt6391_write(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 1);
181 /* [0:0]: VCA15_DEG_EN; */
182 mt6391_write(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 0);
183 /* [11:11]: RG_INT_EN_THR_H; */
184 mt6391_write(PMIC_RG_INT_CON0, 0x1, 0x1, 11);
185 /* [10:10]: RG_INT_EN_THR_L; */
186 mt6391_write(PMIC_RG_INT_CON0, 0x1, 0x1, 10);
187 /* [4:4]: RG_INT_EN_BAT_L; */
188 mt6391_write(PMIC_RG_INT_CON0, 0x1, 0x1, 4);
189 /* [11:11]: RG_INT_EN_VGPU; OC protection */
190 mt6391_write(PMIC_RG_INT_CON1, 0x1, 0x1, 11);
191 /* [8:8]: RG_INT_EN_VCA15; OC protection */
192 mt6391_write(PMIC_RG_INT_CON1, 0x1, 0x1, 8);
193 /* [12:0]: BUCK_RSV; for OC protection */
194 mt6391_write(PMIC_RG_BUCK_CON3, 0x600, 0x0FFF, 0);
195 /* [11:10]: QI_VCORE_VSLEEP; sleep mode only (0.7V) */
henryc.chen53e78532016-04-25 15:53:29 +0800[diff] [blame]196 mt6391_write(PMIC_RG_BUCK_CON8, 0x0, 0x3, 10);
henryc.chen31ae3142015-07-31 17:10:52 +0800[diff] [blame]197 /* [7:6]: QI_VSRMCA7_VSLEEP; sleep mode only (0.85V) */
198 mt6391_write(PMIC_RG_BUCK_CON8, 0x0, 0x3, 6);
199 /* [5:4]: QI_VSRMCA15_VSLEEP; sleep mode only (0.7V) */
200 mt6391_write(PMIC_RG_BUCK_CON8, 0x1, 0x3, 4);
201 /* [3:2]: QI_VPCA7_VSLEEP; sleep mode only (0.85V) */
202 mt6391_write(PMIC_RG_BUCK_CON8, 0x0, 0x3, 2);
203 /* [1:0]: QI_VCA15_VSLEEP; sleep mode only (0.7V) */
204 mt6391_write(PMIC_RG_BUCK_CON8, 0x1, 0x3, 0);
205 /* [13:12]: RG_VCA15_CSL2; for OC protection */
206 mt6391_write(PMIC_RG_VCA15_CON1, 0x0, 0x3, 12);
207 /* [11:10]: RG_VCA15_CSL1; for OC protection */
208 mt6391_write(PMIC_RG_VCA15_CON1, 0x0, 0x3, 10);
209 /* [15:15]: VCA15_SFCHG_REN; soft change rising enable */
210 mt6391_write(PMIC_RG_VCA15_CON8, 0x1, 0x1, 15);
211 /* [14:8]: VCA15_SFCHG_RRATE; soft change rising step=0.5 */
212 mt6391_write(PMIC_RG_VCA15_CON8, 0x5, 0x7F, 8);
213 /* [7:7]: VCA15_SFCHG_FEN; soft change falling enable */
214 mt6391_write(PMIC_RG_VCA15_CON8, 0x1, 0x1, 7);
215 /* [6:0]: VCA15_SFCHG_FRATE; soft change falling step=2us */
216 mt6391_write(PMIC_RG_VCA15_CON8, 0x17, 0x7F, 0);
217 /* [6:0]: VCA15_VOSEL_SLEEP; sleep mode only (0.7V) */
218 mt6391_write(PMIC_RG_VCA15_CON11, 0x0, 0x7F, 0);
219 /* [8:8]: VCA15_VSLEEP_EN; set sleep mode reference volt */
220 mt6391_write(PMIC_RG_VCA15_CON18, 0x1, 0x1, 8);
221 /* [5:4]: VCA15_VOSEL_TRANS_EN; rising & falling enable */
222 mt6391_write(PMIC_RG_VCA15_CON18, 0x3, 0x3, 4);
223 /* [5:5]: VSRMCA15_TRACK_SLEEP_CTRL; */
224 mt6391_write(PMIC_RG_VSRMCA15_CON5, 0x1, 0x1, 5);
225 /* [5:4]: VSRMCA15_VOSEL_SEL; */
226 mt6391_write(PMIC_RG_VSRMCA15_CON6, 0x0, 0x3, 4);
227 /* [15:15]: VSRMCA15_SFCHG_REN; */
228 mt6391_write(PMIC_RG_VSRMCA15_CON8, 0x1, 0x1, 15);
229 /* [14:8]: VSRMCA15_SFCHG_RRATE; */
230 mt6391_write(PMIC_RG_VSRMCA15_CON8, 0x5, 0x7F, 8);
231 /* [7:7]: VSRMCA15_SFCHG_FEN; */
232 mt6391_write(PMIC_RG_VSRMCA15_CON8, 0x1, 0x1, 7);
233 /* [6:0]: VSRMCA15_SFCHG_FRATE; */
234 mt6391_write(PMIC_RG_VSRMCA15_CON8, 0x17, 0x7F, 0);
235 /* [6:0]: VSRMCA15_VOSEL_SLEEP; Sleep mode setting on */
236 mt6391_write(PMIC_RG_VSRMCA15_CON11, 0x00, 0x7F, 0);
237 /* [8:8]: VSRMCA15_VSLEEP_EN; set sleep mode referenc */
238 mt6391_write(PMIC_RG_VSRMCA15_CON18, 0x1, 0x1, 8);
239 /* [5:4]: VSRMCA15_VOSEL_TRANS_EN; rising & falling e */
240 mt6391_write(PMIC_RG_VSRMCA15_CON18, 0x3, 0x3, 4);
241 /* [1:1]: VCORE_VOSEL_CTRL; sleep mode voltage control fo */
242 mt6391_write(PMIC_RG_VCORE_CON5, 0x1, 0x1, 1);
243 /* [5:4]: VCORE_VOSEL_SEL; */
244 mt6391_write(PMIC_RG_VCORE_CON6, 0x0, 0x3, 4);
245 /* [15:15]: VCORE_SFCHG_REN; */
246 mt6391_write(PMIC_RG_VCORE_CON8, 0x1, 0x1, 15);
247 /* [14:8]: VCORE_SFCHG_RRATE; */
248 mt6391_write(PMIC_RG_VCORE_CON8, 0x5, 0x7F, 8);
249 /* [6:0]: VCORE_SFCHG_FRATE; */
250 mt6391_write(PMIC_RG_VCORE_CON8, 0x17, 0x7F, 0);
251 /* [6:0]: VCORE_VOSEL_SLEEP; Sleep mode setting only (0. */
252 mt6391_write(PMIC_RG_VCORE_CON11, 0x0, 0x7F, 0);
253 /* [8:8]: VCORE_VSLEEP_EN; Sleep mode HW control R2R to */
254 mt6391_write(PMIC_RG_VCORE_CON18, 0x1, 0x1, 8);
255 /* [5:4]: VCORE_VOSEL_TRANS_EN; Follows MT6320 VCORE set */
256 mt6391_write(PMIC_RG_VCORE_CON18, 0x0, 0x3, 4);
257 /* [1:0]: VCORE_TRANSTD; */
258 mt6391_write(PMIC_RG_VCORE_CON18, 0x3, 0x3, 0);
259 /* [9:8]: RG_VGPU_CSL; for OC protection */
260 mt6391_write(PMIC_RG_VGPU_CON1, 0x1, 0x3, 8);
261 /* [15:15]: VGPU_SFCHG_REN; */
262 mt6391_write(PMIC_RG_VGPU_CON8, 0x1, 0x1, 15);
263 /* [14:8]: VGPU_SFCHG_RRATE; */
264 mt6391_write(PMIC_RG_VGPU_CON8, 0x5, 0x7F, 8);
265 /* [6:0]: VGPU_SFCHG_FRATE; */
266 mt6391_write(PMIC_RG_VGPU_CON8, 0x17, 0x7F, 0);
267 /* [5:4]: VGPU_VOSEL_TRANS_EN; */
268 mt6391_write(PMIC_RG_VGPU_CON18, 0x0, 0x3, 4);
269 /* [1:0]: VGPU_TRANSTD; */
270 mt6391_write(PMIC_RG_VGPU_CON18, 0x3, 0x3, 0);
271 /* [5:4]: VPCA7_VOSEL_SEL; */
272 mt6391_write(PMIC_RG_VPCA7_CON6, 0x0, 0x3, 4);
273 /* [15:15]: VPCA7_SFCHG_REN; */
274 mt6391_write(PMIC_RG_VPCA7_CON8, 0x1, 0x1, 15);
275 /* [14:8]: VPCA7_SFCHG_RRATE; */
276 mt6391_write(PMIC_RG_VPCA7_CON8, 0x5, 0x7F, 8);
277 /* [7:7]: VPCA7_SFCHG_FEN; */
278 mt6391_write(PMIC_RG_VPCA7_CON8, 0x1, 0x1, 7);
279 /* [6:0]: VPCA7_SFCHG_FRATE; */
280 mt6391_write(PMIC_RG_VPCA7_CON8, 0x17, 0x7F, 0);
281 /* [6:0]: VPCA7_VOSEL_SLEEP; */
282 mt6391_write(PMIC_RG_VPCA7_CON11, 0x18, 0x7F, 0);
283 /* [8:8]: VPCA7_VSLEEP_EN; */
284 mt6391_write(PMIC_RG_VPCA7_CON18, 0x0, 0x1, 8);
285 /* [5:4]: VPCA7_VOSEL_TRANS_EN; */
286 mt6391_write(PMIC_RG_VPCA7_CON18, 0x3, 0x3, 4);
287 /* [5:5]: VSRMCA7_TRACK_SLEEP_CTRL; */
288 mt6391_write(PMIC_RG_VSRMCA7_CON5, 0x0, 0x1, 5);
289 /* [5:4]: VSRMCA7_VOSEL_SEL; */
290 mt6391_write(PMIC_RG_VSRMCA7_CON6, 0x0, 0x3, 4);
291 /* [15:15]: VSRMCA7_SFCHG_REN; */
292 mt6391_write(PMIC_RG_VSRMCA7_CON8, 0x1, 0x1, 15);
293 /* [14:8]: VSRMCA7_SFCHG_RRATE; */
294 mt6391_write(PMIC_RG_VSRMCA7_CON8, 0x5, 0x7F, 8);
295 /* [7:7]: VSRMCA7_SFCHG_FEN; */
296 mt6391_write(PMIC_RG_VSRMCA7_CON8, 0x1, 0x1, 7);
297 /* [6:0]: VSRMCA7_SFCHG_FRATE; */
298 mt6391_write(PMIC_RG_VSRMCA7_CON8, 0x17, 0x7F, 0);
299 /* [6:0]: VSRMCA7_VOSEL_SLEEP; */
300 mt6391_write(PMIC_RG_VSRMCA7_CON11, 0x18, 0x7F, 0);
301 /* [8:8]: VSRMCA7_VSLEEP_EN; */
henryc.chenaad29032016-03-07 15:17:01 +0800[diff] [blame]302 mt6391_write(PMIC_RG_VSRMCA7_CON18, 0x0, 0x1, 8);
henryc.chen31ae3142015-07-31 17:10:52 +0800[diff] [blame]303 /* [5:4]: VSRMCA7_VOSEL_TRANS_EN; */
304 mt6391_write(PMIC_RG_VSRMCA7_CON18, 0x3, 0x3, 4);
305 /* [8:8]: VDRM_VSLEEP_EN; */
306 mt6391_write(PMIC_RG_VDRM_CON18, 0x1, 0x1, 8);
307 /* [2:2]: VIBR_THER_SHEN_EN; */
308 mt6391_write(PMIC_RG_DIGLDO_CON24, 0x1, 0x1, 2);
309 /* [5:5]: THR_HWPDN_EN; */
310 mt6391_write(PMIC_RG_STRUP_CON0, 0x1, 0x1, 5);
311 /* [3:3]: RG_RST_DRVSEL; */
312 mt6391_write(PMIC_RG_STRUP_CON2, 0x1, 0x1, 3);
313 /* [2:2]: RG_EN_DRVSEL; */
314 mt6391_write(PMIC_RG_STRUP_CON2, 0x1, 0x1, 2);
315 /* [1:1]: PWRBB_DEB_EN; */
316 mt6391_write(PMIC_RG_STRUP_CON5, 0x1, 0x1, 1);
317 /* [12:12]: VSRMCA15_PG_H2L_EN; */
318 mt6391_write(PMIC_RG_STRUP_CON7, 0x1, 0x1, 12);
319 /* [11:11]: VPCA15_PG_H2L_EN; */
320 mt6391_write(PMIC_RG_STRUP_CON7, 0x1, 0x1, 11);
321 /* [10:10]: VCORE_PG_H2L_EN; */
322 mt6391_write(PMIC_RG_STRUP_CON7, 0x1, 0x1, 10);
323 /* [9:9]: VSRMCA7_PG_H2L_EN; */
324 mt6391_write(PMIC_RG_STRUP_CON7, 0x1, 0x1, 9);
325 /* [8:8]: VPCA7_PG_H2L_EN; */
326 mt6391_write(PMIC_RG_STRUP_CON7, 0x1, 0x1, 8);
327 /* [1:1]: STRUP_PWROFF_PREOFF_EN; */
328 mt6391_write(PMIC_RG_STRUP_CON10, 0x1, 0x1, 1);
329 /* [0:0]: STRUP_PWROFF_SEQ_EN; */
330 mt6391_write(PMIC_RG_STRUP_CON10, 0x1, 0x1, 0);
331 /* [15:8]: RG_ADC_TRIM_CH_SEL; */
332 mt6391_write(PMIC_RG_AUXADC_CON14, 0xFC, 0xFF, 8);
333 /* [1:1]: FLASH_THER_SHDN_EN; */
334 mt6391_write(PMIC_RG_FLASH_CON0, 0x1, 0x1, 1);
335 /* [1:1]: KPLED_THER_SHDN_EN; */
336 mt6391_write(PMIC_RG_KPLED_CON0, 0x1, 0x1, 1);
337 /* [14:8]: VSRMCA15_VOSEL_OFFSET; set offset=100mV */
338 mt6391_write(PMIC_RG_VSRMCA15_CON19, 0x10, 0x7F, 8);
339 /* [6:0]: VSRMCA15_VOSEL_DELTA; set delta=0mV */
340 mt6391_write(PMIC_RG_VSRMCA15_CON19, 0x0, 0x7F, 0);
341 /* [14:8]: VSRMCA15_VOSEL_ON_HB; set HB=1.15V */
342 mt6391_write(PMIC_RG_VSRMCA15_CON20, 0x48, 0x7F, 8);
343 /* [6:0]: VSRMCA15_VOSEL_ON_LB; set LB=0.7V */
344 mt6391_write(PMIC_RG_VSRMCA15_CON20, 0x0, 0x7F, 0);
345 /* [6:0]: VSRMCA15_VOSEL_SLEEP_LB; set sleep LB=0.7V */
346 mt6391_write(PMIC_RG_VSRMCA15_CON21, 0x0, 0x7F, 0);
347 /* [14:8]: VSRMCA7_VOSEL_OFFSET; set offset=25mV */
348 mt6391_write(PMIC_RG_VSRMCA7_CON19, 0x4, 0x7F, 8);
349 /* [6:0]: VSRMCA7_VOSEL_DELTA; set delta=0mV */
350 mt6391_write(PMIC_RG_VSRMCA7_CON19, 0x0, 0x7F, 0);
351 /* [14:8]: VSRMCA7_VOSEL_ON_HB; set HB=1.275V */
352 mt6391_write(PMIC_RG_VSRMCA7_CON20, 0x5C, 0x7F, 8);
353 /* [6:0]: VSRMCA7_VOSEL_ON_LB; set LB=1.05000V */
354 mt6391_write(PMIC_RG_VSRMCA7_CON20, 0x38, 0x7F, 0);
355 /* [6:0]: VSRMCA7_VOSEL_SLEEP_LB; set sleep LB=0.85000 */
356 mt6391_write(PMIC_RG_VSRMCA7_CON21, 0x18, 0x7F, 0);
357 /* [1:1]: VCA15_VOSEL_CTRL, VCA15_EN_CTRL; DVS HW control */
358 mt6391_write(PMIC_RG_VCA15_CON5, 0x3, 0x3, 0);
359 /* [1:1]: VSRMCA15_VOSEL_CTRL, VSRAM15_EN_CTRL; */
360 mt6391_write(PMIC_RG_VSRMCA15_CON5, 0x3, 0x3, 0);
361 /* [1:1]: VPCA7_VOSEL_CTRL; */
362 mt6391_write(PMIC_RG_VPCA7_CON5, 0x0, 0x1, 1);
363 /* [1:1]: VSRMCA7_VOSEL_CTRL; */
364 mt6391_write(PMIC_RG_VSRMCA7_CON5, 0x0, 0x1, 1);
henryc.chenaad29032016-03-07 15:17:01 +0800[diff] [blame]365 /* [0:0]: VSRMCA7_EN_CTRL; */
366 mt6391_write(PMIC_RG_VSRMCA7_CON5, 0x1, 0x1, 0);
henryc.chen31ae3142015-07-31 17:10:52 +0800[diff] [blame]367 /* [4:4]: VCA15_TRACK_ON_CTRL; DVFS tracking enable */
368 mt6391_write(PMIC_RG_VCA15_CON5, 0x1, 0x1, 4);
369 /* [4:4]: VSRMCA15_TRACK_ON_CTRL; */
370 mt6391_write(PMIC_RG_VSRMCA15_CON5, 0x1, 0x1, 4);
371 /* [4:4]: VPCA7_TRACK_ON_CTRL; */
372 mt6391_write(PMIC_RG_VPCA7_CON5, 0x0, 0x1, 4);
373 /* [4:4]: VSRMCA7_TRACK_ON_CTRL; */
374 mt6391_write(PMIC_RG_VSRMCA7_CON5, 0x0, 0x1, 4);
375 /* [15:14]: VGPU OC; */
376 mt6391_write(PMIC_RG_OC_CTL1, 0x3, 0x3, 14);
377 /* [3:2]: VCA15 OC; */
378 mt6391_write(PMIC_RG_OC_CTL1, 0x3, 0x3, 2);
379
380 /* Set VPCA7 to 1.2V */
381 mt6391_write(PMIC_RG_VPCA7_CON9, 0x50, 0x7f, 0x0);
382 mt6391_write(PMIC_RG_VPCA7_CON10, 0x50, 0x7f, 0x0);
383 /* Set VSRMCA7 to 1.1V */
384 mt6391_write(PMIC_RG_VSRMCA7_CON9, 0x40, 0x7f, 0x0);
385 mt6391_write(PMIC_RG_VSRMCA7_CON10, 0x40, 0x7f, 0x0);
386
387 /* Enable VGP6 and set to 3.3V*/
388 mt6391_write(PMIC_RG_DIGLDO_CON10, 0x1, 0x1, 15);
389 mt6391_write(PMIC_RG_DIGLDO_CON33, 0x07, 0x07, 5);
390
391 /* Set VDRM to 1.21875V */
392 mt6391_write(PMIC_RG_VDRM_CON9, 0x43, 0x7F, 0);
393 mt6391_write(PMIC_RG_VDRM_CON10, 0x43, 0x7F, 0);
394
395 /* 26M clock amplitute adjust */
396 mt6391_write(PMIC_RG_DCXO_ANALOG_CON1, 0x0, 0x3, 2);
397 mt6391_write(PMIC_RG_DCXO_ANALOG_CON1, 0x1, 0x3, 11);
398
399 /* For low power, set VTCXO switch by SRCVOLTEN */
400 mt6391_write(PMIC_RG_DIGLDO_CON27, 0x0100, 0x0100, 0);
401 /* [6:5]=0(VTCXO_SRCLK_MODE_SEL) */
402 mt6391_write(PMIC_RG_ANALDO_CON0, 0, 0x3, 13);
403 /* [11]=0(VTCXO_ON_CTRL), */
404 mt6391_write(PMIC_RG_ANALDO_CON0, 1, 0x1, 11);
405 /* [10]=1(RG_VTCXO_EN), */
406 mt6391_write(PMIC_RG_ANALDO_CON0, 1, 0x1, 10);
407 /* [4:3]=1(RG_VTCXOTD_SEL) */
408 mt6391_write(PMIC_RG_ANALDO_CON0, 0x3, 0x3, 3);
409 /* For low power, VIO18 set sleep_en to HW mode */
410 mt6391_write(PMIC_RG_VIO18_CON18, 0x1, 0x1, 8);
411
412}
413
414static void mt6391_default_buck_voltage(void)
415{
416 u16 reg_val = 0;
417 u16 buck_val = 0;
418 /* There are two kinds of PMIC used for MT8173 : MT6397s/MT6391.
419 * MT6397s: the default voltage of register was not suitable for
420 * MT8173, needs to apply the setting of eFuse.
421 * VPCA15/VSRMCA15/: 1.15V
422 * VCORE: 1.05V
423 *
424 * MT6391: the default voltage of register was matched for MT8173.
425 * VPAC15/VCORE/VGPU: 1.0V
426 * VSRMCA15: 1.0125V
427 */
428 reg_val = mt6391_read(PMIC_RG_EFUSE_DOUT_288_303, 0xFFFF, 0);
429
430 if ((reg_val & 0x01) == 0x01) {
431 /* VCORE */
432 reg_val = mt6391_read(PMIC_RG_EFUSE_DOUT_256_271, 0xF, 12);
433 buck_val = mt6391_read(PMIC_RG_VCORE_CON9, 0x7f, 0x0);
434
435 /* VCORE_VOSEL[3:6] => eFuse bit 268-271 */
436 buck_val = (buck_val & 0x07) | (reg_val << 3);
437 mt6391_write(PMIC_RG_VCORE_CON9, buck_val, 0x7f, 0x0);
438 mt6391_write(PMIC_RG_VCORE_CON10, buck_val, 0x7f, 0x0);
439
440 reg_val = mt6391_read(PMIC_RG_EFUSE_DOUT_272_287, 0xFFFF, 0);
441 /* VCA15 */
442 buck_val = 0;
443 buck_val = mt6391_read(PMIC_RG_VCA15_CON9, 0x7f, 0x0);
444 buck_val = (buck_val & 0x07) | ((reg_val & 0x0F) << 3);
445 mt6391_write(PMIC_RG_VCA15_CON9, buck_val, 0x7f, 0x0);
446 mt6391_write(PMIC_RG_VCA15_CON10, buck_val, 0x7f, 0x0);
447
448 /* VSAMRCA15 */
449 buck_val = 0;
450 buck_val = mt6391_read(PMIC_RG_VSRMCA15_CON9, 0x7f, 0x0);
451 buck_val = (buck_val & 0x07) | ((reg_val & 0xF0) >> 1);
452 mt6391_write(PMIC_RG_VSRMCA15_CON9, buck_val, 0x7f, 0x0);
453 mt6391_write(PMIC_RG_VSRMCA15_CON10, buck_val, 0x7f, 0x0);
454
455 /* set the power control by register(use original) */
456 mt6391_write(PMIC_RG_BUCK_CON3, 0x1, 0x1, 12);
457 }
458}
459
460void mt6391_init(void)
461{
462 if (pwrap_init())
463 die("ERROR - Failed to initial pmic wrap!");
464 /* pmic initial setting */
465 mt6391_init_setting();
466
467 /* Adjust default BUCK voltage from eFuse */
468 mt6391_default_buck_voltage();
469}
Biao Huang0dd83152015-09-03 17:39:12 +0800[diff] [blame]470
471/* API of GPIO in PMIC MT6391 */
472enum {
473 MAX_GPIO_REG_BITS = 16,
474 MAX_GPIO_MODE_PER_REG = 5,
475 GPIO_MODE_BITS = 3,
476 GPIO_PORT_OFFSET = 3,
477 GPIO_SET_OFFSET = 2,
478 GPIO_RST_OFFSET = 4,
479 MAX_MT6391_GPIO = 40
480};
481
482enum {
483 MT6391_GPIO_DIRECTION_IN = 0,
484 MT6391_GPIO_DIRECTION_OUT = 1,
485};
486
487enum {
488 MT6391_GPIO_MODE = 0,
489};
490
491static void pos_bit_calc(u32 pin, u16 *pos, u16 *bit)
492{
493 *pos = (pin / MAX_GPIO_REG_BITS) << GPIO_PORT_OFFSET;
494 *bit = pin % MAX_GPIO_REG_BITS;
495}
496
497static void pos_bit_calc_mode(u32 pin, u16 *pos, u16 *bit)
498{
499 *pos = (pin / MAX_GPIO_MODE_PER_REG) << GPIO_PORT_OFFSET;
500 *bit = (pin % MAX_GPIO_MODE_PER_REG) * GPIO_MODE_BITS;
501}
502
503static s32 mt6391_gpio_set_dir(u32 pin, u32 dir)
504{
505 u16 pos;
506 u16 bit;
507 u16 reg;
508
509 assert(pin <= MAX_MT6391_GPIO);
510
511 pos_bit_calc(pin, &pos, &bit);
512
513 if (dir == MT6391_GPIO_DIRECTION_IN)
514 reg = MT6391_GPIO_DIR_BASE + pos + GPIO_RST_OFFSET;
515 else
516 reg = MT6391_GPIO_DIR_BASE + pos + GPIO_SET_OFFSET;
517
518 if (pwrap_write(reg, 1L << bit) != 0)
519 return -1;
520
521 return 0;
522}
523
524void mt6391_gpio_set_pull(u32 pin, enum mt6391_pull_enable enable,
525 enum mt6391_pull_select select)
526{
527 u16 pos;
528 u16 bit;
529 u16 en_reg, sel_reg;
530
531 assert(pin <= MAX_MT6391_GPIO);
532
533 pos_bit_calc(pin, &pos, &bit);
534
535 if (enable == MT6391_GPIO_PULL_DISABLE) {
536 en_reg = MT6391_GPIO_PULLEN_BASE + pos + GPIO_RST_OFFSET;
537 } else {
538 en_reg = MT6391_GPIO_PULLEN_BASE + pos + GPIO_SET_OFFSET;
539 sel_reg = (select == MT6391_GPIO_PULL_DOWN) ?
540 (MT6391_GPIO_PULLSEL_BASE + pos + GPIO_RST_OFFSET) :
541 (MT6391_GPIO_PULLSEL_BASE + pos + GPIO_SET_OFFSET);
542 pwrap_write(sel_reg, 1L << bit);
543 }
544 pwrap_write(en_reg, 1L << bit);
545}
546
547int mt6391_gpio_get(u32 pin)
548{
549 u16 pos;
550 u16 bit;
551 u16 reg;
552 u16 data;
553
554 assert(pin <= MAX_MT6391_GPIO);
555
556 pos_bit_calc(pin, &pos, &bit);
557
558 reg = MT6391_GPIO_DIN_BASE + pos;
559 pwrap_read(reg, &data);
560
561 return (data & (1L << bit)) ? 1 : 0;
562}
563
564void mt6391_gpio_set(u32 pin, int output)
565{
566 u16 pos;
567 u16 bit;
568 u16 reg;
569
570 assert(pin <= MAX_MT6391_GPIO);
571
572 pos_bit_calc(pin, &pos, &bit);
573
574 if (output == 0)
575 reg = MT6391_GPIO_DOUT_BASE + pos + GPIO_RST_OFFSET;
576 else
577 reg = MT6391_GPIO_DOUT_BASE + pos + GPIO_SET_OFFSET;
578
579 pwrap_write(reg, 1L << bit);
580}
581
582void mt6391_gpio_set_mode(u32 pin, int mode)
583{
584 u16 pos;
585 u16 bit;
586 u16 mask = (1L << GPIO_MODE_BITS) - 1;
587
588 assert(pin <= MAX_MT6391_GPIO);
589
590 pos_bit_calc_mode(pin, &pos, &bit);
591 mt6391_write(MT6391_GPIO_MODE_BASE + pos, mode, mask, bit);
592}
593
594void mt6391_gpio_input_pulldown(u32 gpio)
595{
596 mt6391_gpio_set_pull(gpio, MT6391_GPIO_PULL_ENABLE,
597 MT6391_GPIO_PULL_DOWN);
598 mt6391_gpio_set_dir(gpio, MT6391_GPIO_DIRECTION_IN);
599 mt6391_gpio_set_mode(gpio, MT6391_GPIO_MODE);
600}
601
602void mt6391_gpio_input_pullup(u32 gpio)
603{
604 mt6391_gpio_set_pull(gpio, MT6391_GPIO_PULL_ENABLE,
605 MT6391_GPIO_PULL_UP);
606 mt6391_gpio_set_dir(gpio, MT6391_GPIO_DIRECTION_IN);
607 mt6391_gpio_set_mode(gpio, MT6391_GPIO_MODE);
608}
609
610void mt6391_gpio_input(u32 gpio)
611{
612 mt6391_gpio_set_pull(gpio, MT6391_GPIO_PULL_DISABLE,
613 MT6391_GPIO_PULL_DOWN);
614 mt6391_gpio_set_dir(gpio, MT6391_GPIO_DIRECTION_IN);
615 mt6391_gpio_set_mode(gpio, MT6391_GPIO_MODE);
616}
617
618void mt6391_gpio_output(u32 gpio, int value)
619{
620 mt6391_gpio_set_pull(gpio, MT6391_GPIO_PULL_DISABLE,
621 MT6391_GPIO_PULL_DOWN);
622 mt6391_gpio_set(gpio, value);
623 mt6391_gpio_set_dir(gpio, MT6391_GPIO_DIRECTION_OUT);
624 mt6391_gpio_set_mode(gpio, MT6391_GPIO_MODE);
625}