Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * Copyright (C) 2014 Google Inc. |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 6 | * Copyright (C) 2015 Intel Corporation. |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | #include <console/console.h> |
| 19 | #include <delay.h> |
| 20 | #include <arch/io.h> |
| 21 | #include <device/device.h> |
| 22 | #include <device/pci.h> |
| 23 | #include <device/pci_def.h> |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 24 | #include <soc/pch.h> |
| 25 | #include <soc/pci_devs.h> |
| 26 | #include <soc/ramstage.h> |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 27 | #include <soc/spi.h> |
| 28 | |
| 29 | u8 pch_revision(void) |
| 30 | { |
| 31 | return pci_read_config8(PCH_DEV_LPC, PCI_REVISION_ID); |
| 32 | } |
| 33 | |
| 34 | u16 pch_type(void) |
| 35 | { |
| 36 | return pci_read_config16(PCH_DEV_LPC, PCI_DEVICE_ID); |
| 37 | } |
| 38 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 39 | void *get_spi_bar(void) |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 40 | { |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 41 | device_t dev = PCH_DEV_SPI; |
| 42 | uint32_t bar; |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 43 | |
Lee Leahy | f45eb06 | 2015-09-17 11:50:39 -0700 | [diff] [blame] | 44 | bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0); |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 45 | /* Bits 31-12 are the base address as per EDS for SPI 1F/5, |
| 46 | * Don't care about 0-11 bit |
| 47 | */ |
Lee Leahy | f45eb06 | 2015-09-17 11:50:39 -0700 | [diff] [blame] | 48 | return (void *)(bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK); |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 49 | } |
| 50 | |
| 51 | u32 pch_read_soft_strap(int id) |
| 52 | { |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 53 | uint32_t fdoc; |
| 54 | void *spibar = get_spi_bar(); |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 55 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 56 | fdoc = read32(spibar + SPIBAR_FDOC); |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 57 | fdoc &= ~0x00007ffc; |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 58 | write32(spibar + SPIBAR_FDOC, fdoc); |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 59 | |
| 60 | fdoc |= 0x00004000; |
| 61 | fdoc |= id * 4; |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 62 | write32(spibar + SPIBAR_FDOC, fdoc); |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 63 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 64 | return read32(spibar + SPIBAR_FDOD); |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 65 | } |
| 66 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 67 | #if ENV_RAMSTAGE |
| 68 | void pch_enable_dev(device_t dev) |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 69 | { |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 70 | /* FSP should implement routines to disable PCH IPs */ |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 71 | u32 reg32; |
| 72 | |
| 73 | /* These devices need special enable/disable handling */ |
| 74 | switch (PCI_SLOT(dev->path.pci.devfn)) { |
| 75 | case PCH_DEV_SLOT_PCIE: |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 76 | return; |
| 77 | } |
| 78 | |
| 79 | if (!dev->enabled) { |
| 80 | printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); |
| 81 | |
| 82 | /* Ensure memory, io, and bus master are all disabled */ |
| 83 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 84 | reg32 &= ~(PCI_COMMAND_MASTER | |
| 85 | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); |
| 86 | pci_write_config32(dev, PCI_COMMAND, reg32); |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 87 | } else { |
| 88 | /* Enable SERR */ |
| 89 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 90 | reg32 |= PCI_COMMAND_SERR; |
| 91 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 92 | } |
| 93 | } |
| 94 | |
| 95 | #endif |