Patrick Georgi | be61a17 | 2010-12-18 07:48:43 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * Copyright (C) 2009-2010 iWave Systems |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
Uwe Hermann | 405721d | 2010-12-18 13:22:37 +0000 | [diff] [blame] | 9 | * published by the Free Software Foundation; version 2 of the License. |
Patrick Georgi | be61a17 | 2010-12-18 07:48:43 +0000 | [diff] [blame] | 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Patrick Georgi | be61a17 | 2010-12-18 07:48:43 +0000 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <console/console.h> |
| 18 | #include <device/device.h> |
| 19 | #include <device/pci.h> |
| 20 | #include <device/pci_ids.h> |
| 21 | #include <arch/io.h> |
Patrick Georgi | 2c2e78d | 2012-02-16 18:54:37 +0100 | [diff] [blame] | 22 | #include <arch/ioapic.h> |
Vladimir Serbinenko | e6e5b5e | 2014-08-31 02:21:43 +0200 | [diff] [blame] | 23 | #include <arch/acpigen.h> |
| 24 | #include <arch/acpigen.h> |
| 25 | #include <cpu/cpu.h> |
| 26 | #include <cbmem.h> |
| 27 | #include <string.h> |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 28 | #include <drivers/intel/gma/i915.h> |
Vladimir Serbinenko | e6e5b5e | 2014-08-31 02:21:43 +0200 | [diff] [blame] | 29 | #include "nvs.h" |
Patrick Georgi | be61a17 | 2010-12-18 07:48:43 +0000 | [diff] [blame] | 30 | #include "chip.h" |
| 31 | |
Uwe Hermann | 405721d | 2010-12-18 13:22:37 +0000 | [diff] [blame] | 32 | /* SCH LPC defines */ |
| 33 | #define SCH_ACPI_CTL 0x58 |
| 34 | #define SCH_SIRQ_CTL 0x68 |
| 35 | #define PIRQA_ROUT 0x60 |
| 36 | #define PIRQB_ROUT 0x61 |
| 37 | #define PIRQC_ROUT 0x62 |
| 38 | #define PIRQD_ROUT 0x63 |
| 39 | #define PIRQE_ROUT 0x64 |
| 40 | #define PIRQF_ROUT 0x65 |
| 41 | #define PIRQG_ROUT 0x66 |
| 42 | #define PIRQH_ROUT 0x67 |
Patrick Georgi | be61a17 | 2010-12-18 07:48:43 +0000 | [diff] [blame] | 43 | |
Stefan Reinauer | 4bab6e7 | 2016-05-03 15:53:33 -0700 | [diff] [blame] | 44 | typedef struct soc_intel_sch_config config_t; |
Patrick Georgi | be61a17 | 2010-12-18 07:48:43 +0000 | [diff] [blame] | 45 | |
| 46 | /* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control |
| 47 | * 0x00 - 0000 = Reserved |
| 48 | * 0x01 - 0001 = Reserved |
| 49 | * 0x02 - 0010 = Reserved |
| 50 | * 0x03 - 0011 = IRQ3 |
| 51 | * 0x04 - 0100 = IRQ4 |
| 52 | * 0x05 - 0101 = IRQ5 |
| 53 | * 0x06 - 0110 = IRQ6 |
| 54 | * 0x07 - 0111 = IRQ7 |
| 55 | * 0x08 - 1000 = Reserved |
| 56 | * 0x09 - 1001 = IRQ9 |
| 57 | * 0x0A - 1010 = IRQ10 |
| 58 | * 0x0B - 1011 = IRQ11 |
| 59 | * 0x0C - 1100 = IRQ12 |
| 60 | * 0x0D - 1101 = Reserved |
| 61 | * 0x0E - 1110 = IRQ14 |
| 62 | * 0x0F - 1111 = IRQ15 |
| 63 | * PIRQ[n]_ROUT[7] - PIRQ Routing Control |
| 64 | * 0x80 - The PIRQ is not routed. |
| 65 | */ |
| 66 | |
| 67 | #define PIRQA 0x03 |
| 68 | #define PIRQB 0x05 |
| 69 | #define PIRQC 0x06 |
| 70 | #define PIRQD 0x07 |
| 71 | #define PIRQE 0x09 |
| 72 | #define PIRQF 0x0A |
| 73 | #define PIRQG 0x0B |
| 74 | #define PIRQH 0x0C |
Uwe Hermann | 405721d | 2010-12-18 13:22:37 +0000 | [diff] [blame] | 75 | |
Patrick Georgi | be61a17 | 2010-12-18 07:48:43 +0000 | [diff] [blame] | 76 | static void sch_pirq_init(device_t dev) |
| 77 | { |
| 78 | device_t irq_dev; |
Uwe Hermann | 405721d | 2010-12-18 13:22:37 +0000 | [diff] [blame] | 79 | |
Patrick Georgi | be61a17 | 2010-12-18 07:48:43 +0000 | [diff] [blame] | 80 | /* Get the chip configuration */ |
| 81 | config_t *config = dev->chip_info; |
| 82 | |
| 83 | pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing); |
| 84 | pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing); |
| 85 | pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing); |
| 86 | pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing); |
| 87 | |
| 88 | pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing); |
| 89 | pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing); |
| 90 | pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing); |
| 91 | pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing); |
| 92 | |
| 93 | /* Eric Biederman once said we should let the OS do this. |
| 94 | * I am not so sure anymore he was right. |
| 95 | */ |
| 96 | |
Uwe Hermann | 405721d | 2010-12-18 13:22:37 +0000 | [diff] [blame] | 97 | for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { |
| 98 | u8 int_pin = 0, int_line = 0; |
Patrick Georgi | be61a17 | 2010-12-18 07:48:43 +0000 | [diff] [blame] | 99 | |
| 100 | if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) |
| 101 | continue; |
| 102 | |
| 103 | int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); |
| 104 | |
Uwe Hermann | 405721d | 2010-12-18 13:22:37 +0000 | [diff] [blame] | 105 | switch (int_pin) { |
| 106 | case 1: /* INTA# */ |
| 107 | int_line = config->pirqa_routing; |
| 108 | break; |
| 109 | case 2: /* INTB# */ |
| 110 | int_line = config->pirqb_routing; |
| 111 | break; |
| 112 | case 3: /* INTC# */ |
| 113 | int_line = config->pirqc_routing; |
| 114 | break; |
| 115 | case 4: /* INTD# */ |
| 116 | int_line = config->pirqd_routing; |
| 117 | break; |
Patrick Georgi | be61a17 | 2010-12-18 07:48:43 +0000 | [diff] [blame] | 118 | } |
| 119 | |
| 120 | if (!int_line) |
| 121 | continue; |
| 122 | |
| 123 | pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); |
| 124 | } |
| 125 | } |
Uwe Hermann | 405721d | 2010-12-18 13:22:37 +0000 | [diff] [blame] | 126 | |
Patrick Georgi | be61a17 | 2010-12-18 07:48:43 +0000 | [diff] [blame] | 127 | static void sch_fixups(struct device *dev) |
| 128 | { |
Uwe Hermann | 405721d | 2010-12-18 13:22:37 +0000 | [diff] [blame] | 129 | u32 rcba_base; |
| 130 | |
| 131 | /* This needs to happen after PCI enumeration. */ |
| 132 | /* RCBA32(0x1d40) |= 1; */ |
Patrick Georgi | be61a17 | 2010-12-18 07:48:43 +0000 | [diff] [blame] | 133 | rcba_base = pci_read_config32(dev, 0xF0); |
Uwe Hermann | 405721d | 2010-12-18 13:22:37 +0000 | [diff] [blame] | 134 | |
| 135 | /* Remove the enable bit. */ |
Patrick Georgi | be61a17 | 2010-12-18 07:48:43 +0000 | [diff] [blame] | 136 | rcba_base = rcba_base >> 1; |
| 137 | rcba_base = rcba_base << 1; |
| 138 | *((volatile u32 *)(rcba_base +0x104)) &= 0xFF00FFFF; |
| 139 | } |
| 140 | |
| 141 | static void lpc_init(struct device *dev) |
| 142 | { |
| 143 | printk(BIOS_DEBUG, "SCH: lpc_init\n"); |
| 144 | |
| 145 | /* Setup the PIRQ. */ |
| 146 | sch_pirq_init(dev); |
| 147 | pci_write_config8(dev, SCH_SIRQ_CTL,0x80); |
| 148 | sch_fixups(dev); |
| 149 | } |
| 150 | |
| 151 | static void sch_lpc_read_resources(device_t dev) |
| 152 | { |
| 153 | struct resource *res; |
| 154 | |
| 155 | /* Get the normal PCI resources of this device. */ |
| 156 | pci_dev_read_resources(dev); |
| 157 | |
| 158 | /* Add an extra subtractive resource for both memory and I/O. */ |
| 159 | res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); |
| 160 | res->base = 0; |
| 161 | res->size = 0xe000; |
| 162 | res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | |
| 163 | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 164 | |
| 165 | res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); |
| 166 | res->base = 0xff800000; |
| 167 | res->size = 0x00800000; /* 8 MB for flash */ |
| 168 | res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | |
| 169 | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 170 | |
Patrick Georgi | 2c2e78d | 2012-02-16 18:54:37 +0100 | [diff] [blame] | 171 | res = new_resource(dev, 3); |
| 172 | res->base = IO_APIC_ADDR; |
Patrick Georgi | be61a17 | 2010-12-18 07:48:43 +0000 | [diff] [blame] | 173 | res->size = 0x00001000; |
| 174 | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 175 | } |
| 176 | |
| 177 | static void set_subsystem(device_t dev, unsigned vendor, unsigned device) |
| 178 | { |
| 179 | if (!vendor || !device) { |
| 180 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 181 | pci_read_config32(dev, PCI_VENDOR_ID)); |
| 182 | } else { |
| 183 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 184 | ((device & 0xffff) << 16) | (vendor & 0xffff)); |
| 185 | } |
| 186 | } |
| 187 | |
Alexander Couzens | a90dad1 | 2015-04-12 21:49:46 +0200 | [diff] [blame] | 188 | static void southbridge_inject_dsdt(device_t dev) |
Vladimir Serbinenko | e6e5b5e | 2014-08-31 02:21:43 +0200 | [diff] [blame] | 189 | { |
| 190 | global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); |
| 191 | |
| 192 | if (gnvs) { |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 193 | const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); |
Vladimir Serbinenko | e6e5b5e | 2014-08-31 02:21:43 +0200 | [diff] [blame] | 194 | memset(gnvs, 0, sizeof(*gnvs)); |
| 195 | acpi_create_gnvs(gnvs); |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 196 | |
| 197 | gnvs->ndid = gfx->ndid; |
| 198 | memcpy(gnvs->did, gfx->did, sizeof(gnvs->did)); |
| 199 | |
Vladimir Serbinenko | e6e5b5e | 2014-08-31 02:21:43 +0200 | [diff] [blame] | 200 | /* And tell SMI about it */ |
| 201 | smm_setup_structures(gnvs, NULL, NULL); |
| 202 | |
| 203 | /* Add it to SSDT. */ |
Vladimir Serbinenko | d1069e0 | 2014-11-04 21:21:42 +0100 | [diff] [blame] | 204 | acpigen_write_scope("\\"); |
| 205 | acpigen_write_name_dword("NVSA", (u32) gnvs); |
| 206 | acpigen_pop_len(); |
Vladimir Serbinenko | e6e5b5e | 2014-08-31 02:21:43 +0200 | [diff] [blame] | 207 | } |
| 208 | } |
| 209 | |
Patrick Georgi | be61a17 | 2010-12-18 07:48:43 +0000 | [diff] [blame] | 210 | static struct pci_operations pci_ops = { |
| 211 | .set_subsystem = set_subsystem, |
| 212 | }; |
| 213 | |
| 214 | static struct device_operations device_ops = { |
| 215 | .read_resources = sch_lpc_read_resources, |
| 216 | .set_resources = pci_dev_set_resources, |
| 217 | .enable_resources = pci_dev_enable_resources, |
Vladimir Serbinenko | e6e5b5e | 2014-08-31 02:21:43 +0200 | [diff] [blame] | 218 | .acpi_inject_dsdt_generator = southbridge_inject_dsdt, |
| 219 | .write_acpi_tables = acpi_write_hpet, |
Patrick Georgi | be61a17 | 2010-12-18 07:48:43 +0000 | [diff] [blame] | 220 | .init = lpc_init, |
Kyösti Mälkki | d0e212c | 2015-02-26 20:47:47 +0200 | [diff] [blame] | 221 | .scan_bus = scan_lpc_bus, |
Patrick Georgi | be61a17 | 2010-12-18 07:48:43 +0000 | [diff] [blame] | 222 | .ops_pci = &pci_ops, |
| 223 | }; |
| 224 | |
| 225 | /* SCH LPC Interface */ |
| 226 | static const struct pci_driver sch_lpc __pci_driver = { |
| 227 | .ops = &device_ops, |
| 228 | .vendor = PCI_VENDOR_ID_INTEL, |
| 229 | .device = 0x8119, |
| 230 | }; |