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Patrick Georgibe61a172010-12-18 07:48:43 +00001/*
2 * This file is part of the coreboot project.
3 *
Stefan Reinauer4bab6e72016-05-03 15:53:33 -07004 * Copyright (C) 2007-2008 coresystems GmbH
5 * 2012 secunet Security Networks AG
Patrick Georgibe61a172010-12-18 07:48:43 +00006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Patrick Georgibe61a172010-12-18 07:48:43 +000015 */
16
Stefan Reinauer4bab6e72016-05-03 15:53:33 -070017#ifndef SOC_INTEL_SCH_CHIP_H
18#define SOC_INTEL_SCH_CHIP_H
Patrick Georgibe61a172010-12-18 07:48:43 +000019
Stefan Reinauer4bab6e72016-05-03 15:53:33 -070020#include <drivers/intel/gma/i915.h>
21
22struct soc_intel_sch_config {
23 struct i915_gpu_controller_info gfx;
24
Patrick Georgibe61a172010-12-18 07:48:43 +000025 /**
26 * Interrupt Routing configuration
27 * If bit7 is 1, the interrupt is disabled.
28 */
29 uint8_t pirqa_routing;
30 uint8_t pirqb_routing;
31 uint8_t pirqc_routing;
32 uint8_t pirqd_routing;
33 uint8_t pirqe_routing;
34 uint8_t pirqf_routing;
35 uint8_t pirqg_routing;
36 uint8_t pirqh_routing;
37};
38
Stefan Reinauer4bab6e72016-05-03 15:53:33 -070039#endif /* SOC_INTEL_SCH_CHIP_H */