| Lee Leahy | ce9e21a | 2016-06-05 18:48:31 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com> |
| 5 | * Copyright (C) 2007-2008 coresystems GmbH |
| 6 | * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. |
| 7 | * Copyright (C) 2015-2016 Intel Corporation |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; version 2 of the License. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * Replacement for cache_as_ram.inc when using the C environment boot block. |
| 19 | */ |
| 20 | |
| 21 | #include <rules.h> |
| 22 | #include <soc/sd.h> |
| 23 | |
| 24 | .section ".text" |
| 25 | .global car_stage_entry |
| 26 | |
| 27 | car_stage_entry: |
| 28 | |
| 29 | /* Enter the C code */ |
| Lee Leahy | 0c1843a | 2016-07-20 08:41:52 -0700 | [diff] [blame] | 30 | call car_stage_c_entry |
| Lee Leahy | ce9e21a | 2016-06-05 18:48:31 -0700 | [diff] [blame] | 31 | |
| Lee Leahy | 102f625 | 2016-07-25 07:41:54 -0700 | [diff] [blame] | 32 | #if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) |
| Lee Leahy | ce9e21a | 2016-06-05 18:48:31 -0700 | [diff] [blame] | 33 | #if !ENV_VERSTAGE |
| 34 | #include "src/drivers/intel/fsp1_1/after_raminit.S" |
| 35 | #endif |
| Lee Leahy | 102f625 | 2016-07-25 07:41:54 -0700 | [diff] [blame] | 36 | #endif |
| Lee Leahy | ce9e21a | 2016-06-05 18:48:31 -0700 | [diff] [blame] | 37 | |
| 38 | /* The code should never reach this point */ |
| 39 | movb $0x69, %ah |
| 40 | jmp .Lhlt |
| 41 | |
| 42 | #---------------------------------------------------------------------------- |
| 43 | # |
| 44 | # Procedure: .Lhlt |
| 45 | # |
| 46 | # Input: ah - Upper 8-bits of POST code |
| 47 | # al - Lower 8-bits of POST code |
| 48 | # |
| 49 | # Description: |
| 50 | # Infinite loop displaying alternating POST code values |
| 51 | # |
| 52 | #---------------------------------------------------------------------------- |
| 53 | |
| 54 | #define FLASH_DELAY 0x1000 /* I/O delay between post codes on failure */ |
| 55 | #define POST_DELAY 0x50 |
| 56 | |
| 57 | .Lhlt: |
| 58 | xchg %al, %ah |
| 59 | mov $POST_DELAY, %dh |
| 60 | #if IS_ENABLED(CONFIG_POST_IO) |
| 61 | outb %al, $CONFIG_POST_IO_PORT |
| 62 | #else |
| 63 | post_code(POST_DEAD_CODE) |
| 64 | #endif |
| 65 | .flash_setup: |
| 66 | movl $FLASH_DELAY, %ecx |
| 67 | .flash_delay: |
| 68 | outb %al, $0xED |
| 69 | loop .flash_delay |
| 70 | #if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED) |
| 71 | movl $SD_HOST_CTRL, %ebx |
| 72 | movb 0(%ebx), %dl |
| 73 | xorb $1, %dl |
| 74 | movb %dl, 0(%ebx) |
| 75 | #endif /* CONFIG_ENABLE_DEBUG_LED */ |
| 76 | decb %dh |
| 77 | jnz .flash_setup |
| 78 | jmp .Lhlt |