York Yang | d7cba28 | 2016-03-09 10:54:26 -0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * Copyright (C) 2013 Google Inc. |
| 6 | * Copyright (C) 2015-2016 Intel Corp. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | */ |
| 17 | |
| 18 | #include <stdint.h> |
| 19 | #include <arch/io.h> |
| 20 | #include <arch/ioapic.h> |
| 21 | #include <console/console.h> |
| 22 | #include <device/device.h> |
| 23 | #include <device/pci.h> |
| 24 | #include <device/pci_ids.h> |
| 25 | #include <device/pci_def.h> |
| 26 | #include <pc80/mc146818rtc.h> |
| 27 | #include <pc80/i8254.h> |
| 28 | #include <pc80/i8259.h> |
| 29 | #include <pc80/isa-dma.h> |
| 30 | #include <romstage_handoff.h> |
| 31 | #include <soc/iomap.h> |
| 32 | #include <soc/irq.h> |
| 33 | #include <soc/lpc.h> |
| 34 | #include <soc/pci_devs.h> |
| 35 | #include <soc/ramstage.h> |
| 36 | #include <chip.h> |
| 37 | |
| 38 | typedef struct soc_intel_fsp_broadwell_de_config config_t; |
| 39 | |
| 40 | static inline void |
| 41 | add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size) |
| 42 | { |
| 43 | mmio_resource(dev, i, addr >> 10, size >> 10); |
| 44 | } |
| 45 | |
| 46 | static void sc_add_mmio_resources(device_t dev) |
| 47 | { |
| 48 | add_mmio_resource(dev, 0xfeb0, |
| 49 | ABORT_BASE_ADDRESS, |
| 50 | ABORT_BASE_SIZE); |
| 51 | add_mmio_resource(dev, 0xfeb8, |
| 52 | PSEG_BASE_ADDRESS, |
| 53 | PSEG_BASE_SIZE); |
| 54 | add_mmio_resource(dev, 0xfec0, |
| 55 | IOXAPIC1_BASE_ADDRESS, |
| 56 | IOXAPIC1_BASE_SIZE); |
| 57 | add_mmio_resource(dev, 0xfec1, |
| 58 | IOXAPIC2_BASE_ADDRESS, |
| 59 | IOXAPIC2_BASE_SIZE); |
| 60 | add_mmio_resource(dev, 0xfed0, |
| 61 | PCH_BASE_ADDRESS, |
| 62 | PCH_BASE_SIZE); |
| 63 | add_mmio_resource(dev, 0xfee0, |
| 64 | LXAPIC_BASE_ADDRESS, |
| 65 | LXAPIC_BASE_SIZE); |
| 66 | add_mmio_resource(dev, 0xff00, |
| 67 | FIRMWARE_BASE_ADDRESS, |
| 68 | FIRMWARE_BASE_SIZE); |
| 69 | } |
| 70 | |
| 71 | /* |
| 72 | * Write PCI config space IRQ assignments. PCI devices have the INT_LINE |
| 73 | * (0x3C) and INT_PIN (0x3D) registers which report interrupt routing |
| 74 | * information to operating systems and drivers. The INT_PIN register is |
| 75 | * generally read only and reports which interrupt pin A - D it uses. The |
| 76 | * INT_LINE register is configurable and reports which IRQ (generally the |
| 77 | * PIC IRQs 1 - 15) it will use. This needs to take interrupt pin swizzling |
| 78 | * on devices that are downstream on a PCI bridge into account. |
| 79 | * |
| 80 | * This function will loop through all enabled PCI devices and program the |
| 81 | * INT_LINE register with the correct PIC IRQ number for the INT_PIN that it |
| 82 | * uses. It then configures each interrupt in the pic to be level triggered. |
| 83 | */ |
| 84 | static void write_pci_config_irqs(void) |
| 85 | { |
| 86 | device_t irq_dev; |
| 87 | device_t targ_dev; |
| 88 | uint8_t int_line = 0; |
| 89 | uint8_t original_int_pin = 0; |
| 90 | uint8_t new_int_pin = 0; |
| 91 | uint16_t current_bdf = 0; |
| 92 | uint16_t parent_bdf = 0; |
| 93 | uint8_t pirq = 0; |
| 94 | uint8_t device_num = 0; |
| 95 | const struct broadwell_de_irq_route *ir = &global_broadwell_de_irq_route; |
| 96 | |
| 97 | if (ir == NULL) { |
| 98 | printk(BIOS_WARNING, "Warning: Can't write PCI IRQ assignments because" |
| 99 | " 'global_broadwell_de_irq_route' structure does not exist\n"); |
| 100 | return; |
| 101 | } |
| 102 | |
| 103 | /* |
| 104 | * Loop through all enabled devices and program their |
| 105 | * INT_LINE, INT_PIN registers from values taken from |
| 106 | * the Interrupt Route registers in the ILB |
| 107 | */ |
| 108 | printk(BIOS_DEBUG, "PCI_CFG IRQ: Write PCI config space IRQ assignments\n"); |
| 109 | for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { |
| 110 | |
| 111 | if ((irq_dev->path.type != DEVICE_PATH_PCI) || |
| 112 | (!irq_dev->enabled)) |
| 113 | continue; |
| 114 | |
| 115 | current_bdf = irq_dev->path.pci.devfn | |
| 116 | irq_dev->bus->secondary << 8; |
| 117 | |
| 118 | /* |
| 119 | * Step 1: Get the INT_PIN and device structure to look for |
| 120 | * in the pirq_data table defined in the mainboard directory. |
| 121 | */ |
| 122 | targ_dev = NULL; |
| 123 | new_int_pin = get_pci_irq_pins(irq_dev, &targ_dev); |
| 124 | if (targ_dev == NULL || new_int_pin < 1) |
| 125 | continue; |
| 126 | |
| 127 | /* Get the original INT_PIN for record keeping */ |
| 128 | original_int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); |
| 129 | |
| 130 | parent_bdf = targ_dev->path.pci.devfn |
| 131 | | targ_dev->bus->secondary << 8; |
| 132 | device_num = PCI_SLOT(parent_bdf); |
| 133 | |
| 134 | if (ir->pcidev[device_num] == 0) { |
| 135 | printk(BIOS_WARNING, |
| 136 | "Warning: PCI Device %d does not have an IRQ entry, skipping it\n", |
| 137 | device_num); |
| 138 | continue; |
| 139 | } |
| 140 | |
| 141 | /* Find the PIRQ that is attached to the INT_PIN this device uses */ |
| 142 | pirq = (ir->pcidev[device_num] >> ((new_int_pin - 1) * 4)) & 0xF; |
| 143 | |
| 144 | /* Get the INT_LINE this device/function will use */ |
| 145 | int_line = ir->pic[pirq]; |
| 146 | |
| 147 | if (int_line != PIRQ_PIC_IRQDISABLE) { |
| 148 | /* Set this IRQ to level triggered since it is used by a PCI device */ |
| 149 | i8259_configure_irq_trigger(int_line, IRQ_LEVEL_TRIGGERED); |
| 150 | /* Set the Interrupt Line register in PCI config space */ |
| 151 | pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); |
| 152 | } else { |
| 153 | /* Set the Interrupt line register as "unknown or unused" */ |
| 154 | pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, |
| 155 | PIRQ_PIC_UNKNOWN_UNUSED); |
| 156 | } |
| 157 | |
| 158 | printk(BIOS_SPEW, "\tINT_PIN\t\t: %d (%s)\n", |
| 159 | original_int_pin, pin_to_str(original_int_pin)); |
| 160 | if (parent_bdf != current_bdf) |
| 161 | printk(BIOS_SPEW, "\tSwizzled to\t: %d (%s)\n", |
| 162 | new_int_pin, pin_to_str(new_int_pin)); |
| 163 | printk(BIOS_SPEW, "\tPIRQ\t\t: %c\n" |
| 164 | "\tINT_LINE\t: 0x%X (IRQ %d)\n", |
| 165 | 'A' + pirq, int_line, int_line); |
| 166 | } |
| 167 | printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space IRQ assignments\n"); |
| 168 | } |
| 169 | |
| 170 | static void sc_pirq_init(device_t dev) |
| 171 | { |
| 172 | int i; |
| 173 | const uint8_t *pirq = global_broadwell_de_irq_route.pic; |
| 174 | printk(BIOS_DEBUG, "Programming PIRQ[A-H] Routing Control Register\n"); |
| 175 | |
| 176 | for (i = 0; i < 8; i++) { |
| 177 | pci_write_config8(dev, (i < 4) ? (PIRQ_RCR1+i) : (PIRQ_RCR2+i-4), pirq[i]); |
| 178 | printk(BIOS_DEBUG, " PIRQ[%c]: %.2x\n" |
| 179 | , 'A'+i |
| 180 | , pci_read_config8(dev, (i < 4) ? (PIRQ_RCR1+i) : (PIRQ_RCR2+i-4)) |
| 181 | ); |
| 182 | } |
| 183 | } |
| 184 | |
| 185 | static void sc_add_io_resources(device_t dev) |
| 186 | { |
| 187 | struct resource *res; |
| 188 | u8 io_index = 0; |
| 189 | |
| 190 | /* |
| 191 | * Add the default claimed IO range for the LPC device |
| 192 | * and mark it as subtractive decode. |
| 193 | */ |
| 194 | res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0)); |
| 195 | res->base = LPC_DEFAULT_IO_RANGE_LOWER; |
| 196 | res->size = LPC_DEFAULT_IO_RANGE_UPPER - LPC_DEFAULT_IO_RANGE_LOWER; |
| 197 | res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | |
| 198 | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 199 | } |
| 200 | |
| 201 | static void sc_read_resources(device_t dev) |
| 202 | { |
| 203 | pci_dev_read_resources(dev); |
| 204 | sc_add_mmio_resources(dev); |
| 205 | sc_add_io_resources(dev); |
| 206 | } |
| 207 | |
| 208 | static void sc_init(struct device *dev) |
| 209 | { |
| 210 | printk(BIOS_DEBUG, "soc: southcluster_init\n"); |
| 211 | |
| 212 | /* Set the value for PCI command register. */ |
| 213 | pci_write_config16(dev, PCI_COMMAND, |
| 214 | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | |
| 215 | PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); |
| 216 | |
| 217 | /* Program Serial IRQ register. */ |
Werner Zeh | 4f2754c | 2016-09-12 07:48:51 +0200 | [diff] [blame] | 218 | pci_write_config8(dev, SIRQ_CNTL, SIRQ_EN | SIRQ_MODE_CONT); |
| 219 | if (!IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)) { |
| 220 | /* If SERIRQ have to operate in quiet mode, it should have been |
| 221 | run in continuous mode for at least one frame first. Use I/O |
| 222 | access to achieve the delay of at least one LPC cycle. */ |
| 223 | outb(inb(0x80), 0x80); |
| 224 | pci_write_config8(dev, SIRQ_CNTL, SIRQ_EN | SIRQ_MODE_QUIET); |
| 225 | } |
York Yang | d7cba28 | 2016-03-09 10:54:26 -0800 | [diff] [blame] | 226 | |
| 227 | sc_pirq_init(dev); |
| 228 | write_pci_config_irqs(); |
| 229 | isa_dma_init(); |
| 230 | setup_i8259(); |
| 231 | setup_i8254(); |
| 232 | } |
| 233 | |
| 234 | /* |
| 235 | * Common code for the south cluster devices. |
| 236 | */ |
| 237 | void southcluster_enable_dev(device_t dev) |
| 238 | { |
| 239 | uint32_t reg32; |
| 240 | |
| 241 | if (!dev->enabled) { |
| 242 | int slot = PCI_SLOT(dev->path.pci.devfn); |
| 243 | int func = PCI_FUNC(dev->path.pci.devfn); |
| 244 | printk(BIOS_DEBUG, "%s: Disabling device: %02x.%01x\n", |
| 245 | dev_path(dev), slot, func); |
| 246 | |
| 247 | /* Ensure memory, io, and bus master are all disabled */ |
| 248 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 249 | reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); |
| 250 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 251 | } |
| 252 | } |
| 253 | |
| 254 | static struct device_operations device_ops = { |
| 255 | .read_resources = sc_read_resources, |
| 256 | .set_resources = pci_dev_set_resources, |
| 257 | .enable_resources = NULL, |
| 258 | .init = sc_init, |
| 259 | .enable = southcluster_enable_dev, |
| 260 | .scan_bus = scan_lpc_bus, |
| 261 | .ops_pci = &soc_pci_ops, |
| 262 | }; |
| 263 | |
| 264 | static const struct pci_driver southcluster __pci_driver = { |
| 265 | .ops = &device_ops, |
| 266 | .vendor = PCI_VENDOR_ID_INTEL, |
| 267 | .device = LPC_DEVID, |
| 268 | }; |
| 269 | |
| 270 | static const struct pci_driver southcluster_es2 __pci_driver = { |
| 271 | .ops = &device_ops, |
| 272 | .vendor = PCI_VENDOR_ID_INTEL, |
| 273 | .device = LPC_DEVID_ES2, |
| 274 | }; |