York Yang | d7cba28 | 2016-03-09 10:54:26 -0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
| 5 | * Copyright (C) 2015-2016 Intel Corp. |
Werner Zeh | 1cfb555 | 2016-07-27 08:22:50 +0200 | [diff] [blame] | 6 | * Copyright (C) 2016 Siemens AG |
York Yang | d7cba28 | 2016-03-09 10:54:26 -0800 | [diff] [blame] | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | */ |
| 17 | |
| 18 | #include <arch/acpi.h> |
| 19 | #include <console/console.h> |
| 20 | #include <cpu/x86/lapic.h> |
| 21 | #include <device/device.h> |
| 22 | #include <device/pci.h> |
| 23 | #include <device/pci_ids.h> |
| 24 | #include <drivers/intel/fsp1_0/fsp_util.h> |
| 25 | #include <soc/iomap.h> |
| 26 | #include <soc/pci_devs.h> |
| 27 | #include <soc/ramstage.h> |
Werner Zeh | 1cfb555 | 2016-07-27 08:22:50 +0200 | [diff] [blame] | 28 | #include <soc/acpi.h> |
York Yang | d7cba28 | 2016-03-09 10:54:26 -0800 | [diff] [blame] | 29 | |
| 30 | static const int legacy_hole_base_k = 0xa0000 / 1024; |
| 31 | static const int legacy_hole_size_k = 384; |
| 32 | |
| 33 | static int add_fixed_resources(struct device *dev, int index) |
| 34 | { |
| 35 | struct resource *resource; |
| 36 | u32 pcie_config_base, pcie_config_size; |
| 37 | pcie_config_base = MCFG_BASE_ADDRESS; |
| 38 | pcie_config_size = MCFG_BASE_SIZE; |
| 39 | |
| 40 | printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " |
| 41 | "size=0x%x\n", pcie_config_base, pcie_config_size); |
| 42 | resource = new_resource(dev, index++); |
| 43 | resource->base = (resource_t) pcie_config_base; |
| 44 | resource->size = (resource_t) pcie_config_size; |
| 45 | resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | |
| 46 | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; |
| 47 | |
| 48 | resource = new_resource(dev, index++); /* Local APIC */ |
| 49 | resource->base = LAPIC_DEFAULT_BASE; |
| 50 | resource->size = 0x00001000; |
| 51 | resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | |
| 52 | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; |
| 53 | |
| 54 | mmio_resource(dev, index++, legacy_hole_base_k, legacy_hole_size_k); |
| 55 | |
| 56 | return index; |
| 57 | } |
| 58 | |
| 59 | static void mc_add_dram_resources(device_t dev) |
| 60 | { |
| 61 | u32 fsp_mem_base, fsp_mem_len; |
| 62 | u32 tseg_base, tseg_length; |
| 63 | u32 rsv_base, rsv_length; |
| 64 | u32 tolm; |
| 65 | int index = 0; |
| 66 | uint64_t highmem_size = 0; |
| 67 | |
| 68 | fsp_mem_base = GetFspReservedMemory(FspHobListPtr, &fsp_mem_len); |
| 69 | highmem_size = GetUsableHighMemTop(FspHobListPtr) - 0x100000000L; |
| 70 | tseg_base = GetTsegReservedMemory(FspHobListPtr, &tseg_length); |
| 71 | tolm = GetPhysicalLowMemTop(FspHobListPtr); |
| 72 | |
| 73 | printk(BIOS_DEBUG, "\n\n"); |
| 74 | printk(BIOS_DEBUG, "fsp_mem_base: 0x%.8x\n", fsp_mem_base); |
| 75 | printk(BIOS_DEBUG, "fsp_mem_len: 0x%.8x\n", fsp_mem_len); |
| 76 | printk(BIOS_DEBUG, "tseg_base: 0x%.8x\n", tseg_base); |
| 77 | printk(BIOS_DEBUG, "tseg_len: 0x%.8x\n", tseg_length); |
| 78 | printk(BIOS_DEBUG, "highmem_size: 0x%.8x %.8x\n", |
| 79 | (u32)(highmem_size>>32), |
| 80 | (u32)(highmem_size&0xffffffff)); |
| 81 | printk(BIOS_DEBUG, "tolm: 0x%.8x\n", tolm); |
| 82 | printk(BIOS_DEBUG, "Top of system low memory: 0x%08x\n", tolm); |
| 83 | printk(BIOS_DEBUG, "FSP memory location: 0x%x\n (size: %dM)\n", |
| 84 | fsp_mem_base, fsp_mem_len >> 20); |
| 85 | printk(BIOS_DEBUG, "tseg: 0x%08x (size: 0x%.8x)\n", |
| 86 | tseg_base, tseg_length); |
| 87 | |
| 88 | /* Report the memory regions. */ |
| 89 | ram_resource(dev, index++, 0, legacy_hole_base_k); |
| 90 | ram_resource(dev, index++, legacy_hole_base_k + legacy_hole_size_k, |
| 91 | ((fsp_mem_base >> 10) - (legacy_hole_base_k + legacy_hole_size_k))); |
| 92 | |
| 93 | /* Mark SMM & FSP regions reserved */ |
| 94 | mmio_resource(dev, index++, tseg_base >> 10, tseg_length >> 10); |
| 95 | mmio_resource(dev, index++, fsp_mem_base >> 10, fsp_mem_len >> 10); |
| 96 | |
| 97 | /* Reserve MMIO space */ |
| 98 | rsv_base = fsp_mem_base + fsp_mem_len; |
| 99 | rsv_length = tseg_base - rsv_base; |
| 100 | if (rsv_length) { |
| 101 | mmio_resource(dev, index++, rsv_base >> 10, rsv_length >> 10); |
| 102 | printk(BIOS_DEBUG, "Reserved MMIO : 0x%08x length 0x%08x\n", |
| 103 | rsv_base, rsv_length); |
| 104 | } |
| 105 | |
| 106 | rsv_base = tseg_base + tseg_length; |
| 107 | rsv_length = tolm - rsv_base; |
| 108 | if (rsv_length) { |
| 109 | mmio_resource(dev, index++, rsv_base >> 10, rsv_length >> 10); |
| 110 | printk(BIOS_DEBUG, "Reserved MMIO : 0x%08x length 0x%08x\n", |
| 111 | rsv_base, rsv_length); |
| 112 | } |
| 113 | |
| 114 | if (highmem_size) { |
| 115 | ram_resource(dev, index++, 0x100000000 >> 10, highmem_size >> 10); |
| 116 | } |
| 117 | printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", |
| 118 | highmem_size >> 20); |
| 119 | |
| 120 | index = add_fixed_resources(dev, index); |
| 121 | } |
| 122 | |
| 123 | static void nc_read_resources(device_t dev) |
| 124 | { |
| 125 | /* Call the normal read_resources */ |
| 126 | pci_dev_read_resources(dev); |
| 127 | |
| 128 | /* Calculate and add DRAM resources. */ |
| 129 | mc_add_dram_resources(dev); |
| 130 | } |
| 131 | |
| 132 | static void nc_enable(device_t dev) |
| 133 | { |
| 134 | print_fsp_info(); |
| 135 | } |
| 136 | |
| 137 | static struct device_operations nc_ops = { |
Werner Zeh | 1cfb555 | 2016-07-27 08:22:50 +0200 | [diff] [blame] | 138 | .read_resources = nc_read_resources, |
York Yang | d7cba28 | 2016-03-09 10:54:26 -0800 | [diff] [blame] | 139 | .acpi_fill_ssdt_generator = generate_cpu_entries, |
Werner Zeh | 1cfb555 | 2016-07-27 08:22:50 +0200 | [diff] [blame] | 140 | .write_acpi_tables = northcluster_write_acpi_tables, |
| 141 | .set_resources = pci_dev_set_resources, |
| 142 | .enable_resources = pci_dev_enable_resources, |
| 143 | .init = NULL, |
| 144 | .enable = &nc_enable, |
| 145 | .scan_bus = 0, |
| 146 | .ops_pci = &soc_pci_ops, |
York Yang | d7cba28 | 2016-03-09 10:54:26 -0800 | [diff] [blame] | 147 | }; |
| 148 | |
| 149 | static const struct pci_driver nc_driver __pci_driver = { |
| 150 | .ops = &nc_ops, |
| 151 | .vendor = PCI_VENDOR_ID_INTEL, |
| 152 | .device = SOC_DEVID, |
| 153 | }; |
| 154 | |
| 155 | static const struct pci_driver nc_driver_es2 __pci_driver = { |
| 156 | .ops = &nc_ops, |
| 157 | .vendor = PCI_VENDOR_ID_INTEL, |
| 158 | .device = SOC_DEVID_ES2, |
Martin Roth | bb9722b | 2016-07-28 16:32:56 -0600 | [diff] [blame] | 159 | }; |