Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <stdint.h> |
| 17 | #include <cpu/x86/msr.h> |
| 18 | #include <cpu/x86/tsc.h> |
Ben Gardner | fa6014a | 2015-12-08 21:20:25 -0600 | [diff] [blame] | 19 | #include <soc/msr.h> |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 20 | |
| 21 | unsigned bus_freq_khz(void) |
| 22 | { |
| 23 | msr_t clk_info = rdmsr(MSR_BSEL_CR_OVERCLOCK_CONTROL); |
| 24 | switch (clk_info.lo & 0x3) { |
| 25 | case 0: |
| 26 | return 83333; |
| 27 | case 1: |
| 28 | return 100000; |
| 29 | case 2: |
| 30 | return 133333; |
| 31 | case 3: |
| 32 | return 116666; |
| 33 | default: |
| 34 | return 0; |
| 35 | } |
| 36 | } |
| 37 | |
| 38 | unsigned long tsc_freq_mhz(void) |
| 39 | { |
| 40 | msr_t platform_info; |
| 41 | unsigned bclk_khz = bus_freq_khz(); |
| 42 | |
| 43 | if (!bclk_khz) |
| 44 | return 0; |
| 45 | |
| 46 | platform_info = rdmsr(MSR_PLATFORM_INFO); |
| 47 | return (bclk_khz * ((platform_info.lo >> 8) & 0xff)) / 1000; |
| 48 | } |
| 49 | |
| 50 | #if !defined(__SMM__) |
Kayalvizhi Dhandapani | a16055a | 2014-10-07 14:11:20 -0400 | [diff] [blame] | 51 | #if !defined(__PRE_RAM__) |
Ben Gardner | fa6014a | 2015-12-08 21:20:25 -0600 | [diff] [blame] | 52 | #include <soc/ramstage.h> |
Kayalvizhi Dhandapani | a16055a | 2014-10-07 14:11:20 -0400 | [diff] [blame] | 53 | #else |
Ben Gardner | fa6014a | 2015-12-08 21:20:25 -0600 | [diff] [blame] | 54 | #include <soc/romstage.h> |
Kayalvizhi Dhandapani | a16055a | 2014-10-07 14:11:20 -0400 | [diff] [blame] | 55 | #endif |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 56 | |
| 57 | void set_max_freq(void) |
| 58 | { |
| 59 | msr_t perf_ctl; |
| 60 | msr_t msr; |
| 61 | |
| 62 | /* Enable speed step. */ |
| 63 | msr = rdmsr(MSR_IA32_MISC_ENABLES); |
| 64 | msr.lo |= (1 << 16); |
| 65 | wrmsr(MSR_IA32_MISC_ENABLES, msr); |
| 66 | |
| 67 | /* Set guaranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of |
| 68 | * the PERF_CTL. */ |
| 69 | msr = rdmsr(MSR_IACORE_RATIOS); |
| 70 | perf_ctl.lo = (msr.lo & 0x3f0000) >> 8; |
| 71 | /* Set guaranteed vid [21:16] from IACORE_VIDS to bits [7:0] of |
| 72 | * the PERF_CTL. */ |
| 73 | msr = rdmsr(MSR_IACORE_VIDS); |
| 74 | perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16; |
| 75 | perf_ctl.hi = 0; |
| 76 | |
| 77 | wrmsr(MSR_IA32_PERF_CTL, perf_ctl); |
| 78 | } |
| 79 | |
| 80 | #endif /* __SMM__ */ |