Werner Zeh | 1c3b111 | 2016-02-19 10:50:38 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2013 Google Inc. |
| 5 | * Copyright 2016 Siemens AG |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | #include <arch/io.h> |
| 18 | #include <console/console.h> |
| 19 | #include <delay.h> |
| 20 | #include <device/device.h> |
| 21 | #include <device/pci.h> |
| 22 | #include <device/pci_ids.h> |
| 23 | #include <reg_script.h> |
| 24 | #include <stdlib.h> |
| 25 | |
| 26 | #include <soc/gfx.h> |
| 27 | #include <soc/iosf.h> |
| 28 | #include <soc/pci_devs.h> |
| 29 | #include <soc/ramstage.h> |
| 30 | |
| 31 | #define GFX_TIMEOUT 100000 /* 100ms */ |
| 32 | |
| 33 | static const struct reg_script gpu_pre_vbios_script[] = { |
| 34 | /* Make sure GFX is bus master with MMIO access */ |
| 35 | REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MASTER|PCI_COMMAND_MEMORY), |
| 36 | /* Display */ |
| 37 | REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xc0), |
| 38 | REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xc0, 0xc0, |
| 39 | GFX_TIMEOUT), |
| 40 | /* Tx/Rx Lanes */ |
| 41 | REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xfff0c0), |
| 42 | REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfff0c0, 0xfff0c0, |
| 43 | GFX_TIMEOUT), |
| 44 | /* Common Lane */ |
| 45 | REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xfffcc0), |
| 46 | REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffcc0, 0xfffcc0, |
| 47 | GFX_TIMEOUT), |
| 48 | /* Ungating Tx only */ |
| 49 | REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf00cc0), |
| 50 | REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffcc0, 0xf00cc0, |
| 51 | GFX_TIMEOUT), |
| 52 | /* Ungating Common Lane only */ |
| 53 | REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf000c0), |
| 54 | REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xffffc0, 0xf000c0, |
| 55 | GFX_TIMEOUT), |
| 56 | /* Ungating Display */ |
| 57 | REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf00000), |
| 58 | REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffff0, 0xf00000, |
| 59 | GFX_TIMEOUT), |
| 60 | REG_SCRIPT_END |
| 61 | }; |
| 62 | |
| 63 | static const struct reg_script gfx_post_vbios_script[] = { |
| 64 | /* Deassert Render Force-Wake */ |
| 65 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b0, 0x80000000), |
| 66 | REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300b4, 0x8000, 0, GFX_TIMEOUT), |
| 67 | /* Deassert Media Force-Wake */ |
| 68 | REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b8, 0x80000000), |
| 69 | REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300bc, 0x8000, 0, GFX_TIMEOUT), |
| 70 | /* Set Lock bits */ |
| 71 | REG_PCI_RMW32(GGC, 0xffffffff, 1), |
| 72 | REG_PCI_RMW32(GSM_BASE, 0xffffffff, 1), |
| 73 | REG_PCI_RMW32(GTT_BASE, 0xffffffff, 1), |
| 74 | REG_SCRIPT_END |
| 75 | }; |
| 76 | |
| 77 | static inline void gfx_run_script(device_t dev, const struct reg_script *ops) |
| 78 | { |
| 79 | reg_script_run_on_dev(dev, ops); |
| 80 | } |
| 81 | |
| 82 | static void gfx_pre_vbios_init(device_t dev) |
| 83 | { |
| 84 | printk(BIOS_INFO, "GFX: Pre VBIOS Init\n"); |
| 85 | gfx_run_script(dev, gpu_pre_vbios_script); |
| 86 | } |
| 87 | |
| 88 | static void gfx_post_vbios_init(device_t dev) |
| 89 | { |
| 90 | printk(BIOS_INFO, "GFX: Post VBIOS Init\n"); |
| 91 | gfx_run_script(dev, gfx_post_vbios_script); |
| 92 | } |
| 93 | |
| 94 | static void gfx_init(device_t dev) |
| 95 | { |
| 96 | /* Pre VBIOS Init */ |
| 97 | gfx_pre_vbios_init(dev); |
| 98 | |
| 99 | /* Run VBIOS */ |
| 100 | pci_dev_init(dev); |
| 101 | |
| 102 | /* Post VBIOS Init */ |
| 103 | gfx_post_vbios_init(dev); |
| 104 | } |
| 105 | |
| 106 | static struct device_operations gfx_device_ops = { |
| 107 | .read_resources = pci_dev_read_resources, |
| 108 | .set_resources = pci_dev_set_resources, |
| 109 | .enable_resources = pci_dev_enable_resources, |
| 110 | .init = gfx_init, |
| 111 | .ops_pci = &soc_pci_ops, |
| 112 | }; |
| 113 | |
| 114 | static const struct pci_driver gfx_driver __pci_driver = { |
| 115 | .ops = &gfx_device_ops, |
| 116 | .vendor = PCI_VENDOR_ID_INTEL, |
| 117 | .device = GFX_DEVID, |
| 118 | }; |