Ravi Sarawadi | 9d903a1 | 2016-03-04 21:33:04 -0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2015-2016 Intel Corp. |
| 5 | * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.) |
| 6 | * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.) |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
Martin Roth | ebabfad | 2016-04-10 11:09:16 -0600 | [diff] [blame] | 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
Ravi Sarawadi | 9d903a1 | 2016-03-04 21:33:04 -0800 | [diff] [blame] | 17 | */ |
| 18 | |
| 19 | #include <console/console.h> |
| 20 | #include <cpu/cpu.h> |
| 21 | #include <cpu/x86/cache.h> |
| 22 | #include <cpu/x86/mp.h> |
John Zhao | 3156934 | 2016-08-23 16:38:05 -0700 | [diff] [blame] | 23 | #include <cpu/intel/microcode.h> |
Ravi Sarawadi | 9d903a1 | 2016-03-04 21:33:04 -0800 | [diff] [blame] | 24 | #include <cpu/x86/msr.h> |
| 25 | #include <cpu/x86/mtrr.h> |
| 26 | #include <device/device.h> |
| 27 | #include <device/pci.h> |
Ravi Sarawadi | ec729365 | 2016-09-09 14:08:50 -0700 | [diff] [blame] | 28 | #include <reg_script.h> |
Ravi Sarawadi | 9d903a1 | 2016-03-04 21:33:04 -0800 | [diff] [blame] | 29 | #include <soc/cpu.h> |
Ravi Sarawadi | ec729365 | 2016-09-09 14:08:50 -0700 | [diff] [blame] | 30 | #include <soc/iomap.h> |
Andrey Petrov | 3b63753 | 2016-11-30 17:39:16 -0800 | [diff] [blame] | 31 | #include <soc/pm.h> |
Hannah Williams | d9c84ca | 2016-05-13 00:47:14 -0700 | [diff] [blame] | 32 | #include <soc/smm.h> |
Venkateswarlu Vinjamuri | 362180a | 2016-10-31 17:03:55 -0700 | [diff] [blame] | 33 | #include <cpu/intel/turbo.h> |
Ravi Sarawadi | 9d903a1 | 2016-03-04 21:33:04 -0800 | [diff] [blame] | 34 | |
Ravi Sarawadi | ec729365 | 2016-09-09 14:08:50 -0700 | [diff] [blame] | 35 | static const struct reg_script core_msr_script[] = { |
| 36 | /* Enable C-state and IO/MWAIT redirect */ |
| 37 | REG_MSR_WRITE(MSR_PMG_CST_CONFIG_CONTROL, |
| 38 | (PKG_C_STATE_LIMIT_C2_MASK | CORE_C_STATE_LIMIT_C10_MASK |
| 39 | | IO_MWAIT_REDIRECT_MASK | CST_CFG_LOCK_MASK)), |
| 40 | /* Power Management I/O base address for I/O trapping to C-states */ |
| 41 | REG_MSR_WRITE(MSR_PMG_IO_CAPTURE_BASE, |
| 42 | (ACPI_PMIO_CST_REG | (PMG_IO_BASE_CST_RNG_BLK_SIZE << 16))), |
| 43 | /* Disable C1E */ |
| 44 | REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0), |
Venkateswarlu Vinjamuri | 362180a | 2016-10-31 17:03:55 -0700 | [diff] [blame] | 45 | /* Disable support for MONITOR and MWAIT instructions */ |
| 46 | REG_MSR_RMW(MSR_IA32_MISC_ENABLES, ~MONITOR_MWAIT_DIS_MASK, 0), |
Nelson, Cole | 1cf5b87 | 2016-11-11 14:17:37 -0800 | [diff] [blame] | 47 | /* |
| 48 | * Enable and Lock the Advanced Encryption Standard (AES-NI) |
| 49 | * feature register |
| 50 | */ |
| 51 | REG_MSR_RMW(MSR_FEATURE_CONFIG, ~FEATURE_CONFIG_RESERVED_MASK, |
| 52 | FEATURE_CONFIG_LOCK), |
Ravi Sarawadi | ec729365 | 2016-09-09 14:08:50 -0700 | [diff] [blame] | 53 | REG_SCRIPT_END |
| 54 | }; |
| 55 | |
Andrey Petrov | a697c19 | 2016-12-07 10:47:46 -0800 | [diff] [blame] | 56 | void enable_untrusted_mode(void) |
Andrey Petrov | 89e39b5 | 2016-11-30 17:58:38 -0800 | [diff] [blame] | 57 | { |
| 58 | msr_t msr = rdmsr(MSR_POWER_MISC); |
| 59 | msr.lo |= ENABLE_IA_UNTRUSTED; |
| 60 | wrmsr(MSR_POWER_MISC, msr); |
| 61 | } |
| 62 | |
Ravi Sarawadi | ec729365 | 2016-09-09 14:08:50 -0700 | [diff] [blame] | 63 | static void soc_core_init(device_t cpu) |
| 64 | { |
| 65 | /* Set core MSRs */ |
| 66 | reg_script_run(core_msr_script); |
Andrey Petrov | 3b63753 | 2016-11-30 17:39:16 -0800 | [diff] [blame] | 67 | /* |
| 68 | * Enable ACPI PM timer emulation, which also lets microcode know |
| 69 | * location of ACPI_PMIO_BASE. This also enables other features |
| 70 | * implemented in microcode. |
| 71 | */ |
| 72 | enable_pm_timer_emulation(); |
Ravi Sarawadi | ec729365 | 2016-09-09 14:08:50 -0700 | [diff] [blame] | 73 | } |
| 74 | |
Ravi Sarawadi | 9d903a1 | 2016-03-04 21:33:04 -0800 | [diff] [blame] | 75 | static struct device_operations cpu_dev_ops = { |
Ravi Sarawadi | ec729365 | 2016-09-09 14:08:50 -0700 | [diff] [blame] | 76 | .init = soc_core_init, |
Ravi Sarawadi | 9d903a1 | 2016-03-04 21:33:04 -0800 | [diff] [blame] | 77 | }; |
| 78 | |
| 79 | static struct cpu_device_id cpu_table[] = { |
| 80 | { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_A0 }, |
| 81 | { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_B0 }, |
| 82 | { 0, 0 }, |
| 83 | }; |
| 84 | |
| 85 | static const struct cpu_driver driver __cpu_driver = { |
| 86 | .ops = &cpu_dev_ops, |
| 87 | .id_table = cpu_table, |
| 88 | }; |
| 89 | |
Hannah Williams | d9c84ca | 2016-05-13 00:47:14 -0700 | [diff] [blame] | 90 | /* |
| 91 | * MP and SMM loading initialization. |
| 92 | */ |
| 93 | struct smm_relocation_attrs { |
| 94 | uint32_t smbase; |
| 95 | uint32_t smrr_base; |
| 96 | uint32_t smrr_mask; |
| 97 | }; |
| 98 | |
| 99 | static struct smm_relocation_attrs relo_attrs; |
| 100 | |
Ravi Sarawadi | 9d903a1 | 2016-03-04 21:33:04 -0800 | [diff] [blame] | 101 | static void read_cpu_topology(unsigned int *num_phys, unsigned int *num_virt) |
| 102 | { |
| 103 | msr_t msr; |
| 104 | msr = rdmsr(MSR_CORE_THREAD_COUNT); |
| 105 | *num_virt = (msr.lo >> 0) & 0xffff; |
| 106 | *num_phys = (msr.lo >> 16) & 0xffff; |
| 107 | } |
| 108 | |
| 109 | /* |
| 110 | * Do essential initialization tasks before APs can be fired up |
| 111 | * |
| 112 | * 1. Prevent race condition in MTRR solution. Enable MTRRs on the BSP. This |
| 113 | * creates the MTRR solution that the APs will use. Otherwise APs will try to |
| 114 | * apply the incomplete solution as the BSP is calculating it. |
| 115 | */ |
Aaron Durbin | e72b9d4 | 2016-05-03 15:56:24 -0500 | [diff] [blame] | 116 | static void pre_mp_init(void) |
Ravi Sarawadi | 9d903a1 | 2016-03-04 21:33:04 -0800 | [diff] [blame] | 117 | { |
| 118 | x86_setup_mtrrs_with_detect(); |
| 119 | x86_mtrr_check(); |
Martin Roth | 3674c82 | 2016-09-30 08:59:58 -0600 | [diff] [blame] | 120 | |
| 121 | /* Make sure BSP is using the microcode from cbfs */ |
| 122 | intel_update_microcode_from_cbfs(); |
Ravi Sarawadi | 9d903a1 | 2016-03-04 21:33:04 -0800 | [diff] [blame] | 123 | } |
| 124 | |
Aaron Durbin | e72b9d4 | 2016-05-03 15:56:24 -0500 | [diff] [blame] | 125 | /* Find CPU topology */ |
| 126 | static int get_cpu_count(void) |
| 127 | { |
| 128 | unsigned int num_virt_cores, num_phys_cores; |
| 129 | |
| 130 | read_cpu_topology(&num_phys_cores, &num_virt_cores); |
| 131 | |
| 132 | printk(BIOS_DEBUG, "Detected %u core, %u thread CPU.\n", |
| 133 | num_phys_cores, num_virt_cores); |
| 134 | |
| 135 | return num_virt_cores; |
| 136 | } |
| 137 | |
John Zhao | 3156934 | 2016-08-23 16:38:05 -0700 | [diff] [blame] | 138 | static void get_microcode_info(const void **microcode, int *parallel) |
| 139 | { |
| 140 | *microcode = intel_microcode_find(); |
| 141 | *parallel = 1; |
| 142 | } |
| 143 | |
Hannah Williams | d9c84ca | 2016-05-13 00:47:14 -0700 | [diff] [blame] | 144 | static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, |
| 145 | size_t *smm_save_state_size) |
| 146 | { |
| 147 | void *smm_base; |
| 148 | size_t smm_size; |
Brandon Breitenstein | 135eae9 | 2016-09-30 13:57:12 -0700 | [diff] [blame] | 149 | void *handler_base; |
| 150 | size_t handler_size; |
Hannah Williams | d9c84ca | 2016-05-13 00:47:14 -0700 | [diff] [blame] | 151 | |
| 152 | /* All range registers are aligned to 4KiB */ |
| 153 | const uint32_t rmask = ~((1 << 12) - 1); |
| 154 | |
| 155 | /* Initialize global tracking state. */ |
| 156 | smm_region(&smm_base, &smm_size); |
Brandon Breitenstein | 135eae9 | 2016-09-30 13:57:12 -0700 | [diff] [blame] | 157 | smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size); |
| 158 | |
Hannah Williams | d9c84ca | 2016-05-13 00:47:14 -0700 | [diff] [blame] | 159 | relo_attrs.smbase = (uint32_t)smm_base; |
| 160 | relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK; |
| 161 | relo_attrs.smrr_mask = ~(smm_size - 1) & rmask; |
| 162 | relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID; |
| 163 | |
Brandon Breitenstein | 135eae9 | 2016-09-30 13:57:12 -0700 | [diff] [blame] | 164 | *perm_smbase = (uintptr_t)handler_base; |
| 165 | *perm_smsize = handler_size; |
Hannah Williams | d9c84ca | 2016-05-13 00:47:14 -0700 | [diff] [blame] | 166 | *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t); |
| 167 | } |
| 168 | |
| 169 | static void relocation_handler(int cpu, uintptr_t curr_smbase, |
| 170 | uintptr_t staggered_smbase) |
| 171 | { |
| 172 | msr_t smrr; |
| 173 | em64t100_smm_state_save_area_t *smm_state; |
| 174 | /* Set up SMRR. */ |
| 175 | smrr.lo = relo_attrs.smrr_base; |
| 176 | smrr.hi = 0; |
| 177 | wrmsr(SMRR_PHYS_BASE, smrr); |
| 178 | smrr.lo = relo_attrs.smrr_mask; |
| 179 | smrr.hi = 0; |
| 180 | wrmsr(SMRR_PHYS_MASK, smrr); |
| 181 | smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase); |
| 182 | smm_state->smbase = staggered_smbase; |
| 183 | } |
Ravi Sarawadi | 9d903a1 | 2016-03-04 21:33:04 -0800 | [diff] [blame] | 184 | /* |
| 185 | * CPU initialization recipe |
| 186 | * |
| 187 | * Note that no microcode update is passed to the init function. CSE updates |
| 188 | * the microcode on all cores before releasing them from reset. That means that |
| 189 | * the BSP and all APs will come up with the same microcode revision. |
| 190 | */ |
Aaron Durbin | e72b9d4 | 2016-05-03 15:56:24 -0500 | [diff] [blame] | 191 | static const struct mp_ops mp_ops = { |
| 192 | .pre_mp_init = pre_mp_init, |
| 193 | .get_cpu_count = get_cpu_count, |
Hannah Williams | d9c84ca | 2016-05-13 00:47:14 -0700 | [diff] [blame] | 194 | .get_smm_info = get_smm_info, |
John Zhao | 3156934 | 2016-08-23 16:38:05 -0700 | [diff] [blame] | 195 | .get_microcode_info = get_microcode_info, |
Hannah Williams | d9c84ca | 2016-05-13 00:47:14 -0700 | [diff] [blame] | 196 | .pre_mp_smm_init = southbridge_smm_clear_state, |
| 197 | .relocation_handler = relocation_handler, |
| 198 | .post_mp_init = southbridge_smm_enable_smi, |
Ravi Sarawadi | 9d903a1 | 2016-03-04 21:33:04 -0800 | [diff] [blame] | 199 | }; |
| 200 | |
| 201 | void apollolake_init_cpus(device_t dev) |
| 202 | { |
Ravi Sarawadi | 9d903a1 | 2016-03-04 21:33:04 -0800 | [diff] [blame] | 203 | /* Clear for take-off */ |
Aaron Durbin | e72b9d4 | 2016-05-03 15:56:24 -0500 | [diff] [blame] | 204 | if (mp_init_with_smm(dev->link_list, &mp_ops) < 0) |
Ravi Sarawadi | 9d903a1 | 2016-03-04 21:33:04 -0800 | [diff] [blame] | 205 | printk(BIOS_ERR, "MP initialization failure.\n"); |
Aaron Durbin | bf696f5 | 2016-11-10 20:04:19 -0600 | [diff] [blame] | 206 | |
| 207 | /* Temporarily cache the memory-mapped boot media. */ |
| 208 | if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)) |
| 209 | mtrr_use_temp_range(-CONFIG_ROM_SIZE, CONFIG_ROM_SIZE, |
| 210 | MTRR_TYPE_WRPROT); |
Ravi Sarawadi | 9d903a1 | 2016-03-04 21:33:04 -0800 | [diff] [blame] | 211 | } |