Stefan Reinauer | 6651da3 | 2012-04-27 23:16:30 +0200 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #ifndef LINK_GPIO_H |
| 21 | #define LINK_GPIO_H |
| 22 | |
| 23 | #include "southbridge/intel/bd82x6x/gpio.h" |
| 24 | |
| 25 | const struct pch_gpio_set1 pch_gpio_set1_mode = { |
| 26 | .gpio0 = GPIO_MODE_GPIO, |
| 27 | .gpio1 = GPIO_MODE_GPIO, |
| 28 | .gpio3 = GPIO_MODE_GPIO, |
| 29 | .gpio5 = GPIO_MODE_GPIO, |
| 30 | .gpio6 = GPIO_MODE_GPIO, |
| 31 | .gpio7 = GPIO_MODE_GPIO, |
| 32 | .gpio8 = GPIO_MODE_GPIO, |
| 33 | .gpio9 = GPIO_MODE_GPIO, |
| 34 | .gpio12 = GPIO_MODE_GPIO, |
| 35 | .gpio15 = GPIO_MODE_GPIO, |
| 36 | .gpio21 = GPIO_MODE_GPIO, |
| 37 | .gpio24 = GPIO_MODE_GPIO, |
| 38 | .gpio27 = GPIO_MODE_GPIO, |
| 39 | .gpio28 = GPIO_MODE_GPIO, |
| 40 | }; |
| 41 | |
| 42 | const struct pch_gpio_set1 pch_gpio_set1_direction = { |
| 43 | .gpio0 = GPIO_DIR_INPUT, |
| 44 | .gpio3 = GPIO_DIR_INPUT, |
| 45 | .gpio5 = GPIO_DIR_INPUT, |
| 46 | .gpio7 = GPIO_DIR_INPUT, |
| 47 | .gpio8 = GPIO_DIR_INPUT, |
| 48 | .gpio9 = GPIO_DIR_INPUT, |
| 49 | .gpio12 = GPIO_DIR_INPUT, |
| 50 | .gpio15 = GPIO_DIR_INPUT, |
| 51 | .gpio21 = GPIO_DIR_INPUT, |
| 52 | .gpio27 = GPIO_DIR_INPUT, |
| 53 | }; |
| 54 | |
| 55 | const struct pch_gpio_set1 pch_gpio_set1_level = { |
| 56 | }; |
| 57 | |
| 58 | const struct pch_gpio_set1 pch_gpio_set1_invert = { |
| 59 | }; |
| 60 | |
| 61 | const struct pch_gpio_set2 pch_gpio_set2_mode = { |
| 62 | .gpio36 = GPIO_MODE_GPIO, |
| 63 | .gpio57 = GPIO_MODE_GPIO, |
| 64 | .gpio60 = GPIO_MODE_GPIO, |
| 65 | }; |
| 66 | |
| 67 | const struct pch_gpio_set2 pch_gpio_set2_direction = { |
| 68 | .gpio57 = GPIO_DIR_INPUT, |
| 69 | }; |
| 70 | |
| 71 | const struct pch_gpio_set2 pch_gpio_set2_level = { |
| 72 | }; |
| 73 | |
| 74 | const struct pch_gpio_set3 pch_gpio_set3_mode = { |
| 75 | }; |
| 76 | |
| 77 | const struct pch_gpio_set3 pch_gpio_set3_direction = { |
| 78 | }; |
| 79 | |
| 80 | const struct pch_gpio_set3 pch_gpio_set3_level = { |
| 81 | }; |
| 82 | |
| 83 | const struct pch_gpio_map link_gpio_map = { |
| 84 | .set1 = { |
| 85 | .mode = &pch_gpio_set1_mode, |
| 86 | .direction = &pch_gpio_set1_direction, |
| 87 | .level = &pch_gpio_set1_level, |
| 88 | .invert = &pch_gpio_set1_invert, |
| 89 | }, |
| 90 | .set2 = { |
| 91 | .mode = &pch_gpio_set2_mode, |
| 92 | .direction = &pch_gpio_set2_direction, |
| 93 | .level = &pch_gpio_set2_level, |
| 94 | }, |
| 95 | .set3 = { |
| 96 | .mode = &pch_gpio_set3_mode, |
| 97 | .direction = &pch_gpio_set3_direction, |
| 98 | .level = &pch_gpio_set3_level, |
| 99 | }, |
| 100 | }; |
| 101 | |
| 102 | #endif |