blob: f803aaf8b98a11ab25f2f9e17e1ca6627b039293 [file] [log] [blame]
Stefan Reinauer6651da32012-04-27 23:16:30 +02001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20/* Values should match those defined in devicetree.cb */
21
22#undef SIO_ENABLE_FDC0 // pnp 2e.0: Disable Floppy Controller
23#undef SIO_ENABLE_INFR // pnp 2e.a: Disable Consumer IR
24
25#define SIO_ENABLE_PS2K // pnp 2e.5: Enable PS/2 Keyboard
26#define SIO_ENABLE_PS2M // pnp 2e.6: Enable PS/2 Mouse
27#define SIO_ENABLE_COM1 // pnp 2e.1: Enable Serial Port 1
28#define SIO_ENABLE_ENVC // pnp 2e.4: Enable Environmental Controller
29#define SIO_ENVC_IO0 0x700 // pnp 2e.4: io 0x60
30#define SIO_ENVC_IO1 0x710 // pnp 2e.4: io 0x62
31#define SIO_ENABLE_GPIO // pnp 2e.7: Enable GPIO
32#define SIO_GPIO_IO0 0x720 // pnp 2e.7: io 0x60
33#define SIO_GPIO_IO1 0x730 // pnp 2e.7: io 0x60
34
35#include "../../../../superio/smsc/sio1007/acpi/superio.asl"