Eric Lai | 5e053af | 2020-11-26 12:58:10 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | |
| 3 | #include <baseboard/gpio.h> |
| 4 | #include <baseboard/variants.h> |
| 5 | #include <commonlib/helpers.h> |
Tim Wawrzynczak | 885e84e | 2021-03-05 15:44:42 -0700 | [diff] [blame] | 6 | #include <soc/gpio.h> |
Eric Lai | b052c4b | 2020-11-27 13:50:02 +0800 | [diff] [blame] | 7 | #include <vendorcode/google/chromeos/chromeos.h> |
Eric Lai | 5e053af | 2020-11-26 12:58:10 +0800 | [diff] [blame] | 8 | |
| 9 | /* Pad configuration in ramstage */ |
| 10 | static const struct pad_config gpio_table[] = { |
Eric Lai | a239691 | 2020-12-04 12:08:50 +0800 | [diff] [blame] | 11 | /* A0 thru A5, A9 and A10 come configured out of reset, do not touch */ |
| 12 | /* A0 : ESPI_IO0 ==> ESPI_IO_0 */ |
| 13 | /* A1 : ESPI_IO1 ==> ESPI_IO_1 */ |
| 14 | /* A2 : ESPI_IO2 ==> ESPI_IO_2 */ |
| 15 | /* A3 : ESPI_IO3 ==> ESPI_IO_3 */ |
| 16 | /* A4 : ESPI_CS# ==> ESPI_CS_L */ |
| 17 | /* A5 : ESPI_ALERT0# ==> NC */ |
| 18 | PAD_NC(GPP_A5, NONE), |
| 19 | /* A6 : ESPI_ALERT1# ==> SPKR_INT_L */ |
| 20 | PAD_CFG_GPI(GPP_A6, NONE, DEEP), |
| 21 | /* A7 : SRCCLK_OE7# ==> WWAN_PCIE_WAKE_ODL */ |
| 22 | PAD_CFG_GPI_APIC(GPP_A7, NONE, PLTRST, LEVEL, INVERT), |
| 23 | /* A8 : SRCCLKREQ7# ==> WWAN_RF_DISABLE_ODL */ |
| 24 | PAD_CFG_GPO(GPP_A8, 1, DEEP), |
| 25 | /* A9 : ESPI_CLK ==> ESPI_CLK */ |
| 26 | /* A10 : ESPI_RESET# ==> ESPI_PCH_RST_EC_L */ |
| 27 | /* A11 : PMC_I2C_SDA ==> EN_SPKR_PA */ |
| 28 | PAD_CFG_GPO(GPP_A11, 1, DEEP), |
| 29 | /* A12 : SATAXPCIE1 ==> EN_PPVAR_WWAN */ |
| 30 | PAD_CFG_GPO(GPP_A12, 1, DEEP), |
| 31 | /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ |
| 32 | PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), |
| 33 | /* A14 : USB_OC1# ==> USB_C1_OC_ODL */ |
| 34 | PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), |
| 35 | /* A15 : USB_OC2# ==> USB_C2_OC_ODL */ |
| 36 | PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), |
| 37 | /* A16 : USB_OC3# ==> USB_A0_OC_ODL */ |
| 38 | PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), |
| 39 | /* A17 : DISP_MISCC ==> EN_FCAM_PWR */ |
| 40 | PAD_CFG_GPO(GPP_A17, 1, DEEP), |
| 41 | /* A18 : DDSP_HPDB ==> HDMI_HPD */ |
| 42 | PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), |
| 43 | /* A19 : DDSP_HPD1 ==> USB_C2_AUX_DC_P */ |
| 44 | PAD_CFG_NF(GPP_A19, NONE, DEEP, NF6), |
| 45 | /* A20 : DDSP_HPD2 ==> USB_C2_AUX_DC_N */ |
| 46 | PAD_CFG_NF(GPP_A20, NONE, DEEP, NF6), |
| 47 | /* A21 : DDPC_CTRCLK ==> USB_C1_AUX_DC_P */ |
| 48 | PAD_CFG_NF(GPP_A21, NONE, DEEP, NF6), |
| 49 | /* A22 : DDPC_CTRLDATA ==> USB_C1_AUX_DC_N */ |
| 50 | PAD_CFG_NF(GPP_A22, NONE, DEEP, NF6), |
| 51 | /* A23 : ESPI_CS1# ==> AUD_HP_INT_L */ |
| 52 | PAD_CFG_GPI_INT(GPP_A23, NONE, PLTRST, EDGE_BOTH), |
| 53 | |
| 54 | /* B0 : SOC_VID0 */ |
| 55 | PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), |
| 56 | /* B1 : SOC_VID1 */ |
| 57 | PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), |
| 58 | /* B2 : VRALERT# ==> NC */ |
| 59 | PAD_NC(GPP_B2, NONE), |
| 60 | /* B3 : PROC_GP2 ==> SAR2_INT_L */ |
| 61 | PAD_CFG_GPI_INT(GPP_B3, NONE, PLTRST, LEVEL), |
| 62 | /* B4 : PROC_GP3 ==> SSD_PERST_L */ |
| 63 | PAD_CFG_GPO(GPP_B4, 1, DEEP), |
| 64 | /* B5 : ISH_I2C0_SDA ==> PCH_I2C_MISC_SDA */ |
| 65 | PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2), |
| 66 | /* B6 : ISH_I2C0_SCL ==> PCH_I2C_MISC_SCL */ |
| 67 | PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2), |
| 68 | /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ |
| 69 | PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), |
| 70 | /* B8 : ISH_I2C1_SCL ==> PCH_I2C_TPM_SCL */ |
| 71 | PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), |
| 72 | /* B9 : NC */ |
| 73 | PAD_NC(GPP_B9, NONE), |
| 74 | /* B10 : NC */ |
| 75 | PAD_NC(GPP_B10, NONE), |
| 76 | /* B11 : PMCALERT# ==> EN_PP3300_WLAN */ |
| 77 | PAD_CFG_GPO(GPP_B11, 1, DEEP), |
| 78 | /* B12 : SLP_S0# ==> SLP_S0_L */ |
| 79 | PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), |
| 80 | /* B13 : PLTRST# ==> PLT_RST_L */ |
| 81 | PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), |
| 82 | /* B14 : SPKR ==> GPP_B14_STRAP */ |
| 83 | PAD_NC(GPP_B14, NONE), |
| 84 | /* B15 : TIME_SYNC0 ==> NC */ |
| 85 | PAD_NC(GPP_B15, NONE), |
| 86 | /* B16 : I2C5_SDA ==> PCH_I2C_TCHPAD_SDA */ |
| 87 | PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2), |
| 88 | /* B17 : I2C5_SCL ==> PCH_I2C_TCHPAD_SCL */ |
| 89 | PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2), |
| 90 | /* B18 : ADR_COMPLETE ==> GPP_B18_STRAP */ |
| 91 | PAD_NC(GPP_B18, NONE), |
| 92 | /* B19 : NC */ |
| 93 | PAD_NC(GPP_B19, NONE), |
| 94 | /* B20 : NC */ |
| 95 | PAD_NC(GPP_B20, NONE), |
| 96 | /* B21 : NC */ |
| 97 | PAD_NC(GPP_B21, NONE), |
| 98 | /* B22 : NC */ |
| 99 | PAD_NC(GPP_B22, NONE), |
| 100 | /* B23 : SML1ALERT# ==> PCHHOT_ODL_STRAP */ |
| 101 | PAD_NC(GPP_B23, NONE), |
| 102 | |
| 103 | /* C0 : SMBCLK ==> EN_PP3300_TCHSCR */ |
| 104 | PAD_CFG_GPO(GPP_C0, 1, DEEP), |
| 105 | /* C1 : SMBDATA ==> USI_RST_L */ |
| 106 | PAD_CFG_GPO(GPP_C1, 0, DEEP), |
| 107 | /* C2 : SMBALERT# ==> GPP_C2_STRAP */ |
| 108 | PAD_NC(GPP_C2, NONE), |
| 109 | /* C3 : SML0CLK ==> NC */ |
| 110 | PAD_NC(GPP_C3, NONE), |
| 111 | /* C4 : SML0DATA ==> NC */ |
| 112 | PAD_NC(GPP_C4, NONE), |
| 113 | /* C5 : SML0ALERT# ==> GPP_C5_BOOT_STRAP0 */ |
| 114 | PAD_NC(GPP_C5, NONE), |
| 115 | /* C6 : SML1CLK ==> USI_REPORT_EN */ |
| 116 | PAD_CFG_GPO(GPP_C6, 0, DEEP), |
| 117 | /* C7 : SML1DATA ==> USI_INT */ |
| 118 | PAD_CFG_GPI_APIC(GPP_C7, NONE, PLTRST, LEVEL, NONE), |
| 119 | |
| 120 | /* D0 : ISH_GP0 ==> PCH_FP_BOOT0 */ |
| 121 | PAD_NC(GPP_D0, NONE), |
| 122 | /* D1 : ISH_GP1 ==> FP_RST_ODL */ |
| 123 | PAD_CFG_GPO(GPP_D1, 0, DEEP), |
| 124 | /* D2 : ISH_GP2 ==> EN_FP_PWR */ |
| 125 | PAD_CFG_GPO(GPP_D2, 1, DEEP), |
| 126 | /* D3 : ISH_GP3 ==> WCAM_RST_L */ |
| 127 | PAD_CFG_GPO(GPP_D3, 0, DEEP), |
| 128 | /* D4 : IMGCLKOUT0 ==> BT_DISABLE_L */ |
| 129 | PAD_CFG_GPO(GPP_D4, 1, DEEP), |
| 130 | /* D5 : SRCCLKREQ0# ==> WWAN_DPR_SAR_ODL */ |
| 131 | PAD_CFG_GPO(GPP_D5, 1, DEEP), |
| 132 | /* D6 : SRCCLKREQ1# ==> SSD_CLKREQ_ODL */ |
| 133 | PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), |
| 134 | /* D7 : SRCCLKREQ2# ==> WLAN_CLKREQ_ODL */ |
| 135 | PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), |
| 136 | /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ |
| 137 | PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), |
| 138 | /* D9 : ISH_SPI_CS# ==> USB_C2_LSX_TX */ |
| 139 | PAD_CFG_NF(GPP_D9, NONE, DEEP, NF4), |
| 140 | /* D10 : ISH_SPI_CLK ==> USB_C2_LSX_RX_STRAP */ |
| 141 | PAD_CFG_NF(GPP_D10, NONE, DEEP, NF4), |
| 142 | /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ |
| 143 | PAD_CFG_GPO(GPP_D11, 1, DEEP), |
| 144 | /* D12 : ISH_SPI_MOSI ==> GPP_D12_STRAP */ |
| 145 | PAD_NC(GPP_D12, NONE), |
| 146 | /* D13 : ISH_UART0_RXD ==> PCH_I2C_CAM_SDA */ |
| 147 | PAD_CFG_NF(GPP_D13, NONE, DEEP, NF3), |
| 148 | /* D14 : ISH_UART0_TXD ==> PCH_I2C_CAM_SCL */ |
| 149 | PAD_CFG_NF(GPP_D14, NONE, DEEP, NF3), |
| 150 | /* D15 : ISH_UART0_RTS# ==> EN_WCAM_SENR_PWR */ |
| 151 | PAD_CFG_GPO(GPP_D15, 1, DEEP), |
| 152 | /* D16 : ISH_UART0_CTS# ==> EN_WCAM_PWR */ |
| 153 | PAD_CFG_GPO(GPP_D16, 1, DEEP), |
| 154 | /* D17 : UART1_RXD ==> SD_PE_PRSNT_L */ |
| 155 | PAD_CFG_GPI(GPP_D17, NONE, DEEP), |
| 156 | /* D18 : UART1_TXD ==> SD_PE_RST_L */ |
| 157 | PAD_CFG_GPO(GPP_D18, 0, DEEP), |
| 158 | /* D19 : I2S_MCLK1_OUT ==> I2S_MCLK_R */ |
| 159 | PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), |
| 160 | |
| 161 | /* E0 : SATAXPCIE0 ==> WWAN_PERST_L */ |
| 162 | PAD_CFG_GPO(GPP_E0, 1, DEEP), |
| 163 | /* E1 : THC0_SPI1_IO2 ==> MEM_STRAP_2 */ |
| 164 | PAD_CFG_GPI(GPP_E1, NONE, DEEP), |
| 165 | /* E2 : THC0_SPI1_IO3 ==> MEM_STRAP_1 */ |
| 166 | PAD_CFG_GPI(GPP_E2, NONE, DEEP), |
| 167 | /* E3 : PROC_GP0 ==> HPS_INT_ODL */ |
| 168 | PAD_CFG_GPI_IRQ_WAKE(GPP_E3, NONE, PLTRST, LEVEL, NONE), |
| 169 | /* E4 : SATA_DEVSLP0 ==> USB4_BB_RT_FORCE_PWR */ |
| 170 | PAD_CFG_GPO(GPP_E4, 1, DEEP), |
| 171 | /* E5 : SATA_DEVSLP1 ==> USB_A0_RT_RST_ODL */ |
| 172 | PAD_CFG_GPO(GPP_E5, 1, DEEP), |
| 173 | /* E6 : THC0_SPI1_RST# ==> GPPE6_STRAP */ |
| 174 | PAD_NC(GPP_E6, NONE), |
| 175 | /* E7 : PROC_GP1 ==> EN_HPS_PWR */ |
| 176 | PAD_CFG_GPO(GPP_E7, 1, DEEP), |
| 177 | /* E8 : SLP_DRAM# ==> WIFI_DISABLE_L */ |
| 178 | PAD_CFG_GPO(GPP_E8, 1, DEEP), |
| 179 | /* E9 : USB_OC0# ==> USB_C0_OC_ODL */ |
| 180 | PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), |
| 181 | /* E10 : THC0_SPI1_CS# ==> WWAN_CONFIG0 */ |
| 182 | PAD_CFG_GPI(GPP_E10, NONE, DEEP), |
| 183 | /* E11 : THC0_SPI1_CLK ==> MEM_STRAP_0 */ |
| 184 | PAD_CFG_GPI(GPP_E11, NONE, DEEP), |
| 185 | /* E12 : THC0_SPI1_IO1 ==> MEM_STRAP_3 */ |
| 186 | PAD_CFG_GPI(GPP_E12, NONE, DEEP), |
| 187 | /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ |
| 188 | PAD_CFG_GPI(GPP_E13, NONE, DEEP), |
| 189 | /* E14 : DDSP_HPDA ==> SOC_EDP_HPD */ |
| 190 | PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), |
| 191 | /* E15 : RSVD_TP ==> PCH_WP_OD */ |
| 192 | PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), |
| 193 | /* E16 : RSVD_TP ==> WWAN_RST_L */ |
| 194 | PAD_CFG_GPO(GPP_E16, 0, DEEP), |
| 195 | /* E17 : THC0_SPI1_INT# ==> WWAN_CONFIG3 */ |
| 196 | PAD_CFG_GPI(GPP_E17, NONE, DEEP), |
| 197 | /* E18 : DDP1_CTRLCLK ==> USB_C0_LSX_SOC_TX */ |
| 198 | PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4), |
| 199 | /* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_SOC_RX_STRAP */ |
| 200 | PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4), |
| 201 | /* E20 : DDP2_CTRLCLK ==> USB_C1_LSX_SOC_TX */ |
| 202 | PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4), |
| 203 | /* E21 : DDP2_CTRLDATA ==> USB_C1_LSX_SOC_RX_STRAP */ |
| 204 | PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4), |
| 205 | /* E22 : DDPA_CTRLCLK ==> USB_C0_AUX_DC_P */ |
| 206 | PAD_CFG_NF(GPP_E22, NONE, DEEP, NF6), |
| 207 | /* E23 : DDPA_CTRLDATA ==> USB_C0_AUX_DC_N */ |
| 208 | PAD_CFG_NF(GPP_E23, NONE, DEEP, NF6), |
| 209 | |
| 210 | /* F0 : CNV_BRI_DT ==> CNV_BRI_DT_STRAP */ |
| 211 | PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), |
| 212 | /* F1 : CNV_BRI_RSP ==> CNV_BRI_RSP */ |
| 213 | PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), |
| 214 | /* F2 : CNV_RGI_DT ==> CNV_RGI_DT_STRAP */ |
| 215 | PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), |
| 216 | /* F3 : CNV_RGI_RSP ==> CNV_RGI_RSP */ |
| 217 | PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), |
| 218 | /* F4 : CNV_RF_RESET# ==> CNV_RF_RST_L */ |
| 219 | PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), |
| 220 | /* F5 : MODEM_CLKREQ ==> CNV_CLKREQ0 */ |
| 221 | PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3), |
| 222 | /* F6 : CNV_PA_BLANKING ==> WWAN_WLAN_COEX3 */ |
| 223 | PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), |
| 224 | /* F7 : GPPF7_STRAP */ |
| 225 | PAD_NC(GPP_F7, NONE), |
| 226 | /* F8 : NC */ |
| 227 | PAD_NC(GPP_F8, NONE), |
| 228 | /* F9 : BOOTMPC ==> SLP_S0_GATE_R */ |
| 229 | PAD_CFG_GPO(GPP_F9, 1, PLTRST), |
| 230 | /* F10 : GPPF10_STRAP */ |
| 231 | PAD_NC(GPP_F10, DN_20K), |
| 232 | /* F11 : THC1_SPI2_CLK ==> GSPI_PCH_CLK_FPMCU_R */ |
| 233 | PAD_CFG_NF(GPP_F11, NONE, DEEP, NF4), |
| 234 | /* F12 : GSXDOUT ==> GSPI_PCH_DO_FPMCU_DI_R */ |
| 235 | PAD_CFG_NF(GPP_F12, NONE, DEEP, NF4), |
| 236 | /* F13 : GSXDOUT ==> GSPI_PCH_DI_FPMCU_DO */ |
| 237 | PAD_CFG_NF(GPP_F13, NONE, DEEP, NF4), |
| 238 | /* F14 : GSXDIN ==> TCHPAD_INT_ODL */ |
| 239 | PAD_CFG_GPI_IRQ_WAKE(GPP_F14, NONE, DEEP, LEVEL, INVERT), |
| 240 | /* F15 : GSXSRESET# ==> FPMCU_INT_L */ |
| 241 | PAD_CFG_GPI_IRQ_WAKE(GPP_F15, NONE, DEEP, LEVEL, INVERT), |
| 242 | /* F16 : GSXCLK ==> GSPI_PCH_CS_FPMCU_R_L */ |
| 243 | PAD_CFG_NF(GPP_F16, NONE, DEEP, NF4), |
| 244 | /* F17 : THC1_SPI2_RST# ==> EC_PCH_INT_ODL */ |
Boris Mittelberg | 65fce09 | 2021-03-25 22:19:16 +0000 | [diff] [blame^] | 245 | PAD_CFG_GPI_IRQ_WAKE(GPP_F17, NONE, DEEP, LEVEL, INVERT), |
Eric Lai | a239691 | 2020-12-04 12:08:50 +0800 | [diff] [blame] | 246 | /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ |
| 247 | PAD_CFG_GPI(GPP_F18, NONE, DEEP), |
| 248 | /* F19 : SRCCLKREQ6# ==> WWAN_SIM1_DET_OD */ |
| 249 | PAD_CFG_GPI(GPP_F19, NONE, DEEP), |
| 250 | /* F20 : EXT_PWR_GATE# ==> HPS_RST_R */ |
| 251 | PAD_CFG_GPO(GPP_F20, 0, DEEP), |
| 252 | /* F21 : EXT_PWR_GATE2# ==> WAKE_ON_WWAN_ODL */ |
| 253 | PAD_CFG_GPI_IRQ_WAKE(GPP_F21, NONE, DEEP, LEVEL, INVERT), |
| 254 | /* F22 : NC */ |
| 255 | PAD_NC(GPP_F22, NONE), |
| 256 | /* F23 : NC */ |
| 257 | PAD_NC(GPP_F23, NONE), |
| 258 | |
| 259 | /* H0 : GPPH0_BOOT_STRAP1 */ |
| 260 | PAD_NC(GPP_H0, NONE), |
| 261 | /* H1 : GPPH1_BOOT_STRAP2 */ |
| 262 | PAD_NC(GPP_H1, NONE), |
| 263 | /* H2 : GPPH2_BOOT_STRAP3 */ |
| 264 | PAD_NC(GPP_H2, NONE), |
| 265 | /* H3 : SX_EXIT_HOLDOFF# ==> WLAN_PCIE_WAKE_ODL */ |
| 266 | PAD_CFG_GPI(GPP_H3, NONE, DEEP), |
| 267 | /* H4 : I2C0_SDA ==> PCH_I2C_AUD_SDA */ |
| 268 | PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), |
| 269 | /* H5 : I2C0_SCL ==> PCH_I2C_AUD_SCL */ |
| 270 | PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), |
| 271 | /* H6 : I2C1_SDA ==> PCH_I2C_TCHSCR_SDA */ |
| 272 | PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), |
| 273 | /* H7 : I2C1_SCL ==> PCH_I2C_TCHSCR_SCL */ |
| 274 | PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), |
| 275 | /* H8 : I2C4_SDA ==> WWAN_WLAN_COEX1 */ |
| 276 | PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2), |
| 277 | /* H9 : I2C4_SCL ==> WWAN_WLAN_COEX2 */ |
| 278 | PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2), |
| 279 | /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ |
| 280 | PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), |
| 281 | /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ |
| 282 | PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), |
| 283 | /* H12 : I2C7_SDA ==> SD_PE_WAKE_ODL */ |
| 284 | PAD_CFG_GPI(GPP_H12, NONE, DEEP), |
| 285 | /* H13 : I2C7_SCL ==> EN_PP3300_SD */ |
| 286 | PAD_CFG_GPO(GPP_H13, 1, DEEP), |
| 287 | /* H14 : NC */ |
| 288 | PAD_NC(GPP_H14, NONE), |
| 289 | /* H15 : DDPB_CTRLCLK ==> DDIB_HDMI_CTRLCLK */ |
| 290 | PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), |
| 291 | /* H16 : NC */ |
| 292 | PAD_NC(GPP_H16, NONE), |
| 293 | /* H17 : DDPB_CTRLDATA ==> DDIB_HDMI_CTRLDATA */ |
| 294 | PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), |
| 295 | /* H18 : PROC_C10_GATE# ==> CPU_C10_GATE_L */ |
| 296 | PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), |
| 297 | /* H19 : SRCCLKREQ4# ==> SAR1_INT_L */ |
| 298 | PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE), |
| 299 | /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */ |
| 300 | PAD_CFG_GPO(GPP_H20, 1, DEEP), |
| 301 | /* H21 : IMGCLKOUT2 ==> WLAN_INT_L */ |
| 302 | PAD_CFG_GPI_APIC(GPP_H21, NONE, DEEP, EDGE_SINGLE, NONE), |
| 303 | /* H22 : IMGCLKOUT3 ==> WCAM_MCLK_R */ |
| 304 | PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), |
| 305 | /* H23 : SRCCLKREQ5# ==> WWAN_CLKREQ_ODL */ |
| 306 | PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2), |
| 307 | |
| 308 | /* R0 : HDA_BCLK ==> I2S_HP_SCLK_R */ |
| 309 | PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), |
| 310 | /* R1 : HDA_SYNC ==> I2S_HP_SFRM_R */ |
| 311 | PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), |
| 312 | /* R2 : HDA_SDO ==> I2S_PCH_TX_HP_RX_STRAP */ |
| 313 | PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), |
| 314 | /* R3 : HDA_SDIO ==> I2S_PCH_RX_HP_TX */ |
| 315 | PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), |
| 316 | /* R4 : HDA_RST# ==> I2S_SPKR_SCLK_R */ |
| 317 | PAD_CFG_NF(GPP_R4, NONE, DEEP, NF2), |
| 318 | /* R5 : HDA_SDI1 ==> I2S_SPKR_SFRM_R */ |
| 319 | PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), |
| 320 | /* R6 : I2S2_TXD ==> I2S_PCH_TX_SPKR_RX_R */ |
| 321 | PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), |
| 322 | /* R7 : I2S2_RXD ==> I2S_PCH_RX_SPKR_TX */ |
| 323 | PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), |
| 324 | |
| 325 | /* S0 : SNDW0_CLK ==> SDW_HP_CLK_R */ |
| 326 | PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), |
| 327 | /* S1 : SNDW0_DATA ==> SDW_HP_DATA_R */ |
| 328 | PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), |
| 329 | /* S2 : SNDW1_CLK ==> DMIC_CLK0_R */ |
| 330 | PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2), |
| 331 | /* S3 : SNDW1_DATA ==> DMIC_DATA0_R */ |
| 332 | PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2), |
| 333 | /* S4 : SNDW2_CLK ==> SDW_SPKR_CLK */ |
| 334 | PAD_CFG_NF(GPP_S4, NONE, DEEP, NF1), |
| 335 | /* S5 : SNDW2_DATA ==> SDW_SPKR_DATA */ |
| 336 | PAD_CFG_NF(GPP_S5, NONE, DEEP, NF1), |
| 337 | /* S6 : SNDW3_CLK ==> DMIC_CLK1_R */ |
| 338 | PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), |
| 339 | /* S7 : SNDW3_DATA ==> DMIC_DATA1_R */ |
| 340 | PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), |
| 341 | |
| 342 | /* GPD0: BATLOW# ==> BATLOW_L */ |
| 343 | PAD_CFG_NF(GPD0, NONE, DEEP, NF1), |
| 344 | /* GPD1: ACPRESENT ==> PCH_ACPRESENT */ |
| 345 | PAD_CFG_NF(GPD1, NONE, DEEP, NF1), |
Boris Mittelberg | 93df61f | 2021-01-27 15:55:01 -0800 | [diff] [blame] | 346 | /* GPD2: LAN_WAKE# ==> NC */ |
| 347 | PAD_NC(GPD2, NONE), |
Eric Lai | a239691 | 2020-12-04 12:08:50 +0800 | [diff] [blame] | 348 | /* GPD3: PWRBTN# ==> EC_PCH_PWR_BTN_ODL */ |
| 349 | PAD_CFG_NF(GPD3, NONE, DEEP, NF1), |
| 350 | /* GPD4: SLP_S3# ==> SLP_S3_L */ |
| 351 | PAD_CFG_NF(GPD4, NONE, DEEP, NF1), |
| 352 | /* GPD5: SLP_S4# ==> SLP_S4_L */ |
| 353 | PAD_CFG_NF(GPD5, NONE, DEEP, NF1), |
| 354 | /* GPD6: SLP_A# ==> SLP_A_L */ |
| 355 | PAD_CFG_NF(GPD6, NONE, DEEP, NF1), |
| 356 | /* GPD7: GPD7_STRAP */ |
| 357 | PAD_NC(GPD7, NONE), |
| 358 | /* GPD8: SUSCLK ==> PCH_SUSCLK */ |
| 359 | PAD_CFG_NF(GPD8, NONE, DEEP, NF1), |
| 360 | /* GPD9: SLP_WLAN# ==> SLP_WLAN_L */ |
| 361 | PAD_CFG_NF(GPD9, NONE, DEEP, NF1), |
| 362 | /* GPD10: SLP_S5# ==> SLP_S5_L */ |
| 363 | PAD_CFG_NF(GPD10, NONE, DEEP, NF1), |
| 364 | /* GPD11: LANPHYC ==> WWAN_CONFIG1 */ |
| 365 | PAD_CFG_GPI(GPD11, NONE, DEEP), |
Eric Lai | 5e053af | 2020-11-26 12:58:10 +0800 | [diff] [blame] | 366 | }; |
| 367 | |
| 368 | /* Early pad configuration in bootblock */ |
| 369 | static const struct pad_config early_gpio_table[] = { |
Eric Lai | a239691 | 2020-12-04 12:08:50 +0800 | [diff] [blame] | 370 | /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ |
| 371 | PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), |
| 372 | /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ |
| 373 | PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), |
| 374 | /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ |
| 375 | PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), |
| 376 | /* E0 : SATAXPCIE0 ==> WWAN_PERST_L */ |
| 377 | PAD_CFG_GPO(GPP_E0, 0, DEEP), |
| 378 | /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ |
| 379 | PAD_CFG_GPI(GPP_E13, NONE, DEEP), |
| 380 | /* E15 : RSVD_TP ==> PCH_WP_OD */ |
| 381 | PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), |
| 382 | /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ |
| 383 | PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), |
| 384 | /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ |
| 385 | PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), |
Eric Lai | 5e053af | 2020-11-26 12:58:10 +0800 | [diff] [blame] | 386 | }; |
| 387 | |
| 388 | const struct pad_config *__weak variant_gpio_table(size_t *num) |
| 389 | { |
| 390 | *num = ARRAY_SIZE(gpio_table); |
| 391 | return gpio_table; |
| 392 | } |
| 393 | |
| 394 | const struct pad_config *__weak variant_early_gpio_table(size_t *num) |
| 395 | { |
| 396 | *num = ARRAY_SIZE(early_gpio_table); |
| 397 | return early_gpio_table; |
| 398 | } |
Eric Lai | b052c4b | 2020-11-27 13:50:02 +0800 | [diff] [blame] | 399 | |
| 400 | static const struct cros_gpio cros_gpios[] = { |
Tim Wawrzynczak | 885e84e | 2021-03-05 15:44:42 -0700 | [diff] [blame] | 401 | CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), |
| 402 | CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), |
Eric Lai | b052c4b | 2020-11-27 13:50:02 +0800 | [diff] [blame] | 403 | }; |
| 404 | |
| 405 | const struct cros_gpio *__weak variant_cros_gpios(size_t *num) |
| 406 | { |
| 407 | *num = ARRAY_SIZE(cros_gpios); |
| 408 | return cros_gpios; |
| 409 | } |