Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | #include <console/console.h> |
| 18 | #include <arch/io.h> |
| 19 | #include <stdint.h> |
| 20 | #include <device/device.h> |
| 21 | #include <device/pci.h> |
| 22 | #include <device/pci_ids.h> |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 23 | #include <stdlib.h> |
| 24 | #include <string.h> |
| 25 | #include <cpu/cpu.h> |
| 26 | #include <boot/tables.h> |
| 27 | #include <arch/acpi.h> |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 28 | #include <northbridge/intel/x4x/iomap.h> |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 29 | #include <northbridge/intel/x4x/chip.h> |
| 30 | #include <northbridge/intel/x4x/x4x.h> |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 31 | |
Arthur Heymans | 4c4f56a | 2017-02-27 13:46:11 +0100 | [diff] [blame] | 32 | static const int legacy_hole_base_k = 0xa0000 / 1024; |
| 33 | |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 34 | static void mch_domain_read_resources(device_t dev) |
| 35 | { |
Arthur Heymans | 4c4f56a | 2017-02-27 13:46:11 +0100 | [diff] [blame] | 36 | u8 index, reg8; |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 37 | u64 tom, touud; |
Arthur Heymans | 4c4f56a | 2017-02-27 13:46:11 +0100 | [diff] [blame] | 38 | u32 tomk, tseg_sizek = 0, tolud; |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 39 | u32 pcie_config_base, pcie_config_size; |
| 40 | u32 uma_sizek = 0; |
| 41 | |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 42 | const u32 top32memk = 4 * (GiB / KiB); |
| 43 | index = 3; |
| 44 | |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 45 | pci_domain_read_resources(dev); |
| 46 | |
| 47 | /* Top of Upper Usable DRAM, including remap */ |
| 48 | touud = pci_read_config16(dev, D0F0_TOUUD); |
| 49 | touud <<= 20; |
| 50 | |
| 51 | /* Top of Lower Usable DRAM */ |
| 52 | tolud = pci_read_config16(dev, D0F0_TOLUD) & 0xfff0; |
| 53 | tolud <<= 16; |
| 54 | |
| 55 | /* Top of Memory - does not account for any UMA */ |
| 56 | tom = pci_read_config16(dev, D0F0_TOM) & 0x01ff; |
| 57 | tom <<= 26; |
| 58 | |
| 59 | printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n", |
| 60 | touud, tolud, tom); |
| 61 | |
| 62 | tomk = tolud >> 10; |
| 63 | |
| 64 | /* Graphics memory comes next */ |
Arthur Heymans | 4c4f56a | 2017-02-27 13:46:11 +0100 | [diff] [blame] | 65 | |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 66 | const u16 ggc = pci_read_config16(dev, D0F0_GGC); |
| 67 | printk(BIOS_DEBUG, "IGD decoded, subtracting "); |
| 68 | |
| 69 | /* Graphics memory */ |
| 70 | const u32 gms_sizek = decode_igd_memory_size((ggc >> 4) & 0xf); |
| 71 | printk(BIOS_DEBUG, "%uM UMA", gms_sizek >> 10); |
Arthur Heymans | 4c4f56a | 2017-02-27 13:46:11 +0100 | [diff] [blame] | 72 | tomk -= gms_sizek; |
| 73 | uma_sizek += gms_sizek; |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 74 | |
| 75 | /* GTT Graphics Stolen Memory Size (GGMS) */ |
| 76 | const u32 gsm_sizek = decode_igd_gtt_size((ggc >> 8) & 0xf); |
| 77 | printk(BIOS_DEBUG, " and %uM GTT\n", gsm_sizek >> 10); |
Arthur Heymans | 4c4f56a | 2017-02-27 13:46:11 +0100 | [diff] [blame] | 78 | tomk -= gsm_sizek; |
| 79 | uma_sizek += gsm_sizek; |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 80 | |
Arthur Heymans | 4c4f56a | 2017-02-27 13:46:11 +0100 | [diff] [blame] | 81 | printk(BIOS_DEBUG, "TSEG decoded, subtracting "); |
| 82 | reg8 = pci_read_config8(dev, D0F0_ESMRAMC); |
| 83 | reg8 >>= 1; |
| 84 | reg8 &= 3; |
| 85 | switch (reg8) { |
| 86 | case 0: |
| 87 | tseg_sizek = 1024; |
| 88 | break; /* TSEG = 1M */ |
| 89 | case 1: |
| 90 | tseg_sizek = 2048; |
| 91 | break; /* TSEG = 2M */ |
| 92 | case 2: |
| 93 | tseg_sizek = 8192; |
| 94 | break; /* TSEG = 8M */ |
| 95 | } |
| 96 | uma_sizek += tseg_sizek; |
| 97 | tomk -= tseg_sizek; |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 98 | |
Arthur Heymans | 4c4f56a | 2017-02-27 13:46:11 +0100 | [diff] [blame] | 99 | printk(BIOS_DEBUG, "%dM\n", tseg_sizek >> 10); |
| 100 | |
| 101 | printk(BIOS_INFO, "Available memory below 4GB: %uM\n", tomk >> 10); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 102 | |
| 103 | /* Report the memory regions */ |
Arthur Heymans | 4c4f56a | 2017-02-27 13:46:11 +0100 | [diff] [blame] | 104 | ram_resource(dev, index++, 0, legacy_hole_base_k); |
| 105 | mmio_resource(dev, index++, legacy_hole_base_k, |
| 106 | (0xc0000 >> 10) - legacy_hole_base_k); |
| 107 | reserved_ram_resource(dev, index++, 0xc0000 >> 10, |
| 108 | (0x100000 - 0xc0000) >> 10); |
| 109 | ram_resource(dev, index++, 0x100000 >> 10, (tomk - (0x100000 >> 10))); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 110 | |
| 111 | /* |
| 112 | * If >= 4GB installed then memory from TOLUD to 4GB |
| 113 | * is remapped above TOM, TOUUD will account for both |
| 114 | */ |
| 115 | touud >>= 10; /* Convert to KB */ |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 116 | if (touud > top32memk) { |
| 117 | ram_resource(dev, index++, top32memk, touud - top32memk); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 118 | printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 119 | (touud - top32memk) >> 10); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 120 | } |
| 121 | |
| 122 | printk(BIOS_DEBUG, "Adding UMA memory area base=0x%08x " |
Arthur Heymans | 4c4f56a | 2017-02-27 13:46:11 +0100 | [diff] [blame] | 123 | "size=0x%08x\n", tomk << 10, uma_sizek << 10); |
| 124 | uma_resource(dev, index++, tomk, uma_sizek); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 125 | |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 126 | /* Reserve high memory where the NB BARs are up to 4GiB */ |
| 127 | fixed_mem_resource(dev, index++, DEFAULT_HECIBAR >> 10, |
| 128 | top32memk - (DEFAULT_HECIBAR >> 10), |
| 129 | IORESOURCE_RESERVE); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 130 | |
| 131 | if (decode_pciebar(&pcie_config_base, &pcie_config_size)) { |
| 132 | printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " |
| 133 | "size=0x%x\n", pcie_config_base, pcie_config_size); |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 134 | fixed_mem_resource(dev, index++, pcie_config_base >> 10, |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 135 | pcie_config_size >> 10, IORESOURCE_RESERVE); |
| 136 | } |
| 137 | } |
| 138 | |
| 139 | static void mch_domain_set_resources(device_t dev) |
| 140 | { |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 141 | struct resource *res; |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 142 | |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 143 | for (res = dev->resource_list; res; res = res->next) |
| 144 | report_resource_stored(dev, res, ""); |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 145 | |
| 146 | assign_resources(dev->link_list); |
| 147 | } |
| 148 | |
| 149 | static void mch_domain_init(device_t dev) |
| 150 | { |
| 151 | u32 reg32; |
| 152 | |
| 153 | /* Enable SERR */ |
| 154 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 155 | reg32 |= PCI_COMMAND_SERR; |
| 156 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 157 | } |
| 158 | |
| 159 | static struct device_operations pci_domain_ops = { |
| 160 | .read_resources = mch_domain_read_resources, |
| 161 | .set_resources = mch_domain_set_resources, |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 162 | .init = mch_domain_init, |
| 163 | .scan_bus = pci_domain_scan_bus, |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 164 | .ops_pci_bus = pci_bus_default_ops, |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 165 | .write_acpi_tables = northbridge_write_acpi_tables, |
| 166 | .acpi_fill_ssdt_generator = generate_cpu_entries, |
| 167 | }; |
| 168 | |
| 169 | |
| 170 | static void cpu_bus_init(device_t dev) |
| 171 | { |
| 172 | initialize_cpus(dev->link_list); |
| 173 | } |
| 174 | |
| 175 | static struct device_operations cpu_bus_ops = { |
| 176 | .read_resources = DEVICE_NOOP, |
| 177 | .set_resources = DEVICE_NOOP, |
| 178 | .enable_resources = DEVICE_NOOP, |
| 179 | .init = cpu_bus_init, |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 180 | }; |
| 181 | |
| 182 | |
| 183 | static void enable_dev(device_t dev) |
| 184 | { |
| 185 | /* Set the operations if it is a special bus type */ |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 186 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 187 | dev->ops = &pci_domain_ops; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 188 | else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 189 | dev->ops = &cpu_bus_ops; |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 190 | } |
| 191 | |
| 192 | static void x4x_init(void *const chip_info) |
| 193 | { |
| 194 | int dev, fn, bit_base; |
| 195 | |
| 196 | struct device *const d0f0 = dev_find_slot(0, 0); |
| 197 | |
| 198 | /* Hide internal functions based on devicetree info. */ |
Arthur Heymans | 293445a | 2017-02-27 21:45:07 +0100 | [diff] [blame] | 199 | for (dev = 6; dev > 0; --dev) { |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 200 | switch (dev) { |
Arthur Heymans | 293445a | 2017-02-27 21:45:07 +0100 | [diff] [blame] | 201 | case 6: /* PEG1: only on P45 */ |
| 202 | fn = 0; |
| 203 | bit_base = 13; |
| 204 | break; |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 205 | case 3: /* ME */ |
| 206 | fn = 3; |
| 207 | bit_base = 6; |
| 208 | break; |
| 209 | case 2: /* IGD */ |
| 210 | fn = 1; |
| 211 | bit_base = 3; |
| 212 | break; |
Arthur Heymans | 293445a | 2017-02-27 21:45:07 +0100 | [diff] [blame] | 213 | case 1: /* PEG0 */ |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 214 | fn = 0; |
| 215 | bit_base = 1; |
| 216 | break; |
Arthur Heymans | 293445a | 2017-02-27 21:45:07 +0100 | [diff] [blame] | 217 | case 4: /* Nothing to do */ |
| 218 | case 5: |
| 219 | continue; |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 220 | } |
| 221 | for (; fn >= 0; --fn) { |
| 222 | const struct device *const d = |
| 223 | dev_find_slot(0, PCI_DEVFN(dev, fn)); |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 224 | if (!d || d->enabled) |
| 225 | continue; |
Damien Zammit | 43a1f78 | 2015-08-19 15:16:59 +1000 | [diff] [blame] | 226 | const u32 deven = pci_read_config32(d0f0, D0F0_DEVEN); |
| 227 | pci_write_config32(d0f0, D0F0_DEVEN, |
| 228 | deven & ~(1 << (bit_base + fn))); |
| 229 | } |
| 230 | } |
| 231 | |
| 232 | const u32 deven = pci_read_config32(d0f0, D0F0_DEVEN); |
| 233 | if (!(deven & (0xf << 6))) |
| 234 | pci_write_config32(d0f0, D0F0_DEVEN, deven & ~(1 << 14)); |
| 235 | } |
| 236 | |
| 237 | struct chip_operations northbridge_intel_x4x_ops = { |
| 238 | CHIP_NAME("Intel 4-Series Northbridge") |
| 239 | .enable_dev = enable_dev, |
| 240 | .init = x4x_init, |
| 241 | }; |