Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2014 Damien Zammit <damien@zamaudio.com> |
| 5 | * Copyright (C) 2014 Vladimir Serbinenko <phcoder@gmail.com> |
| 6 | * Copyright (C) 2016 Patrick Rudolph <siro@das-labor.org> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | */ |
| 17 | |
| 18 | #ifndef RAMINIT_COMMON_H |
| 19 | #define RAMINIT_COMMON_H |
| 20 | |
| 21 | #define BASEFREQ 133 |
| 22 | #define tDLLK 512 |
| 23 | |
| 24 | #define IS_SANDY_CPU(x) ((x & 0xffff0) == 0x206a0) |
| 25 | #define IS_SANDY_CPU_C(x) ((x & 0xf) == 4) |
| 26 | #define IS_SANDY_CPU_D0(x) ((x & 0xf) == 5) |
| 27 | #define IS_SANDY_CPU_D1(x) ((x & 0xf) == 6) |
| 28 | #define IS_SANDY_CPU_D2(x) ((x & 0xf) == 7) |
| 29 | |
| 30 | #define IS_IVY_CPU(x) ((x & 0xffff0) == 0x306a0) |
| 31 | #define IS_IVY_CPU_C(x) ((x & 0xf) == 4) |
| 32 | #define IS_IVY_CPU_K(x) ((x & 0xf) == 5) |
| 33 | #define IS_IVY_CPU_D(x) ((x & 0xf) == 6) |
| 34 | #define IS_IVY_CPU_E(x) ((x & 0xf) >= 8) |
| 35 | |
| 36 | #define NUM_CHANNELS 2 |
| 37 | #define NUM_SLOTRANKS 4 |
| 38 | #define NUM_SLOTS 2 |
| 39 | #define NUM_LANES 8 |
| 40 | |
| 41 | /* FIXME: Vendor BIOS uses 64 but our algorithms are less |
| 42 | performant and even 1 seems to be enough in practice. */ |
| 43 | #define NUM_PATTERNS 4 |
| 44 | |
| 45 | typedef struct odtmap_st { |
| 46 | u16 rttwr; |
| 47 | u16 rttnom; |
| 48 | } odtmap; |
| 49 | |
| 50 | typedef struct dimm_info_st { |
| 51 | dimm_attr dimm[NUM_CHANNELS][NUM_SLOTS]; |
| 52 | } dimm_info; |
| 53 | |
| 54 | struct ram_rank_timings { |
| 55 | /* Register 4024. One byte per slotrank. */ |
| 56 | u8 val_4024; |
| 57 | /* Register 4028. One nibble per slotrank. */ |
| 58 | u8 val_4028; |
| 59 | |
| 60 | int val_320c; |
| 61 | |
| 62 | struct ram_lane_timings { |
| 63 | /* lane register offset 0x10. */ |
| 64 | u16 timA; /* bits 0 - 5, bits 16 - 18 */ |
| 65 | u8 rising; /* bits 8 - 14 */ |
| 66 | u8 falling; /* bits 20 - 26. */ |
| 67 | |
| 68 | /* lane register offset 0x20. */ |
| 69 | int timC; /* bit 0 - 5, 19. */ |
| 70 | u16 timB; /* bits 8 - 13, 15 - 17. */ |
| 71 | } lanes[NUM_LANES]; |
| 72 | }; |
| 73 | |
| 74 | struct ramctr_timing_st; |
| 75 | |
| 76 | typedef struct ramctr_timing_st { |
| 77 | u16 spd_crc[NUM_CHANNELS][NUM_SLOTS]; |
| 78 | int mobile; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 79 | int sandybridge; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 80 | |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 81 | /* DDR base_freq = 100 Mhz / 133 Mhz */ |
| 82 | u8 base_freq; |
| 83 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 84 | u16 cas_supported; |
| 85 | /* tLatencies are in units of ns, scaled by x256 */ |
| 86 | u32 tCK; |
| 87 | u32 tAA; |
| 88 | u32 tWR; |
| 89 | u32 tRCD; |
| 90 | u32 tRRD; |
| 91 | u32 tRP; |
| 92 | u32 tRAS; |
| 93 | u32 tRFC; |
| 94 | u32 tWTR; |
| 95 | u32 tRTP; |
| 96 | u32 tFAW; |
Dan Elkouby | dabebc3 | 2018-04-13 18:47:10 +0300 | [diff] [blame] | 97 | u32 tCWL; |
| 98 | u32 tCMD; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 99 | /* Latencies in terms of clock cycles |
| 100 | * They are saved separately as they are needed for DRAM MRS commands*/ |
| 101 | u8 CAS; /* CAS read latency */ |
| 102 | u8 CWL; /* CAS write latency */ |
| 103 | |
| 104 | u32 tREFI; |
| 105 | u32 tMOD; |
| 106 | u32 tXSOffset; |
| 107 | u32 tWLO; |
| 108 | u32 tCKE; |
| 109 | u32 tXPDLL; |
| 110 | u32 tXP; |
| 111 | u32 tAONPD; |
| 112 | |
| 113 | u16 reg_5064b0; /* bits 0-11. */ |
| 114 | |
| 115 | u8 rankmap[NUM_CHANNELS]; |
| 116 | int ref_card_offset[NUM_CHANNELS]; |
| 117 | u32 mad_dimm[NUM_CHANNELS]; |
| 118 | int channel_size_mb[NUM_CHANNELS]; |
| 119 | u32 cmd_stretch[NUM_CHANNELS]; |
| 120 | |
| 121 | int reg_c14_offset; |
| 122 | int reg_320c_range_threshold; |
| 123 | |
| 124 | int edge_offset[3]; |
| 125 | int timC_offset[3]; |
| 126 | |
| 127 | int extended_temperature_range; |
| 128 | int auto_self_refresh; |
| 129 | |
| 130 | int rank_mirror[NUM_CHANNELS][NUM_SLOTRANKS]; |
| 131 | |
| 132 | struct ram_rank_timings timings[NUM_CHANNELS][NUM_SLOTRANKS]; |
| 133 | |
| 134 | dimm_info info; |
| 135 | } ramctr_timing; |
| 136 | |
| 137 | #define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0) |
| 138 | #define NORTHBRIDGE PCI_DEV(0, 0x0, 0) |
| 139 | #define FOR_ALL_LANES for (lane = 0; lane < NUM_LANES; lane++) |
| 140 | #define FOR_ALL_CHANNELS for (channel = 0; channel < NUM_CHANNELS; channel++) |
| 141 | #define FOR_ALL_POPULATED_RANKS for (slotrank = 0; slotrank < NUM_SLOTRANKS; slotrank++) if (ctrl->rankmap[channel] & (1 << slotrank)) |
| 142 | #define FOR_ALL_POPULATED_CHANNELS for (channel = 0; channel < NUM_CHANNELS; channel++) if (ctrl->rankmap[channel]) |
| 143 | #define MAX_EDGE_TIMING 71 |
| 144 | #define MAX_TIMC 127 |
| 145 | #define MAX_TIMB 511 |
| 146 | #define MAX_TIMA 127 |
| 147 | #define MAX_CAS 18 |
| 148 | #define MIN_CAS 4 |
| 149 | |
| 150 | #define MAKE_ERR ((channel<<16)|(slotrank<<8)|1) |
| 151 | #define GET_ERR_CHANNEL(x) (x>>16) |
| 152 | |
Patrick Rudolph | 652c491 | 2017-10-31 11:36:55 +0100 | [diff] [blame^] | 153 | #define MC_BIOS_REQ 0x5e00 |
| 154 | #define MC_BIOS_DATA 0x5e04 |
| 155 | #define PM_PDWN_Config 0x4cb0 |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 156 | |
| 157 | u8 get_CWL(u32 tCK); |
| 158 | void dram_mrscommands(ramctr_timing * ctrl); |
| 159 | void program_timings(ramctr_timing * ctrl, int channel); |
| 160 | void dram_find_common_params(ramctr_timing *ctrl); |
| 161 | void dram_xover(ramctr_timing * ctrl); |
| 162 | void dram_timing_regs(ramctr_timing * ctrl); |
| 163 | void dram_dimm_mapping(ramctr_timing *ctrl); |
| 164 | void dram_dimm_set_mapping(ramctr_timing * ctrl); |
| 165 | void dram_zones(ramctr_timing * ctrl, int training); |
| 166 | unsigned int get_mem_min_tck(void); |
| 167 | void dram_memorymap(ramctr_timing * ctrl, int me_uma_size); |
| 168 | void dram_jedecreset(ramctr_timing * ctrl); |
| 169 | int read_training(ramctr_timing * ctrl); |
| 170 | int write_training(ramctr_timing * ctrl); |
| 171 | int command_training(ramctr_timing *ctrl); |
| 172 | int discover_edges(ramctr_timing *ctrl); |
| 173 | int discover_edges_write(ramctr_timing *ctrl); |
| 174 | int discover_timC_write(ramctr_timing *ctrl); |
| 175 | void normalize_training(ramctr_timing * ctrl); |
| 176 | void write_controller_mr(ramctr_timing * ctrl); |
| 177 | int channel_test(ramctr_timing *ctrl); |
| 178 | void set_scrambling_seed(ramctr_timing * ctrl); |
| 179 | void set_4f8c(void); |
| 180 | void prepare_training(ramctr_timing * ctrl); |
| 181 | void set_4008c(ramctr_timing * ctrl); |
| 182 | void set_42a0(ramctr_timing * ctrl); |
| 183 | void final_registers(ramctr_timing * ctrl); |
| 184 | void restore_timings(ramctr_timing * ctrl); |
| 185 | |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 186 | int try_init_dram_ddr3_sandy(ramctr_timing *ctrl, int fast_boot, |
| 187 | int s3_resume, int me_uma_size); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 188 | |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 189 | int try_init_dram_ddr3_ivy(ramctr_timing *ctrl, int fast_boot, |
| 190 | int s3_resume, int me_uma_size); |
| 191 | |
| 192 | #endif |