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Mario Scheithauer66038c82018-09-25 17:26:32 +02001chip soc/intel/apollolake
2
Mario Scheithauer66038c82018-09-25 17:26:32 +02003 register "sci_irq" = "SCIS_IRQ10"
Mario Scheithauer66038c82018-09-25 17:26:32 +02004
Mario Scheithauer66038c82018-09-25 17:26:32 +02005 # EMMC TX DATA Delay 1
6 # Refer to EDS-Vol2-22.3.
7 # [14:8] steps of delay for HS400, each 125ps.
8 # [6:0] steps of delay for SDR104/HS200, each 125ps.
9 register "emmc_tx_data_cntl1" = "0x0C16"
10
11 # EMMC TX DATA Delay 2
12 # Refer to EDS-Vol2-22.3.
13 # [30:24] steps of delay for SDR50, each 125ps.
14 # [22:16] steps of delay for DDR50, each 125ps.
15 # [14:8] steps of delay for SDR25/HS50, each 125ps.
16 # [6:0] steps of delay for SDR12, each 125ps.
17 register "emmc_tx_data_cntl2" = "0x28162828"
18
19 # EMMC RX CMD/DATA Delay 1
20 # Refer to EDS-Vol2-22.3.
21 # [30:24] steps of delay for SDR50, each 125ps.
22 # [22:16] steps of delay for DDR50, each 125ps.
23 # [14:8] steps of delay for SDR25/HS50, each 125ps.
24 # [6:0] steps of delay for SDR12, each 125ps.
25 register "emmc_rx_cmd_data_cntl1" = "0x00181717"
26
27 # EMMC RX CMD/DATA Delay 2
28 # Refer to EDS-Vol2-22.3.
29 # [17:16] stands for Rx Clock before Output Buffer
30 # [14:8] steps of delay for Auto Tuning Mode, each 125ps.
31 # [6:0] steps of delay for HS200, each 125ps.
32 register "emmc_rx_cmd_data_cntl2" = "0x10008"
33
34 # 0:HS400(Default), 1:HS200, 2:DDR50
Mario Scheithauer1f21a962019-07-10 13:15:54 +020035 register "emmc_host_max_speed" = "1"
Mario Scheithauer66038c82018-09-25 17:26:32 +020036
Werner Zehd7e5f4b2019-02-01 12:39:40 +010037 # Enable Vtd feature
38 register "enable_vtd" = "1"
39
Werner Zeh45f44942021-04-27 11:40:17 +020040 # I2C3 controller used for RTC
41 register "common_soc_config" = "{
42 .i2c[3] = {
43 .speed = I2C_SPEED_STANDARD,
44 .rise_time_ns = 60,
45 .fall_time_ns = 20,
Werner Zeha67bda32021-05-31 07:15:36 +020046 .data_hold_time_ns = 300,
47 .speed_config[0] = {
48 .speed = I2C_SPEED_FAST,
49 .scl_hcnt = 0x68,
50 .scl_lcnt = 0xd4,
51 .sda_hold = 0x28
52 },
Werner Zeh45f44942021-04-27 11:40:17 +020053 },
54 }"
55
Mario Scheithauer66038c82018-09-25 17:26:32 +020056 device domain 0 on
57 device pci 00.0 on end # - Host Bridge
58 device pci 00.1 off end # - DPTF
59 device pci 00.2 off end # - NPK
60 device pci 02.0 on end # - Gen - Display
61 device pci 03.0 off end # - Iunit
62 device pci 0d.0 on end # - P2SB
63 device pci 0d.1 off end # - PMC
64 device pci 0d.2 on end # - SPI
65 device pci 0d.3 off end # - Shared SRAM
Werner Zeha4e52362019-04-12 09:10:27 +020066 device pci 0e.0 on end # - Audio
Subrata Banike9b93732020-09-17 15:48:54 +053067 device pci 0f.0 on end # - CSE
Mario Scheithauer66038c82018-09-25 17:26:32 +020068 device pci 11.0 on end # - ISH
Mario Scheithauerf0232702022-01-26 11:53:00 +010069 device pci 12.0 on # - SATA
Sean Rhodes57779952022-05-19 15:35:31 +010070 register "SataPortsEnable[0]" = "1"
71 register "SataPortsEnable[1]" = "1"
Mario Scheithauerf0232702022-01-26 11:53:00 +010072 register "DisableSataSalpSupport" = "1"
73 end
Mario Scheithauer92e4ed12021-01-14 14:54:38 +010074 device pci 13.0 on # - RP 2 - PCIe A 0
75 register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
76 register "pcie_rp_hotplug_enable[2]" = "0"
77 end
78 device pci 13.1 on # - RP 3 - PCIe A 1
79 register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED"
80 register "pcie_rp_hotplug_enable[3]" = "0"
81 end
82 device pci 13.2 on # - RP 4 - PCIe-A 2
83 register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
84 register "pcie_rp_hotplug_enable[4]" = "0"
85 end
86 device pci 13.3 on # - RP 5 - PCIe-A 3
87 register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
88 register "pcie_rp_hotplug_enable[5]" = "0"
89 end
90 device pci 14.0 on # - RP 0 - PCIe-B 0
91 register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED"
92 register "pcie_rp_hotplug_enable[0]" = "0"
93 end
94 device pci 14.1 on # - RP 1 - PCIe-B 1
95 register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED"
96 register "pcie_rp_hotplug_enable[1]" = "0"
97 end
Mario Scheithauer66038c82018-09-25 17:26:32 +020098 device pci 15.0 on end # - XHCI
99 device pci 15.1 off end # - XDCI
Werner Zeh6f74d382022-02-21 07:52:13 +0100100 device pci 16.0 on end # - I2C 0
Werner Zehb2bb9592021-05-31 07:27:50 +0200101 device pci 16.1 off end # - I2C 1
102 device pci 16.2 off end # - I2C 2
Mario Scheithauer1cd95b02021-02-08 13:45:26 +0100103 device pci 16.3 on # - I2C 3
Mario Scheithauer66038c82018-09-25 17:26:32 +0200104 # Enable external RTC chip
105 chip drivers/i2c/rx6110sa
106 register "pmon_sampling" = "PMON_SAMPL_256_MS"
107 register "bks_on" = "0"
108 register "bks_off" = "1"
109 register "iocut_en" = "1"
110 register "set_user_date" = "1"
111 register "user_year" = "04"
112 register "user_month" = "07"
113 register "user_day" = "01"
114 register "user_weekday" = "4"
115 device i2c 0x32 on end # RTC RX6110 SA
116 end
117 end
Werner Zehb2bb9592021-05-31 07:27:50 +0200118 device pci 17.0 off end # - I2C 4
119 device pci 17.1 off end # - I2C 5
120 device pci 17.2 off end # - I2C 6
121 device pci 17.3 off end # - I2C 7
Mario Scheithauerddf84982019-01-29 08:38:54 +0100122 device pci 18.0 on end # - UART 0
123 device pci 18.1 on end # - UART 1
124 device pci 18.2 on end # - UART 2
125 device pci 18.3 on end # - UART 3
Mario Scheithauer66038c82018-09-25 17:26:32 +0200126 device pci 19.0 off end # - SPI 0
127 device pci 19.1 off end # - SPI 1
128 device pci 19.2 off end # - SPI 2
129 device pci 1a.0 off end # - PWM
130 device pci 1b.0 on end # - SDCARD
131 device pci 1c.0 on end # - eMMC
132 device pci 1d.0 off end # - UFS
133 device pci 1e.0 off end # - SDIO
Mario Scheithauer67be4912019-01-28 16:18:45 +0100134 device pci 1f.0 on # - LPC
135 chip drivers/pc80/tpm
136 device pnp 0c31.0 on end
137 end
138 end
Mario Scheithauer66038c82018-09-25 17:26:32 +0200139 device pci 1f.1 on end # - SMBUS
140 end
141end