Hannah Williams | d59f62b | 2017-05-05 16:39:21 -0700 | [diff] [blame] | 1 | chip soc/intel/apollolake |
| 2 | |
Furquan Shaikh | 6d5e10c | 2018-03-14 19:57:16 -0700 | [diff] [blame] | 3 | register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED" |
Hannah Williams | d59f62b | 2017-05-05 16:39:21 -0700 | [diff] [blame] | 4 | # Disable unused clkreq of PCIe root ports |
Furquan Shaikh | 6d5e10c | 2018-03-14 19:57:16 -0700 | [diff] [blame] | 5 | register "pcie_rp_clkreq_pin[1]" = "3" # wifi/bt |
| 6 | register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" |
| 7 | register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED" |
Roy Mingi Park | a6ab9af | 2018-03-01 11:09:58 -0800 | [diff] [blame] | 8 | register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" |
Furquan Shaikh | 6d5e10c | 2018-03-14 19:57:16 -0700 | [diff] [blame] | 9 | register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" |
Hannah Williams | d59f62b | 2017-05-05 16:39:21 -0700 | [diff] [blame] | 10 | |
| 11 | # GPIO for PERST_0 |
| 12 | # If the Board has PERST_0 signal, assign the GPIO |
| 13 | # If the Board does not have PERST_0, assign GPIO_PRT0_UDEF |
Roy Mingi Park | a6ab9af | 2018-03-01 11:09:58 -0800 | [diff] [blame] | 14 | register "prt0_gpio" = "GPIO_163" |
Hannah Williams | d59f62b | 2017-05-05 16:39:21 -0700 | [diff] [blame] | 15 | |
| 16 | # GPIO for SD card detect |
| 17 | register "sdcard_cd_gpio" = "GPIO_186" |
| 18 | |
| 19 | # EMMC TX DATA Delay 1 |
| 20 | # Refer to EDS-Vol2-22.3. |
| 21 | # [14:8] steps of delay for HS400, each 125ps. |
| 22 | # [6:0] steps of delay for SDR104/HS200, each 125ps. |
| 23 | register "emmc_tx_data_cntl1" = "0x0C3A" |
| 24 | |
| 25 | # EMMC TX DATA Delay 2 |
| 26 | # Refer to EDS-Vol2-22.3. |
| 27 | # [30:24] steps of delay for SDR50, each 125ps. |
| 28 | # [22:16] steps of delay for DDR50, each 125ps. |
| 29 | # [14:8] steps of delay for SDR25/HS50, each 125ps. |
| 30 | # [6:0] steps of delay for SDR12, each 125ps. |
| 31 | register "emmc_tx_data_cntl2" = "0x28272929" |
| 32 | |
| 33 | # EMMC RX CMD/DATA Delay 1 |
| 34 | # Refer to EDS-Vol2-22.3. |
| 35 | # [30:24] steps of delay for SDR50, each 125ps. |
| 36 | # [22:16] steps of delay for DDR50, each 125ps. |
| 37 | # [14:8] steps of delay for SDR25/HS50, each 125ps. |
| 38 | # [6:0] steps of delay for SDR12, each 125ps. |
| 39 | register "emmc_rx_cmd_data_cntl1" = "0x003B263B" |
| 40 | |
| 41 | # EMMC RX CMD/DATA Delay 2 |
| 42 | # Refer to EDS-Vol2-22.3. |
| 43 | # [17:16] stands for Rx Clock before Output Buffer |
| 44 | # [14:8] steps of delay for Auto Tuning Mode, each 125ps. |
| 45 | # [6:0] steps of delay for HS200, each 125ps. |
| 46 | register "emmc_rx_cmd_data_cntl2" = "0x10008" |
| 47 | |
| 48 | register "emmc_rx_strobe_cntl" = "0x0a0a" |
| 49 | register "emmc_tx_cmd_cntl" = "0x1305" |
| 50 | |
| 51 | # Enable DPTF |
| 52 | register "dptf_enable" = "1" |
| 53 | |
Cole Nelson | 735779c | 2017-05-18 15:39:22 -0700 | [diff] [blame] | 54 | # PL1 override: 7.5W setting gives a run-time 6W actual |
Hannah Williams | d59f62b | 2017-05-05 16:39:21 -0700 | [diff] [blame] | 55 | # Set RAPL PL2 to 15W. |
Sumeet R Pawnikar | 2adb50d | 2020-05-09 15:37:09 +0530 | [diff] [blame] | 56 | register "power_limits_config" = "{ |
| 57 | .tdp_pl1_override = 7, |
| 58 | .tdp_pl2_override = 15, |
| 59 | }" |
Hannah Williams | d59f62b | 2017-05-05 16:39:21 -0700 | [diff] [blame] | 60 | |
| 61 | # Enable Audio Clock and Power gating |
| 62 | register "hdaudio_clk_gate_enable" = "1" |
| 63 | register "hdaudio_pwr_gate_enable" = "1" |
| 64 | register "hdaudio_bios_config_lockdown" = "1" |
| 65 | |
| 66 | # Enable lpss s0ix |
| 67 | register "lpss_s0ix_enable" = "1" |
| 68 | |
| 69 | # GPE configuration |
| 70 | # Note that GPE events called out in ASL code rely on this |
| 71 | # route, i.e., if this route changes then the affected GPE |
| 72 | # offset bits also need to be changed. This sets the PMC register |
| 73 | # GPE_CFG fields. |
| 74 | #PMC_GPE_NW_63_32 - 03 |
| 75 | #PMC_GPE_N_95_64 - 08 |
| 76 | #PMC_GPE_NW_31_0 - 02 |
| 77 | register "gpe0_dw1" = "PMC_GPE_NW_63_32" |
| 78 | register "gpe0_dw2" = "PMC_GPE_N_95_64" |
| 79 | register "gpe0_dw3" = "PMC_GPE_NW_31_0" |
| 80 | |
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 81 | # Intel Common SoC Config |
| 82 | #+-------------------+---------------------------+ |
| 83 | #| Field | Value | |
| 84 | #+-------------------+---------------------------+ |
| 85 | #| I2C0 | Audio | |
| 86 | #+-------------------+---------------------------+ |
| 87 | register "common_soc_config" = "{ |
| 88 | .i2c[0] = { |
| 89 | .speed = I2C_SPEED_FAST, |
| 90 | .rise_time_ns = 104, |
| 91 | .fall_time_ns = 52, |
| 92 | }, |
Hannah Williams | 7427abc | 2017-06-20 14:31:44 -0700 | [diff] [blame] | 93 | }" |
Hannah Williams | d59f62b | 2017-05-05 16:39:21 -0700 | [diff] [blame] | 94 | |
| 95 | # Minimum SLP S3 assertion width 28ms. |
| 96 | register "slp_s3_assertion_width_usecs" = "28000" |
| 97 | |
Shaunak Saha | cf1ba95 | 2018-03-21 07:39:40 -0700 | [diff] [blame] | 98 | register "pnp_settings" = "PNP_PERF_POWER" |
| 99 | |
Hannah Williams | d59f62b | 2017-05-05 16:39:21 -0700 | [diff] [blame] | 100 | device domain 0 on |
| 101 | device pci 00.0 on end # - Host Bridge |
| 102 | device pci 00.1 on end # - DPTF |
| 103 | device pci 00.2 on end # - NPK |
| 104 | device pci 02.0 on end # - Gen |
| 105 | device pci 03.0 on end # - Iunit |
| 106 | device pci 0c.0 on end # - CNVi |
| 107 | device pci 0d.0 on end # - P2SB |
| 108 | device pci 0d.1 on end # - PMC |
| 109 | device pci 0d.2 on end # - SPI |
| 110 | device pci 0d.3 on end # - Shared SRAM |
Hannah Williams | 7427abc | 2017-06-20 14:31:44 -0700 | [diff] [blame] | 111 | device pci 0e.0 on # - Audio |
| 112 | chip drivers/generic/max98357a |
Aamir Bohra | a1c82c5 | 2020-03-16 18:57:48 +0530 | [diff] [blame] | 113 | register "hid" = ""MX98357A"" |
Hannah Williams | 7427abc | 2017-06-20 14:31:44 -0700 | [diff] [blame] | 114 | register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_160)" |
| 115 | register "sdmode_delay" = "5" |
| 116 | device generic 0 on end |
| 117 | end |
| 118 | end |
Hannah Williams | d59f62b | 2017-05-05 16:39:21 -0700 | [diff] [blame] | 119 | device pci 0f.0 on end # - Heci1 |
| 120 | device pci 0f.1 on end # - Heci2 |
| 121 | device pci 0f.2 on end # - Heci3 |
| 122 | device pci 11.0 off end # - ISH |
Sean Rhodes | 5777995 | 2022-05-19 15:35:31 +0100 | [diff] [blame] | 123 | device pci 12.0 on # - SATA |
| 124 | register "SataPortsEnable[0]" = "1" |
| 125 | register "SataPortsEnable[1]" = "1" |
| 126 | end |
Hannah Williams | d59f62b | 2017-05-05 16:39:21 -0700 | [diff] [blame] | 127 | device pci 13.0 off end # - PCIe-A 0 Slot 1 |
| 128 | device pci 13.1 off end # - PCIe-A 1 |
Roy Mingi Park | a6ab9af | 2018-03-01 11:09:58 -0800 | [diff] [blame] | 129 | device pci 13.2 off end # - PCIe-A 2 Onboard Lan |
Hannah Williams | d59f62b | 2017-05-05 16:39:21 -0700 | [diff] [blame] | 130 | device pci 13.3 off end # - PCIe-A 3 |
Roy Mingi Park | a6ab9af | 2018-03-01 11:09:58 -0800 | [diff] [blame] | 131 | device pci 14.0 off end # - PCIe-B 0 Slot2 |
Hannah Williams | d59f62b | 2017-05-05 16:39:21 -0700 | [diff] [blame] | 132 | device pci 14.1 on end # - PCIe-B 1 Onboard M2 Slot(Wifi/BT) |
| 133 | device pci 15.0 on end # - XHCI |
| 134 | device pci 15.1 off end # - XDCI |
Hannah Williams | 7427abc | 2017-06-20 14:31:44 -0700 | [diff] [blame] | 135 | device pci 16.0 on # - I2C 0 |
| 136 | chip drivers/i2c/da7219 |
| 137 | register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_20_IRQ)" |
| 138 | register "btn_cfg" = "50" |
| 139 | register "mic_det_thr" = "500" |
| 140 | register "jack_ins_deb" = "20" |
| 141 | register "jack_det_rate" = ""32ms_64ms"" |
| 142 | register "jack_rem_deb" = "1" |
| 143 | register "a_d_btn_thr" = "0xa" |
| 144 | register "d_b_btn_thr" = "0x16" |
| 145 | register "b_c_btn_thr" = "0x21" |
| 146 | register "c_mic_btn_thr" = "0x3e" |
| 147 | register "btn_avg" = "4" |
| 148 | register "adc_1bit_rpt" = "1" |
| 149 | register "micbias_lvl" = "2600" |
| 150 | register "mic_amp_in_sel" = ""diff"" |
| 151 | device i2c 1a on end |
| 152 | end |
| 153 | end |
Hannah Williams | d59f62b | 2017-05-05 16:39:21 -0700 | [diff] [blame] | 154 | device pci 16.1 off end # - I2C 1 |
| 155 | device pci 16.2 off end # - I2C 2 |
| 156 | device pci 16.3 off end # - I2C 3 |
Shaunak Saha | ced0864 | 2017-11-29 00:19:54 -0800 | [diff] [blame] | 157 | device pci 17.0 on |
| 158 | chip drivers/i2c/hid |
| 159 | register "generic.hid" = ""ALPS0001"" |
| 160 | register "generic.desc" = ""Touchpad"" |
| 161 | register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_18_IRQ)" |
| 162 | register "hid_desc_reg_offset" = "0x1" |
| 163 | device i2c 2C on end |
| 164 | end |
| 165 | end # I2C 4 |
Hannah Williams | d59f62b | 2017-05-05 16:39:21 -0700 | [diff] [blame] | 166 | device pci 17.1 off end # - I2C 5 |
| 167 | device pci 17.2 off end # - I2C 6 |
| 168 | device pci 17.3 on end # - I2C 7 |
| 169 | device pci 18.0 on end # - UART 0 |
| 170 | device pci 18.1 off end # - UART 1 |
| 171 | device pci 18.2 on end # - UART 2 |
| 172 | device pci 18.3 off end # - UART 3 |
| 173 | device pci 19.0 on end # - SPI 0 |
| 174 | device pci 19.1 on end # - SPI 1 |
| 175 | device pci 19.2 on end # - SPI 2 |
| 176 | device pci 1a.0 on end # - PWM |
| 177 | device pci 1b.0 on end # - SDCARD |
| 178 | device pci 1c.0 on end # - eMMC |
Sean Rhodes | 9088b68 | 2022-06-08 21:41:53 +0100 | [diff] [blame] | 179 | device pci 1d.0 on end # - UFS |
Hannah Williams | d59f62b | 2017-05-05 16:39:21 -0700 | [diff] [blame] | 180 | device pci 1e.0 off end # - SDIO |
| 181 | device pci 1f.0 on # - LPC |
| 182 | chip drivers/pc80/tpm |
| 183 | register "irq_polarity" = "2" |
| 184 | device pnp 0c31.0 on |
| 185 | irq 0x70 = 10 |
| 186 | end |
| 187 | end |
| 188 | chip ec/google/chromeec |
| 189 | device pnp 0c09.0 on end |
| 190 | end |
| 191 | end |
| 192 | device pci 1f.1 on end # - SMBUS |
| 193 | end |
| 194 | end |