Marshall Dawson | f0619f4 | 2020-01-21 21:46:51 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Marshall Dawson | f0619f4 | 2020-01-21 21:46:51 -0700 | [diff] [blame] | 2 | |
| 3 | /* |
| 4 | * These definitions are used to describe PCIe bifurcation and display physical |
| 5 | * connector types connected to the SOC. |
| 6 | */ |
| 7 | |
| 8 | #ifndef __PI_PICASSO_PLATFORM_DESCRIPTORS_H__ |
| 9 | #define __PI_PICASSO_PLATFORM_DESCRIPTORS_H__ |
| 10 | |
| 11 | /* Engine descriptor type */ |
| 12 | typedef enum { |
| 13 | UNUSED_ENGINE = 0x00, // Unused descriptor |
| 14 | PCIE_ENGINE = 0x01, // PCIe port |
| 15 | USB_ENGINE = 0x02, // USB port |
| 16 | SATA_ENGINE = 0x03, // SATA |
| 17 | DP_ENGINE = 0x08, // Digital Display |
| 18 | ETHERNET_ENGINE = 0x10, // Ethernet (GBe, XGBe) |
| 19 | MAX_ENGINE // Max engine type for boundary check. |
| 20 | } dxio_engine_type; |
| 21 | |
| 22 | /* PCIe link capability/speed */ |
| 23 | typedef enum { |
| 24 | GEN_MAX = 0, // Maximum supported |
| 25 | GEN1, |
| 26 | GEN2, |
| 27 | GEN3, |
| 28 | GEN_INVALID // Max Gen for boundary check |
| 29 | } dxio_link_speed_cap; |
| 30 | |
Matt Papageorge | 8107cef | 2020-08-18 16:27:36 -0500 | [diff] [blame] | 31 | /* Upstream Auto Speed Change Allowed */ |
| 32 | typedef enum { |
| 33 | SPDC_DEFAULT = 0, // Enabled for Gen2 and Gen3 |
Felix Held | d9c02cd | 2021-04-01 13:52:29 +0200 | [diff] [blame] | 34 | SPDC_DISABLED, |
Matt Papageorge | 8107cef | 2020-08-18 16:27:36 -0500 | [diff] [blame] | 35 | SPDC_ENABLED, |
| 36 | SPDC_INVALID |
| 37 | } dxio_upstream_auto_speed_change; |
| 38 | |
Marshall Dawson | f0619f4 | 2020-01-21 21:46:51 -0700 | [diff] [blame] | 39 | /* SATA ChannelType initialization */ |
| 40 | typedef enum { |
| 41 | SATA_CHANNEL_OTHER = 0, // Default Channel Type |
| 42 | SATA_CHANNEL_SHORT, // Short Trace Channel Type |
| 43 | SATA_CHANNEL_LONG // Long Trace Channel Type |
| 44 | } dxio_sata_channel_type; |
| 45 | |
| 46 | /* CLKREQ for PCIe type descriptors */ |
| 47 | typedef enum { |
| 48 | CLK_DISABLE = 0x00, |
| 49 | CLK_REQ0, |
| 50 | CLK_REQ1, |
| 51 | CLK_REQ2, |
| 52 | CLK_REQ3, |
| 53 | CLK_REQ4, |
| 54 | CLK_REQ5, |
| 55 | CLK_REQ6, |
| 56 | CLK_REQ7, |
| 57 | CLK_REQ8, |
| 58 | CLK_REQGFX = 0x0c, |
| 59 | } cpm_clk_req; |
| 60 | |
| 61 | /* PCIe link ASPM initialization */ |
| 62 | typedef enum { |
| 63 | ASPM_DISABLED = 0, // Disabled |
| 64 | ASPM_L0s, // PCIe L0s link state |
| 65 | ASPM_L1, // PCIe L1 link state |
| 66 | ASPM_L0sL1, // PCIe L0s & L1 link state |
| 67 | ASPM_MAX // Not valid value, used to verify input |
| 68 | } dxio_aspm_type; |
| 69 | |
| 70 | /* DDI Aux channel */ |
| 71 | typedef enum { |
| 72 | AUX1 = 0, |
| 73 | AUX2, |
| 74 | AUX3, |
| 75 | AUX4, |
| 76 | AUX5, |
| 77 | AUX6, |
| 78 | AUX_MAX // Not valid value, used to verify input |
Felix Held | e84111c | 2021-03-03 22:49:30 +0100 | [diff] [blame] | 79 | } ddi_aux_type; |
Marshall Dawson | f0619f4 | 2020-01-21 21:46:51 -0700 | [diff] [blame] | 80 | |
| 81 | /* DDI Hdp Index */ |
| 82 | typedef enum { |
| 83 | HDP1 = 0, |
| 84 | HDP2, |
| 85 | HDP3, |
| 86 | HDP4, |
| 87 | HDP5, |
| 88 | HDP6, |
| 89 | HDP_MAX // Not valid value, used to verify input |
Felix Held | e84111c | 2021-03-03 22:49:30 +0100 | [diff] [blame] | 90 | } ddi_hdp_type; |
Marshall Dawson | f0619f4 | 2020-01-21 21:46:51 -0700 | [diff] [blame] | 91 | |
| 92 | /* DDI display connector type */ |
| 93 | typedef enum { |
| 94 | DP = 0, // DP |
| 95 | EDP, // eDP |
| 96 | SINGLE_LINK_DVI, // Single Link DVI-D |
| 97 | DUAL_LINK_DVI, // Dual Link DVI-D |
| 98 | HDMI, // HDMI |
| 99 | DP_TO_VGA, // DP-to-VGA |
| 100 | DP_TO_LVDS, // DP-to-LVDS |
| 101 | NUTMEG_DP_TO_VGA, // Hudson-2 NutMeg DP-to-VGA |
| 102 | SINGLE_LINK_DVI_I, // Single Link DVI-I |
| 103 | CRT, // CRT (VGA) |
| 104 | LVDS, // LVDS |
| 105 | EDP_TO_LVDS, // eDP-to-LVDS translator chip without AMD SW init |
| 106 | EDP_TO_LVDS_SW, // eDP-to-LVDS translator which requires AMD SW init |
| 107 | AUTO_DETECT, // VBIOS auto detect connector type |
Felix Held | d9c02cd | 2021-04-01 13:52:29 +0200 | [diff] [blame] | 108 | UNUSED_TYPE, // UnusedType |
Marshall Dawson | f0619f4 | 2020-01-21 21:46:51 -0700 | [diff] [blame] | 109 | MAX_CONNECTOR_TYPE // Not valid value, used to verify input |
Felix Held | e84111c | 2021-03-03 22:49:30 +0100 | [diff] [blame] | 110 | } ddi_connector_type; |
Marshall Dawson | f0619f4 | 2020-01-21 21:46:51 -0700 | [diff] [blame] | 111 | |
Felix Held | 6433517 | 2023-07-12 22:49:49 +0200 | [diff] [blame^] | 112 | /* DDI Descriptor: used for configuring display outputs */ |
Marshall Dawson | f0619f4 | 2020-01-21 21:46:51 -0700 | [diff] [blame] | 113 | typedef struct __packed { |
| 114 | uint8_t connector_type; |
| 115 | uint8_t aux_index; |
| 116 | uint8_t hdp_index; |
| 117 | uint8_t reserved; |
Felix Held | ca428c3 | 2020-06-10 19:05:45 +0200 | [diff] [blame] | 118 | } fsp_ddi_descriptor; |
Marshall Dawson | f0619f4 | 2020-01-21 21:46:51 -0700 | [diff] [blame] | 119 | |
Felix Held | 86db2c7 | 2020-07-21 17:09:31 +0200 | [diff] [blame] | 120 | /* |
| 121 | * Picasso DXIO Descriptor: Used for assigning lanes to PCIe/SATA/XGBE engines, configure |
| 122 | * bifurcation and other settings. Beware that the lane numbers in here are the logical and not |
| 123 | * the physical lane numbers! |
Felix Held | 42d5294 | 2020-07-30 16:13:35 +0200 | [diff] [blame] | 124 | * |
| 125 | * Picasso DXIO lane mapping: |
| 126 | * |
| 127 | * physical | logical | protocol |
| 128 | * ---------|---------|----------- |
| 129 | * GFX[7:0] | [15:8] | PCIe |
| 130 | * GPP[3:0] | [7:4] | PCIe |
| 131 | * GPP[5:4] | [1:0] | PCIe, XGBE |
| 132 | * GPP[7:6] | [3:2] | PCIe, SATA |
| 133 | * |
Felix Held | e2f5fb2 | 2020-07-31 00:13:55 +0200 | [diff] [blame] | 134 | * Picasso supports up to 7 PCIe ports. The 8 GFX PCIe lanes can either be used as an x8 port |
| 135 | * or split into two x4 ports. The GPP general purpose lanes can be used as PCIe x4, x2 and x1 |
| 136 | * ports. The ports can only start at logical lane numbers that are integer multiples of the |
| 137 | * lane width, so for example an x4 port can only start with the logical lane 0, 4, 8 or 12. |
| 138 | * Different ports mustn't overlap or be assigned to the same lane(s). Within ports with the |
| 139 | * same width the one with a higher start logical lane number needs to be assigned to a higher |
| 140 | * PCIe root port number; ports of the same size don't have to be assigned to consecutive PCIe |
| 141 | * root ports though. |
| 142 | * |
| 143 | * Dali only supports up to 5 PCIe ports and has less DXIO connectivity than Picasso: |
Felix Held | 42d5294 | 2020-07-30 16:13:35 +0200 | [diff] [blame] | 144 | * |
| 145 | * physical | logical | protocol |
| 146 | * ---------|---------|----------- |
| 147 | * GFX[3:0] | [11:8] | PCIe |
| 148 | * GPP[1:0] | [5:4] | PCIe |
| 149 | * GPP[5:4] | [1:0] | PCIe, XGBE |
| 150 | * GPP[7:6] | [3:2] | SATA |
| 151 | * |
| 152 | * Pollock has even less DXIO lanes and the mapping of GPP lane numbers to the logical lane |
| 153 | * numbers differs to Picasso/Dali: |
| 154 | * |
| 155 | * physical | logical | protocol |
| 156 | * ---------|---------|---------- |
| 157 | * GPP[1:0] | [1:0] | PCIe |
| 158 | * GPP[3:2] | [5:4] | PCIe |
Felix Held | 86db2c7 | 2020-07-21 17:09:31 +0200 | [diff] [blame] | 159 | */ |
Marshall Dawson | f0619f4 | 2020-01-21 21:46:51 -0700 | [diff] [blame] | 160 | typedef struct __packed { |
Matt Papageorge | 8107cef | 2020-08-18 16:27:36 -0500 | [diff] [blame] | 161 | uint8_t engine_type; // See dxio_engine_type |
Felix Held | a19d986 | 2020-07-20 15:46:56 +0200 | [diff] [blame] | 162 | uint8_t start_logical_lane; // Start lane of the pci device |
| 163 | uint8_t end_logical_lane; // End lane of the pci device |
Matt Papageorge | 8107cef | 2020-08-18 16:27:36 -0500 | [diff] [blame] | 164 | uint8_t gpio_group_id; // Currently unused by FSP |
Matt Papageorge | 02f7471 | 2020-06-16 15:45:40 -0500 | [diff] [blame] | 165 | uint32_t port_present :1; // Should be TRUE if train link |
| 166 | uint32_t reserved_3 :7; |
| 167 | uint32_t device_number :5; // Desired root port device number |
| 168 | uint32_t function_number :3; // Desired root port function number |
Matt Papageorge | 8107cef | 2020-08-18 16:27:36 -0500 | [diff] [blame] | 169 | uint32_t link_speed_capability :2; // See dxio_link_speed_cap |
| 170 | uint32_t auto_spd_change :2; // See dxio_upstream_auto_speed_change |
| 171 | uint32_t eq_preset :4; // Gen3 equalization preset |
| 172 | uint32_t link_aspm :2; // See dxio_aspm_type |
| 173 | uint32_t link_aspm_L1_1 :1; // En/Dis root port capabilities for L1.1 |
| 174 | uint32_t link_aspm_L1_2 :1; // En/Dis root port capabilities for L1.2 |
| 175 | uint32_t clk_req :4; // See cpm_clk_req |
| 176 | uint8_t link_hotplug; // Currently unused by FSP |
| 177 | uint8_t slot_power_limit; // Currently unused by FSP |
| 178 | uint32_t slot_power_limit_scale :2; // Currently unused by FSP |
Matt Papageorge | 02f7471 | 2020-06-16 15:45:40 -0500 | [diff] [blame] | 179 | uint32_t reserved_4 :6; |
Matt Papageorge | 8107cef | 2020-08-18 16:27:36 -0500 | [diff] [blame] | 180 | uint32_t link_compliance_mode :1; // Currently unused by FSP |
| 181 | uint32_t link_safe_mode :1; // Currently unused by FSP |
| 182 | uint32_t sb_link :1; // Currently unused by FSP |
| 183 | uint32_t clk_pm_support :1; // Currently unused by FSP |
| 184 | uint32_t channel_type :3; // See dxio_sata_channel_type |
| 185 | uint32_t turn_off_unused_lanes :1; // Power down lanes if device not present |
Marshall Dawson | f0619f4 | 2020-01-21 21:46:51 -0700 | [diff] [blame] | 186 | uint8_t reserved[4]; |
Felix Held | 86db2c7 | 2020-07-21 17:09:31 +0200 | [diff] [blame] | 187 | } fsp_dxio_descriptor; |
Marshall Dawson | f0619f4 | 2020-01-21 21:46:51 -0700 | [diff] [blame] | 188 | |
| 189 | #endif /* __PI_PICASSO_PLATFORM_DESCRIPTORS_H__ */ |