zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * Configure Max Payload |
| 6 | * |
| 7 | * |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: GNB |
| 12 | * @e \$Revision: |
| 13 | * |
| 14 | */ |
| 15 | /* |
| 16 | ***************************************************************************** |
| 17 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame^] | 18 | * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. |
| 19 | * All rights reserved. |
| 20 | * |
| 21 | * Redistribution and use in source and binary forms, with or without |
| 22 | * modification, are permitted provided that the following conditions are met: |
| 23 | * * Redistributions of source code must retain the above copyright |
| 24 | * notice, this list of conditions and the following disclaimer. |
| 25 | * * Redistributions in binary form must reproduce the above copyright |
| 26 | * notice, this list of conditions and the following disclaimer in the |
| 27 | * documentation and/or other materials provided with the distribution. |
| 28 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 29 | * its contributors may be used to endorse or promote products derived |
| 30 | * from this software without specific prior written permission. |
| 31 | * |
| 32 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 33 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 35 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 36 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 37 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 38 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 39 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 40 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 41 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 42 | * *************************************************************************** |
| 43 | * |
| 44 | */ |
| 45 | |
| 46 | /*---------------------------------------------------------------------------------------- |
| 47 | * M O D U L E S U S E D |
| 48 | *---------------------------------------------------------------------------------------- |
| 49 | */ |
| 50 | #include "AGESA.h" |
| 51 | #include "Ids.h" |
| 52 | #include "amdlib.h" |
| 53 | #include "Gnb.h" |
| 54 | #include "GnbPcie.h" |
| 55 | #include "GnbCommonLib.h" |
| 56 | #include "GnbPcieConfig.h" |
| 57 | #include "GnbPcieInitLibV1.h" |
| 58 | #include "GnbPcieInitLibV4.h" |
| 59 | #include "PcieMaxPayloadV4.h" |
| 60 | #include "GnbRegistersTN.h" |
| 61 | #include "Filecode.h" |
| 62 | #define FILECODE PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEMAXPAYLOADV4_FILECODE |
| 63 | |
| 64 | /*---------------------------------------------------------------------------------------- |
| 65 | * D E F I N I T I O N S A N D M A C R O S |
| 66 | *---------------------------------------------------------------------------------------- |
| 67 | */ |
| 68 | |
| 69 | |
| 70 | /*---------------------------------------------------------------------------------------- |
| 71 | * T Y P E D E F S A N D S T R U C T U R E S |
| 72 | *---------------------------------------------------------------------------------------- |
| 73 | */ |
| 74 | typedef struct { |
| 75 | GNB_PCI_SCAN_DATA ScanData; |
| 76 | UINT8 MaxPayload; |
| 77 | } PCIE_MAX_PAYLOAD_DATA; |
| 78 | |
| 79 | |
| 80 | /*---------------------------------------------------------------------------------------- |
| 81 | * P R O T O T Y P E S O F L O C A L F U N C T I O N S |
| 82 | *---------------------------------------------------------------------------------------- |
| 83 | */ |
| 84 | |
| 85 | |
| 86 | SCAN_STATUS |
| 87 | PcieGetMaxPayloadCallback ( |
| 88 | IN PCI_ADDR Device, |
| 89 | IN OUT GNB_PCI_SCAN_DATA *ScanData |
| 90 | ); |
| 91 | |
| 92 | SCAN_STATUS |
| 93 | PcieSetMaxPayloadCallback ( |
| 94 | IN PCI_ADDR Device, |
| 95 | IN OUT GNB_PCI_SCAN_DATA *ScanData |
| 96 | ); |
| 97 | |
| 98 | AGESA_STATUS |
| 99 | PciePayloadBlackListFeature ( |
| 100 | IN PCI_ADDR Device, |
| 101 | IN UINT8 *MaxPayload, |
| 102 | IN AMD_CONFIG_PARAMS *StdHeader |
| 103 | ); |
| 104 | |
| 105 | /*----------------------------------------------------------------------------------------*/ |
| 106 | /** |
| 107 | * Determine maximum payload size for PCIe segment |
| 108 | * |
| 109 | * Scan through all link in segment to determine maximum payload by EPs. |
| 110 | * |
| 111 | * @param[in] DownstreamPort PCI address of PCIe port |
| 112 | * @param[in] StdHeader Standard configuration header |
| 113 | * |
| 114 | */ |
| 115 | |
| 116 | VOID |
| 117 | PcieSetMaxPayload ( |
| 118 | IN PCI_ADDR DownstreamPort, |
| 119 | IN AMD_CONFIG_PARAMS *StdHeader |
| 120 | ) |
| 121 | { |
| 122 | PCIE_MAX_PAYLOAD_DATA PcieMaxPayloadData; |
| 123 | |
| 124 | IDS_HDT_CONSOLE (GNB_TRACE, " PcieSetMaxPayload for Device = %d:%d:%d\n", |
| 125 | DownstreamPort.Address.Bus, |
| 126 | DownstreamPort.Address.Device, |
| 127 | DownstreamPort.Address.Function |
| 128 | ); |
| 129 | PcieMaxPayloadData.MaxPayload = MAX_PAYLOAD; |
| 130 | PcieMaxPayloadData.ScanData.StdHeader = StdHeader; |
| 131 | PcieMaxPayloadData.ScanData.GnbScanCallback = PcieGetMaxPayloadCallback; |
| 132 | GnbLibPciScan (DownstreamPort, DownstreamPort, &PcieMaxPayloadData.ScanData); |
| 133 | PcieMaxPayloadData.ScanData.GnbScanCallback = PcieSetMaxPayloadCallback; |
| 134 | GnbLibPciScan (DownstreamPort, DownstreamPort, &PcieMaxPayloadData.ScanData); |
| 135 | IDS_HDT_CONSOLE (GNB_TRACE, " PcieSetMaxPayloadExit\n"); |
| 136 | } |
| 137 | |
| 138 | /*----------------------------------------------------------------------------------------*/ |
| 139 | /** |
| 140 | * Evaluate device Max Payload - save SMALLEST Max Payload for PCIe Segment |
| 141 | * |
| 142 | * |
| 143 | * |
| 144 | * @param[in] Device PCI Address |
| 145 | * @param[in,out] ScanData Scan configuration data |
| 146 | * @retval Scan Status of 0 |
| 147 | */ |
| 148 | |
| 149 | SCAN_STATUS |
| 150 | PcieGetMaxPayloadCallback ( |
| 151 | IN PCI_ADDR Device, |
| 152 | IN OUT GNB_PCI_SCAN_DATA *ScanData |
| 153 | ) |
| 154 | { |
| 155 | SCAN_STATUS ScanStatus; |
| 156 | PCIE_MAX_PAYLOAD_DATA *PcieMaxPayloadData; |
| 157 | PCIE_DEVICE_TYPE DeviceType; |
| 158 | UINT32 Value; |
| 159 | UINT8 PcieCapPtr; |
| 160 | UINT8 DeviceMaxPayload; |
| 161 | |
| 162 | PcieMaxPayloadData = (PCIE_MAX_PAYLOAD_DATA*) ScanData; |
| 163 | ScanStatus = SCAN_SUCCESS; |
| 164 | IDS_HDT_CONSOLE (GNB_TRACE, " PcieGetMaxPayloadCallback for Device = %d:%d:%d\n", |
| 165 | Device.Address.Bus, |
| 166 | Device.Address.Device, |
| 167 | Device.Address.Function |
| 168 | ); |
| 169 | PcieCapPtr = GnbLibFindPciCapability (Device.AddressValue, PCIE_CAP_ID, ScanData->StdHeader); |
| 170 | if (PcieCapPtr != 0) { |
| 171 | GnbLibPciRead ( |
| 172 | Device.AddressValue | (PcieCapPtr + PCIE_DEVICE_CAP_REGISTER), |
| 173 | AccessWidth32, |
| 174 | &Value, |
| 175 | ScanData->StdHeader |
| 176 | ); |
| 177 | DeviceMaxPayload = (UINT8) (Value & 0x7); |
| 178 | PciePayloadBlackListFeature (Device, &DeviceMaxPayload, ScanData->StdHeader); |
| 179 | IDS_HDT_CONSOLE (GNB_TRACE, " Found DeviceMaxPayload as %d (Value = %x\n", DeviceMaxPayload, Value); |
| 180 | if (DeviceMaxPayload < PcieMaxPayloadData->MaxPayload) { |
| 181 | PcieMaxPayloadData->MaxPayload = DeviceMaxPayload; |
| 182 | } |
| 183 | } |
| 184 | DeviceType = GnbLibGetPcieDeviceType (Device, ScanData->StdHeader); |
| 185 | switch (DeviceType) { |
| 186 | case PcieDeviceRootComplex: |
| 187 | case PcieDeviceDownstreamPort: |
| 188 | case PcieDeviceUpstreamPort: |
| 189 | GnbLibPciScanSecondaryBus (Device, &PcieMaxPayloadData->ScanData); |
| 190 | break; |
| 191 | case PcieDeviceEndPoint: |
| 192 | case PcieDeviceLegacyEndPoint: |
| 193 | break; |
| 194 | default: |
| 195 | break; |
| 196 | } |
| 197 | return SCAN_SUCCESS; |
| 198 | } |
| 199 | |
| 200 | /*----------------------------------------------------------------------------------------*/ |
| 201 | /** |
| 202 | * Configure the Max Payload setting to all devices in the PCIe Segment |
| 203 | * |
| 204 | * |
| 205 | * |
| 206 | * @param[in] Device PCI Address |
| 207 | * @param[in,out] ScanData Scan configuration data |
| 208 | * @retval Scan Status of 0 |
| 209 | */ |
| 210 | |
| 211 | SCAN_STATUS |
| 212 | PcieSetMaxPayloadCallback ( |
| 213 | IN PCI_ADDR Device, |
| 214 | IN OUT GNB_PCI_SCAN_DATA *ScanData |
| 215 | ) |
| 216 | { |
| 217 | SCAN_STATUS ScanStatus; |
| 218 | PCIE_MAX_PAYLOAD_DATA *PcieMaxPayloadData; |
| 219 | PCIE_DEVICE_TYPE DeviceType; |
| 220 | UINT8 PcieCapPtr; |
| 221 | |
| 222 | PcieMaxPayloadData = (PCIE_MAX_PAYLOAD_DATA*) ScanData; |
| 223 | ScanStatus = SCAN_SUCCESS; |
| 224 | IDS_HDT_CONSOLE (GNB_TRACE, " PcieSetMaxPayloadCallback for Device = %d:%d:%d to %d\n", |
| 225 | Device.Address.Bus, |
| 226 | Device.Address.Device, |
| 227 | Device.Address.Function, |
| 228 | PcieMaxPayloadData->MaxPayload |
| 229 | ); |
| 230 | PcieCapPtr = GnbLibFindPciCapability (Device.AddressValue, PCIE_CAP_ID, ScanData->StdHeader); |
| 231 | if (PcieCapPtr != 0) { |
| 232 | GnbLibPciRMW ( |
| 233 | Device.AddressValue | (PcieCapPtr + PCIE_DEVICE_CTRL_REGISTER), |
| 234 | AccessWidth32, |
| 235 | ~(UINT32) (0x7 << 5), |
| 236 | ((UINT32)PcieMaxPayloadData->MaxPayload << 5), |
| 237 | ScanData->StdHeader |
| 238 | ); |
| 239 | } |
| 240 | DeviceType = GnbLibGetPcieDeviceType (Device, ScanData->StdHeader); |
| 241 | switch (DeviceType) { |
| 242 | case PcieDeviceRootComplex: |
| 243 | case PcieDeviceDownstreamPort: |
| 244 | case PcieDeviceUpstreamPort: |
| 245 | GnbLibPciScanSecondaryBus (Device, &PcieMaxPayloadData->ScanData); |
| 246 | break; |
| 247 | case PcieDeviceEndPoint: |
| 248 | case PcieDeviceLegacyEndPoint: |
| 249 | break; |
| 250 | default: |
| 251 | break; |
| 252 | } |
| 253 | return SCAN_SUCCESS; |
| 254 | } |
| 255 | |
| 256 | UINT16 PayloadBlacklistDeviceTable[] = { |
| 257 | 0x1969, 0x1083, (UINT16) MAX_PAYLOAD_128 |
| 258 | }; |
| 259 | |
| 260 | /*----------------------------------------------------------------------------------------*/ |
| 261 | /** |
| 262 | * Pcie Max_Payload_Size Black List |
| 263 | * |
| 264 | * |
| 265 | * |
| 266 | * @param[in] Device PCI_ADDR of PCIe Device to evaluate |
| 267 | * @param[in] MaxPayload Pointer to Max_Payload_Size value |
| 268 | * @param[in] StdHeader Standard configuration header |
| 269 | * @retval AGESA_STATUS |
| 270 | */ |
| 271 | |
| 272 | AGESA_STATUS |
| 273 | PciePayloadBlackListFeature ( |
| 274 | IN PCI_ADDR Device, |
| 275 | IN UINT8 *MaxPayload, |
| 276 | IN AMD_CONFIG_PARAMS *StdHeader |
| 277 | ) |
| 278 | { |
| 279 | UINT32 TargetDeviceId; |
| 280 | UINTN i; |
| 281 | UINT32 DeviceId; |
| 282 | UINT32 VendorId; |
| 283 | |
| 284 | GnbLibPciRead (Device.AddressValue, AccessWidth32, &TargetDeviceId, StdHeader); |
| 285 | for (i = 0; i < (sizeof (PayloadBlacklistDeviceTable) / sizeof (UINT16)); i = i + 3) { |
| 286 | VendorId = PayloadBlacklistDeviceTable[i]; |
| 287 | DeviceId = PayloadBlacklistDeviceTable[i + 1]; |
| 288 | if (VendorId == (UINT16)TargetDeviceId) { |
| 289 | if (DeviceId == 0xFFFF || DeviceId == (TargetDeviceId >> 16)) { |
| 290 | *MaxPayload = (UINT8) PayloadBlacklistDeviceTable[i + 2]; |
| 291 | } |
| 292 | } |
| 293 | } |
| 294 | return AGESA_SUCCESS; |
| 295 | } |