Jian Tong | c2149b7 | 2024-05-21 14:38:18 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | |
| 3 | #include <baseboard/gpio.h> |
| 4 | #include <baseboard/variants.h> |
| 5 | #include <soc/gpio.h> |
| 6 | #include <vendorcode/google/chromeos/chromeos.h> |
| 7 | |
| 8 | /* Pad configuration in ramstage */ |
| 9 | static const struct pad_config override_gpio_table[] = { |
Jing Tong | 63f2437 | 2024-06-21 14:37:33 +0800 | [diff] [blame^] | 10 | /* GPP_B14 : [NF1: SPKR NF2: TIME_SYNC1 NF4: SATA_LED# NF5: ISH_GP6 |
| 11 | * NF6: USB_C_GPP_B14] ==> ACZ_SPKR */ |
| 12 | PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), |
Jian Tong | c2149b7 | 2024-05-21 14:38:18 +0800 | [diff] [blame] | 13 | /* GPP_D5 : SRCCLKREQ0_L ==> PCIE_REFCLK_SSD1_REQ_N */ |
| 14 | PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), |
| 15 | /* GPP_D6 : [NF1: SRCCLKREQ1# NF6: USB_C_GPP_D6] ==> SOC_GPP_E10 (NC) */ |
| 16 | PAD_NC(GPP_D6, NONE), |
| 17 | /* GPP_D7 : SRCCLKREQ2_L ==> WLAN_CLKREQ_ODL */ |
| 18 | PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), |
| 19 | /* GPP_D9 : [NF1: ISH_SPI_CS# NF2: DDP3_CTRLCLK NF4: TBT_LSX2_TXD NF5: BSSB_LS2_RX |
| 20 | * NF6: USB_C_GPP_D9 NF7: GSPI2_CS0#] ==> HOST_MCU_FW_UP_STRAP */ |
| 21 | PAD_CFG_GPO_LOCK(GPP_D9, 0, LOCK_CONFIG), |
| 22 | /* GPP_E7 : [NF1: PROC_GP1 NF6: USB_C_GPP_E7] ==> SD_PERST_L */ |
| 23 | PAD_CFG_GPO(GPP_E7, 1, DEEP), |
| 24 | /* GPP_E10 : THC0_SPI1_CS_L/GSPI0_CS0_L ==> GSPI0_SOC_FP_CS_L */ |
Jian Tong | 95332df | 2024-06-11 14:42:06 +0800 | [diff] [blame] | 25 | PAD_CFG_NF(GPP_E10, NONE, DEEP, NF7), |
Jian Tong | c2149b7 | 2024-05-21 14:38:18 +0800 | [diff] [blame] | 26 | /* GPP_E11 : [NF2: THC0_SPI1_CLK NF6: USB_C_GPP_E11 |
| 27 | * NF7: GSPI0_CLK] ==> GSPI0_SOC_FP_CLK */ |
| 28 | PAD_CFG_NF(GPP_E11, NONE, DEEP, NF7), |
| 29 | /* GPP_E12 : THC0_SPI1_IO1/I2C0A_SDA/GSPI0_MISO ==> GSPI0_SOC_DI_FP_DO */ |
Jian Tong | 95332df | 2024-06-11 14:42:06 +0800 | [diff] [blame] | 30 | PAD_CFG_NF(GPP_E12, NONE, DEEP, NF7), |
Jian Tong | c2149b7 | 2024-05-21 14:38:18 +0800 | [diff] [blame] | 31 | /* GPP_E13 : THC0_SPI1_IO0/I2C0A_SCL/GSPI0_MOSI ==> GSPI0_SOC_DO_FP_DI */ |
Jian Tong | 95332df | 2024-06-11 14:42:06 +0800 | [diff] [blame] | 32 | PAD_CFG_NF(GPP_E13, NONE, DEEP, NF7), |
Jian Tong | c2149b7 | 2024-05-21 14:38:18 +0800 | [diff] [blame] | 33 | /* GPP_E15 : SRCCLK_OE8_L ==> SOC_GPP_E15 (NC) */ |
| 34 | PAD_NC(GPP_E15, NONE), |
| 35 | /* GPP_E18 : [NF1: DDP1_CTRLCLK NF4: TBT_LSX0_TXD NF5: BSSB_LS0_RX |
| 36 | * NF6: USB_C_GPP_E18] ==> SOC_FPMCU_INT_L */ |
| 37 | PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_E18, NONE, LEVEL, INVERT, LOCK_CONFIG), |
| 38 | /* GPP_E20 : [NF1: DDP2_CTRLCLK NF4: TBT_LSX1_TXD NF5: BSSB_LS1_RX |
| 39 | * NF6: USB_C_GPP_E20] ==> EN_FP_PWR */ |
| 40 | PAD_CFG_GPO_LOCK(GPP_E20, 0, LOCK_CONFIG), |
| 41 | /* GPP_E21 : DDP2_CTRLDATA/TBT_LSX1_RXD/BSSB_LS1_TX ==> FP_RST_ODL */ |
| 42 | PAD_CFG_GPO_LOCK(GPP_E21, 0, LOCK_CONFIG), |
| 43 | /* GPP_F11 : [NF3: THC1_SPI2_CLK NF4: GSPI1_CLK |
| 44 | * NF6: USB_C_GPP_F11] ==> GSPI1_SOC_TCHSCR_CLK */ |
| 45 | PAD_CFG_NF_LOCK(GPP_F11, NONE, NF4, LOCK_CONFIG), |
| 46 | /* GPP_F12 : [NF1: GSXDOUT NF3: THC1_SPI2_IO0 NF4: GSPI1_MOSI NF5: I2C1A_SCL |
| 47 | * NF6: USB_C_GPP_F12] ==> GSPI1_SOC_DO_TCHSCR_DI */ |
| 48 | PAD_CFG_NF_LOCK(GPP_F12, NONE, NF4, LOCK_CONFIG), |
| 49 | /* GPP_F13 : [NF1: GSXSLOAD NF3: THC1_SPI2_IO1 NF4: GSPI1_MISIO NF5: I2C1A_SDA |
| 50 | * NF6: USB_C_GPP_F13] ==> GSPI1_SOC_DI_TCHSCR_DO */ |
| 51 | PAD_CFG_NF_LOCK(GPP_F13, NONE, NF4, LOCK_CONFIG), |
| 52 | /* GPP_F15 : [NF1: GSXSRESET# NF3: THC1_SPI2_IO3 |
| 53 | * NF6: USB_C_GPP_F15] ==> PCH_TCHSCR_REPORT_EN */ |
| 54 | PAD_CFG_GPO(GPP_F15, 0, PLTRST), |
| 55 | /* GPP_F16 : [NF1: GSXCLK NF3: THC1_SPI2_CS# NF4: GSPI1_CS0# |
| 56 | * NF6: USB_C_GPP_F16] ==> GSPI1_SOC_TCHSCR_CS_L */ |
| 57 | PAD_CFG_NF_LOCK(GPP_F16, NONE, NF4, LOCK_CONFIG), |
| 58 | /* GPP_S4 : SNDW2_CLK/DMIC_CLK_B0 ==> MEM_STRAP_0 */ |
| 59 | PAD_CFG_GPI(GPP_S4, NONE, PLTRST), |
| 60 | /* GPP_S5 : SNDW2_DATA/DMIC_CLK_B1 ==> MEM_STRAP_1 */ |
| 61 | PAD_CFG_GPI(GPP_S5, NONE, PLTRST), |
| 62 | /* GPP_S6 : SNDW3_CLK/DMIC_CLK_A1 ==> MEM_STRAP_2 */ |
| 63 | PAD_CFG_GPI(GPP_S6, NONE, PLTRST), |
| 64 | /* GPP_S7 : SNDW3_DATA/DMIC_DATA1 ==> MEM_STRAP_3 */ |
| 65 | PAD_CFG_GPI(GPP_S7, NONE, PLTRST), |
Jian Tong | 95332df | 2024-06-11 14:42:06 +0800 | [diff] [blame] | 66 | /* GPP_F18 : [NF3: THC1_SPI2_INT# NF6: USB_C_GPP_F18] ==> TCHSCR_INT_ODL */ |
| 67 | PAD_CFG_GPI_APIC(GPP_F18, NONE, DEEP, EDGE_SINGLE, NONE), |
Jian Tong | c2149b7 | 2024-05-21 14:38:18 +0800 | [diff] [blame] | 68 | }; |
| 69 | |
| 70 | |
| 71 | const struct pad_config *variant_gpio_override_table(size_t *num) |
| 72 | { |
| 73 | *num = ARRAY_SIZE(override_gpio_table); |
| 74 | return override_gpio_table; |
| 75 | } |
| 76 | |
| 77 | /* Early pad configuration in bootblock */ |
| 78 | static const struct pad_config early_gpio_table[] = { |
| 79 | /* GPP_D11 : [] ==> EN_PP3300_SSD (NC) */ |
| 80 | PAD_NC(GPP_D11, NONE), |
| 81 | /* GPP_E2 : THC0_SPI1_IO3 ==> GSC_PCH_INT_ODL */ |
| 82 | PAD_CFG_GPI_APIC_LOCK(GPP_E2, NONE, LEVEL, INVERT, LOCK_CONFIG), |
| 83 | /* GPP_E8 : GPP_E8 ==> PCH_WP_OD */ |
| 84 | PAD_CFG_GPI_LOCK(GPP_E8, NONE, LOCK_CONFIG), |
| 85 | /* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */ |
| 86 | PAD_CFG_GPO(GPP_F9, 0, DEEP), |
| 87 | /* F21 : EXT_PWR_GATE2# ==> NC */ |
| 88 | PAD_NC(GPP_F21, NONE), |
| 89 | /* GPP_H8 : [NF1: I2C4_SDA NF2: CNV_MFUART2_RXD NF6: USB_C_GPP_H8] ==> PCH_I2C_GSC_SDA */ |
| 90 | PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), |
| 91 | /* GPP_H9 : [NF1: I2C4_SCL NF2: CNV_MFUART2_TXD] ==> PCH_I2C_GSC_SCL */ |
| 92 | PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), |
| 93 | /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ |
| 94 | PAD_CFG_NF(GPP_H10, NONE, PLTRST, NF2), |
| 95 | /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ |
| 96 | PAD_CFG_NF(GPP_H11, NONE, PLTRST, NF2), |
| 97 | /* GPP_S0 : SNDW0_CLL/I2S1_SCLK ==> MEM_CH_SEL */ |
| 98 | PAD_CFG_GPI(GPP_S0, NONE, DEEP), |
| 99 | |
| 100 | /* CPU PCIe VGPIO for PEG60 */ |
| 101 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), |
| 102 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1), |
| 103 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1), |
| 104 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1), |
| 105 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1), |
| 106 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1), |
| 107 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1), |
| 108 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1), |
| 109 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1), |
| 110 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1), |
| 111 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1), |
| 112 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1), |
| 113 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1), |
| 114 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1), |
| 115 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1), |
| 116 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1), |
| 117 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1), |
| 118 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1), |
| 119 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1), |
| 120 | PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1), |
| 121 | }; |
| 122 | |
| 123 | static const struct pad_config romstage_gpio_table[] = { |
| 124 | /* GPP_S4 : SNDW2_CLK/DMIC_CLK_B0 ==> MEM_STRAP_0 */ |
| 125 | PAD_CFG_GPI(GPP_S4, NONE, PLTRST), |
| 126 | /* GPP_S5 : SNDW2_DATA/DMIC_CLK_B1 ==> MEM_STRAP_1 */ |
| 127 | PAD_CFG_GPI(GPP_S5, NONE, PLTRST), |
| 128 | /* GPP_S6 : SNDW3_CLK/DMIC_CLK_A1 ==> MEM_STRAP_2 */ |
| 129 | PAD_CFG_GPI(GPP_S6, NONE, PLTRST), |
| 130 | /* GPP_S7 : SNDW3_DATA/DMIC_DATA1 ==> MEM_STRAP_3 */ |
| 131 | PAD_CFG_GPI(GPP_S7, NONE, PLTRST), |
| 132 | /* GPP_F7 : [NF6: USB_C_GPP_F7] ==> EN_PP3300_TCHSCR */ |
| 133 | PAD_CFG_GPO(GPP_F7, 1, PLTRST), |
| 134 | /* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */ |
| 135 | PAD_CFG_GPO(GPP_F9, 1, DEEP), |
| 136 | /* GPP_F17 : [NF3: THC1_SPI2_RST# NF6: USB_C_GPP_F17] ==> TCHSCR_RST_L */ |
| 137 | PAD_CFG_GPO(GPP_F17, 0, DEEP), |
| 138 | /* GPP_S0 : SNDW0_CLL/I2S1_SCLK ==> MEM_CH_SEL */ |
| 139 | PAD_CFG_GPI(GPP_S0, NONE, DEEP), |
| 140 | }; |
| 141 | |
| 142 | const struct pad_config *variant_early_gpio_table(size_t *num) |
| 143 | { |
| 144 | *num = ARRAY_SIZE(early_gpio_table); |
| 145 | return early_gpio_table; |
| 146 | } |
| 147 | |
| 148 | const struct pad_config *variant_romstage_gpio_table(size_t *num) |
| 149 | { |
| 150 | *num = ARRAY_SIZE(romstage_gpio_table); |
| 151 | return romstage_gpio_table; |
| 152 | } |
| 153 | |
| 154 | static const struct cros_gpio cros_gpios[] = { |
| 155 | CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), |
| 156 | CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), |
| 157 | }; |
| 158 | |
| 159 | DECLARE_CROS_GPIOS(cros_gpios); |