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review.coreboot.org / coreboot / 63e62b03a8385663bebff3bdee88327bb57b27fd / . / src / southbridge / amd / cimx_wrapper / sb800 / lpc.c
blob: 39762a9bec65062ef000dcd2bfc87ed3ea37e0ca [file] [log] [blame]
Frank Vibrans63e62b02011-02-14 18:38:14 +0000[diff] [blame^]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20#include <device/pci.h>
21#include "lpc.h"
22
23
24void lpc_read_resources(device_t dev)
25{
26 struct resource *res;
27
28 /* Get the normal pci resources of this device */
29 pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */
30
31 pci_get_resource(dev, SPIROM_BASE_ADDRESS); /* SPI ROM base address */
32
33 /* Add an extra subtractive resource for both memory and I/O. */
34 res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
35 res->base = 0;
36 res->size = 0x1000;
37 res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
38 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
39
40 res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
41 res->base = 0xff800000;
42 res->size = 0x00800000; /* 8 MB for flash */
43 res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
44 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
45
46 res = new_resource(dev, 3); /* IOAPIC */
47 res->base = 0xfec00000;
48 res->size = 0x00001000;
49 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
50
51 compact_resources(dev);
52}
53
54void lpc_set_resources(struct device *dev)
55{
56 struct resource *res;
57
58 pci_dev_set_resources(dev);
59
60 /* Specical case. SPI Base Address. The SpiRomEnable should be set. */
61 res = find_resource(dev, SPIROM_BASE_ADDRESS);
62 pci_write_config32(dev, SPIROM_BASE_ADDRESS, res->base | 1 << 1);
63
64}
65
66/**
67 * @brief Enable resources for children devices
68 *
69 * @param dev the device whos children's resources are to be enabled
70 *
71 */
72void lpc_enable_childrens_resources(device_t dev)
73{
74 struct bus *link;
75 u32 reg, reg_x;
76 int var_num = 0;
77 u16 reg_var[3];
78
79 reg = pci_read_config32(dev, 0x44);
80 reg_x = pci_read_config32(dev, 0x48);
81
82 for (link = dev->link_list; link; link = link->next) {
83 device_t child;
84 for (child = link->children; child;
85 child = child->sibling) {
86 if (child->enabled
87 && (child->path.type == DEVICE_PATH_PNP)) {
88 struct resource *res;
89 for (res = child->resource_list; res; res = res->next) {
90 u32 base, end; /* don't need long long */
91 if (!(res->flags & IORESOURCE_IO))
92 continue;
93 base = res->base;
94 end = resource_end(res);
95/*
96 printk(BIOS_DEBUG, "sb800 lpc decode:%s, base=0x%08x, end=0x%08x\n",
97 dev_path(child), base, end);
98*/
99 switch (base) {
100 case 0x60: /* KB */
101 case 0x64: /* MS */
102 reg |= (1 << 29);
103 break;
104 case 0x3f8: /* COM1 */
105 reg |= (1 << 6);
106 break;
107 case 0x2f8: /* COM2 */
108 reg |= (1 << 7);
109 break;
110 case 0x378: /* Parallal 1 */
111 reg |= (1 << 0);
112 break;
113 case 0x3f0: /* FD0 */
114 reg |= (1 << 26);
115 break;
116 case 0x220: /* Aduio 0 */
117 reg |= (1 << 8);
118 break;
119 case 0x300: /* Midi 0 */
120 reg |= (1 << 18);
121 break;
122 case 0x400:
123 reg_x |= (1 << 16);
124 break;
125 case 0x480:
126 reg_x |= (1 << 17);
127 break;
128 case 0x500:
129 reg_x |= (1 << 18);
130 break;
131 case 0x580:
132 reg_x |= (1 << 19);
133 break;
134 case 0x4700:
135 reg_x |= (1 << 22);
136 break;
137 case 0xfd60:
138 reg_x |= (1 << 23);
139 break;
140 default:
141 if (var_num >= 3)
142 continue; /* only 3 var ; compact them ? */
143 switch (var_num) {
144 case 0:
145 reg_x |= (1 << 2);
146 break;
147 case 1:
148 reg_x |= (1 << 24);
149 break;
150 case 2:
151 reg_x |= (1 << 25);
152 break;
153 }
154 reg_var[var_num++] =
155 base & 0xffff;
156 }
157 }
158 }
159 }
160 }
161 pci_write_config32(dev, 0x44, reg);
162 pci_write_config32(dev, 0x48, reg_x);
163 /* Set WideIO for as many IOs found (fall through is on purpose) */
164 switch (var_num) {
165 case 2:
166 pci_write_config16(dev, 0x90, reg_var[2]);
167 case 1:
168 pci_write_config16(dev, 0x66, reg_var[1]);
169 case 0:
170 //pci_write_config16(dev, 0x64, reg_var[0]); //cause filo can not find sata
171 break;
172 }
173}