Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 2 | |
| 3 | #include <bootblock_common.h> |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 4 | #include <console/console.h> |
Johnny Lin | 34473ea | 2020-03-18 10:23:26 +0800 | [diff] [blame] | 5 | #include <cpu/x86/mtrr.h> |
Jeremy Compostella | 63d5fc6 | 2024-02-01 14:30:48 -0800 | [diff] [blame^] | 6 | #include <device/pci.h> |
Arthur Heymans | 087fe9f | 2020-10-28 14:10:37 +0100 | [diff] [blame] | 7 | #include <fsp/util.h> |
Jeremy Compostella | 63d5fc6 | 2024-02-01 14:30:48 -0800 | [diff] [blame^] | 8 | #include <FsptUpd.h> |
| 9 | #include <intelblocks/fast_spi.h> |
| 10 | #include <intelblocks/lpc_lib.h> |
| 11 | #include <intelblocks/tco.h> |
| 12 | #include <security/intel/cbnt/cbnt.h> |
| 13 | #include <soc/bootblock.h> |
| 14 | #include <soc/iomap.h> |
| 15 | #include <soc/pci_devs.h> |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 16 | |
| 17 | const FSPT_UPD temp_ram_init_params = { |
| 18 | .FspUpdHeader = { |
| 19 | .Signature = FSPT_UPD_SIGNATURE, |
| 20 | .Revision = 1, |
| 21 | .Reserved = {0}, |
| 22 | }, |
| 23 | .FsptCoreUpd = { |
| 24 | .MicrocodeRegionBase = (UINT32)CONFIG_CPU_MICROCODE_CBFS_LOC, |
| 25 | .MicrocodeRegionLength = (UINT32)CONFIG_CPU_MICROCODE_CBFS_LEN, |
Johnny Lin | 34473ea | 2020-03-18 10:23:26 +0800 | [diff] [blame] | 26 | .CodeRegionBase = (UINT32)CACHE_ROM_BASE, |
| 27 | .CodeRegionLength = (UINT32)CACHE_ROM_SIZE, |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 28 | .Reserved1 = {0}, |
| 29 | }, |
| 30 | .FsptConfig = { |
Jonathan Zhang | 641642e | 2020-05-26 13:42:28 -0700 | [diff] [blame] | 31 | .FsptPort80RouteDisable = 0, |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 32 | .ReservedTempRamInitUpd = {0}, |
| 33 | }, |
| 34 | .UnusedUpdSpace0 = {0}, |
| 35 | .UpdTerminator = 0x55AA, |
| 36 | }; |
| 37 | |
Arthur Heymans | 02dec12 | 2020-11-18 12:27:28 +0100 | [diff] [blame] | 38 | static uint64_t assembly_timestamp; |
| 39 | static uint64_t bootblock_timestamp; |
| 40 | |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 41 | asmlinkage void bootblock_c_entry(uint64_t base_timestamp) |
| 42 | { |
Arthur Heymans | 02dec12 | 2020-11-18 12:27:28 +0100 | [diff] [blame] | 43 | /* |
| 44 | * FSP-T does not respect its own API and trashes registers |
| 45 | * coreboot uses to store its initial timestamp. |
| 46 | */ |
| 47 | assembly_timestamp = base_timestamp; |
| 48 | bootblock_timestamp = timestamp_get(); |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 49 | fast_spi_cache_bios_region(); |
| 50 | |
Arthur Heymans | 02dec12 | 2020-11-18 12:27:28 +0100 | [diff] [blame] | 51 | bootblock_main_with_basetime(MIN(assembly_timestamp, bootblock_timestamp)); |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 52 | } |
| 53 | |
| 54 | void bootblock_soc_early_init(void) |
| 55 | { |
| 56 | fast_spi_early_init(SPI_BASE_ADDRESS); |
Johnny Lin | ebb7f54 | 2020-02-19 15:52:45 +0800 | [diff] [blame] | 57 | pch_enable_lpc(); |
Andrey Petrov | 335384d | 2020-03-22 22:27:44 -0700 | [diff] [blame] | 58 | |
| 59 | /* Set up P2SB BAR. This is needed for PCR to work */ |
Nico Huber | f4f365f | 2021-10-14 18:16:39 +0200 | [diff] [blame] | 60 | uint8_t p2sb_cmd = pci_s_read_config8(PCH_DEV_P2SB, PCI_COMMAND); |
| 61 | pci_s_write_config8(PCH_DEV_P2SB, PCI_COMMAND, p2sb_cmd | PCI_COMMAND_MEMORY); |
| 62 | pci_s_write_config32(PCH_DEV_P2SB, PCI_BASE_ADDRESS_0, CONFIG_PCR_BASE_ADDRESS); |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 63 | } |
| 64 | |
| 65 | void bootblock_soc_init(void) |
| 66 | { |
Arthur Heymans | 02dec12 | 2020-11-18 12:27:28 +0100 | [diff] [blame] | 67 | if (assembly_timestamp > bootblock_timestamp) |
| 68 | printk(BIOS_WARNING, "Invalid initial timestamp detected\n"); |
| 69 | |
Arthur Heymans | 087fe9f | 2020-10-28 14:10:37 +0100 | [diff] [blame] | 70 | if (CONFIG(FSP_CAR)) |
| 71 | report_fspt_output(); |
Arthur Heymans | ee55d71 | 2021-05-12 16:22:05 +0200 | [diff] [blame] | 72 | |
| 73 | if (CONFIG(INTEL_CBNT_LOGGING)) |
| 74 | intel_cbnt_log_registers(); |
| 75 | |
Rocky Phagura | c62c98a | 2020-05-23 20:29:00 -0700 | [diff] [blame] | 76 | bootblock_pch_init(); |
Johnny Lin | 6b1e7dd | 2022-01-24 15:18:57 +0800 | [diff] [blame] | 77 | |
| 78 | /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ |
| 79 | tco_configure(); |
Naresh Solanki | 0813533 | 2022-12-05 11:42:10 +0100 | [diff] [blame] | 80 | |
| 81 | report_platform_info(); |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 82 | } |