blob: a930bc9a95ce794a104fbc4bdcdb28cfb01c9fdf [file] [log] [blame]
Martin Rothb5b1c5a2021-08-09 13:47:48 -06001/* SPDX-License-Identifier: GPL-2.0-only */
2
3
4#ifndef AMD_COMMON_PSP_EFS_H
5#define AMD_COMMON_PSP_EFS_H
6
7#include <types.h>
8
Zheng Bao63c952a2023-07-27 17:14:41 +08009#define EFS_OFFSET (CONFIG_ROM_SIZE - (0x80000 << CONFIG_AMD_FWM_POSITION_INDEX) + 0x20000)
Martin Rothb5b1c5a2021-08-09 13:47:48 -060010
11#define EMBEDDED_FW_SIGNATURE 0x55aa55aa
12
13#if CONFIG(SOC_AMD_STONEYRIDGE)
14 #define SPI_MODE_FIELD spi_readmode_f15_mod_60_6f
15 #define SPI_SPEED_FIELD fast_speed_new_f15_mod_60_6f
16#elif CONFIG(SOC_AMD_PICASSO)
17 #define SPI_MODE_FIELD spi_readmode_f17_mod_00_2f
18 #define SPI_SPEED_FIELD spi_fastspeed_f17_mod_00_2f
Jon Murphy4f732422022-08-05 15:43:44 -060019#elif CONFIG(SOC_AMD_CEZANNE) | CONFIG(SOC_AMD_MENDOCINO)
Martin Rothb5b1c5a2021-08-09 13:47:48 -060020 #define SPI_MODE_FIELD spi_readmode_f17_mod_30_3f
21 #define SPI_SPEED_FIELD spi_fastspeed_f17_mod_30_3f
Martin Rothb5b1c5a2021-08-09 13:47:48 -060022#endif
23
Martin Rothb5b1c5a2021-08-09 13:47:48 -060024struct second_gen_efs { /* todo: expand for Server products */
Felix Helde240f872021-10-01 20:11:45 +020025 uint32_t gen:1; /* Client products only use bit 0 */
26 uint32_t reserved:31;
Martin Rothb5b1c5a2021-08-09 13:47:48 -060027} __attribute__((packed));
28
Kangheui Wonfab6e442021-10-18 15:35:28 +110029#define EFS_SECOND_GEN 0
30
Martin Rothb5b1c5a2021-08-09 13:47:48 -060031/* Copied from coreboot/util/amdfwtool.h */
Felix Held3c1c90b2021-10-18 14:04:01 +020032struct embedded_firmware {
Martin Rothb5b1c5a2021-08-09 13:47:48 -060033 uint32_t signature; /* 0x55aa55aa */
34 uint32_t imc_entry;
35 uint32_t gec_entry;
36 uint32_t xhci_entry;
Felix Held35360a92021-10-18 13:57:50 +020037 uint32_t psp_directory;
Felix Held4bdea412023-02-17 00:31:43 +010038 uint32_t new_psp_directory;
Martin Rothb5b1c5a2021-08-09 13:47:48 -060039 uint32_t bios0_entry;
40 uint32_t bios1_entry;
41 uint32_t bios2_entry;
42 struct second_gen_efs efs_gen;
43 uint32_t bios3_entry;
44 uint32_t reserved_2Ch;
45 uint32_t promontory_fw_ptr;
46 uint32_t lp_promontory_fw_ptr;
47 uint32_t reserved_38h;
48 uint32_t reserved_3Ch;
49 uint8_t spi_readmode_f15_mod_60_6f;
50 uint8_t fast_speed_new_f15_mod_60_6f;
51 uint8_t reserved_42h;
52 uint8_t spi_readmode_f17_mod_00_2f;
53 uint8_t spi_fastspeed_f17_mod_00_2f;
54 uint8_t qpr_dummy_cycle_f17_mod_00_2f;
55 uint8_t reserved_46h;
56 uint8_t spi_readmode_f17_mod_30_3f;
57 uint8_t spi_fastspeed_f17_mod_30_3f;
58 uint8_t micron_detect_f17_mod_30_3f;
59 uint8_t reserved_4Ah;
60 uint8_t reserved_4Bh;
61 uint32_t reserved_4Ch;
Felix Held3c1c90b2021-10-18 14:04:01 +020062} __attribute__((packed, aligned(16)));
Martin Rothb5b1c5a2021-08-09 13:47:48 -060063
Martin Rothb5b1c5a2021-08-09 13:47:48 -060064bool read_efs_spi_settings(uint8_t *mode, uint8_t *speed);
65
66#endif /* AMD_COMMON_PSP_EFS_H */