Jincheng Li | 6195357 | 2023-08-01 09:47:48 +0800 | [diff] [blame^] | 1 | /** @file |
| 2 | |
| 3 | Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR> |
| 4 | |
| 5 | Redistribution and use in source and binary forms, with or without modification, |
| 6 | are permitted provided that the following conditions are met: |
| 7 | |
| 8 | * Redistributions of source code must retain the above copyright notice, this |
| 9 | list of conditions and the following disclaimer. |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, this |
| 11 | list of conditions and the following disclaimer in the documentation and/or |
| 12 | other materials provided with the distribution. |
| 13 | * Neither the name of Intel Corporation nor the names of its contributors may |
| 14 | be used to endorse or promote products derived from this software without |
| 15 | specific prior written permission. |
| 16 | |
| 17 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 18 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 19 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 20 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
| 21 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 22 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 23 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 24 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 25 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 26 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF |
| 27 | THE POSSIBILITY OF SUCH DAMAGE. |
| 28 | |
| 29 | **/ |
| 30 | |
| 31 | #ifndef _SYSTEM_INFO_HOB_H_ |
| 32 | #define _SYSTEM_INFO_HOB_H_ |
| 33 | |
| 34 | #define SYSTEM_INFO_HOB_GUID { 0x7650A0F2, 0x0D91, 0x4B0C, { 0x92, 0x3B, 0xBD, 0xCF, 0x22, 0xD1, 0x64, 0x35 }} |
| 35 | |
| 36 | #ifndef MAX_SOCKET |
| 37 | #define MAX_SOCKET 4 |
| 38 | #endif |
| 39 | |
| 40 | #ifndef MAX_IIO_STACK |
| 41 | #define MAX_IIO_STACK 12 |
| 42 | #endif |
| 43 | |
| 44 | #define MAX_LOGIC_IIO_STACK 14 |
| 45 | |
| 46 | #ifndef MAX_IMC |
| 47 | #define MAX_IMC 4 // Maximum memory controllers per socket |
| 48 | #endif |
| 49 | |
| 50 | #ifndef MAX_MC_CH |
| 51 | #define MAX_MC_CH 2 // Max number of channels per MC (3 for EP) |
| 52 | #endif |
| 53 | |
| 54 | #ifndef MAX_CH |
| 55 | #define MAX_CH ((MAX_IMC)*(MAX_MC_CH)) // Max channels per socket (worst case EP * EX combination = 16) |
| 56 | #endif |
| 57 | |
| 58 | #define MAX_HPM_PFS_ENTRY_NUM 15 // Number of entries in PFS structure |
| 59 | #define HPM_PFS_ENTRY_SIZE 2 // Entry size of PFS structure in DWORD |
| 60 | |
| 61 | #pragma pack(1) |
| 62 | |
| 63 | #ifndef MMIO_BARS_ENUM |
| 64 | #define MMIO_BARS_ENUM |
| 65 | typedef enum { |
| 66 | TYPE_SCF_BAR = 0, |
| 67 | TYPE_PCU_BAR, |
| 68 | TYPE_MEM_BAR0, |
| 69 | TYPE_MEM_BAR1, |
| 70 | TYPE_MEM_BAR2, |
| 71 | TYPE_MEM_BAR3, |
| 72 | TYPE_MEM_BAR4, |
| 73 | TYPE_MEM_BAR5, |
| 74 | TYPE_MEM_BAR6, |
| 75 | TYPE_MEM_BAR7, |
| 76 | TYPE_SBREG_BAR, |
| 77 | TYPE_MAX_MMIO_BAR |
| 78 | } MMIO_BARS; |
| 79 | #endif |
| 80 | |
| 81 | typedef enum { |
| 82 | ReservedMemSs, |
| 83 | Ddr4MemSs = 1, |
| 84 | Ddr5MemSs = 2, |
| 85 | LpDdr4MemSs = 3, |
| 86 | LpDdr5MemSs = 4, |
| 87 | Hbm2MemSs = 5, |
| 88 | MrcMstMax, |
| 89 | MrcMstDelim = MAX_INT32 |
| 90 | } MRC_MST; |
| 91 | |
| 92 | typedef enum BootMode { |
| 93 | NormalBoot = 0, // Normal path through RC with full init, mem detection, init, training, etc. |
| 94 | // Some of these MRC specific init routines can be skipped based on MRC input params |
| 95 | // in addition to the sub-boot type (WarmBoot, WarmBootFast, etc). |
| 96 | S3Resume = 1 // S3 flow through RC. Should do the bare minimum required for S3 |
| 97 | // init and be optimized for speed. |
| 98 | } BootMode; |
| 99 | |
| 100 | // |
| 101 | // This is used to determine what type of die is connected to a UPI link |
| 102 | // |
| 103 | typedef enum { |
| 104 | UpiConnectionTypeCpu, |
| 105 | UpiConnectionTypePcieGen4, |
| 106 | UpiConnectionTypeFpga, |
| 107 | UpiConnectionTypeMax |
| 108 | } UPI_CONNECTION_TYPE; |
| 109 | |
| 110 | // |
| 111 | // VSEC info for HPM |
| 112 | // The HPM_INFO struct contains info collected from the VSEC structure for the HPM. |
| 113 | // VSEC Structure is defined as below: |
| 114 | // |
| 115 | // ------------------------VSEC Structure------------------------ |
| 116 | // | Next Cap Offset(12b) | Cap Version(4b) | PCIe Cap ID(16b) | |
| 117 | // -------------------------------------------------------------- |
| 118 | // | VSEC_LEN(12b) | VSEC_REV(4b) | VSEC_ID(16b) | |
| 119 | // -------------------------------------------------------------- |
| 120 | // | EntrySize(8b) | NumEntries(8b) | Rsvd(16b) | |
| 121 | // -------------------------------------------------------------- |
| 122 | // | Address(29b) | tBIR(3b) | |
| 123 | // -------------------------------------------------------------- |
| 124 | // |
| 125 | // |
| 126 | typedef struct { |
| 127 | UINT8 NumEntries; // The number of PM feature interface instances in this VSEC space |
| 128 | UINT8 EntrySize; // The entry size for each PM interface instance in 32-bit DWORDs |
| 129 | UINT32 Address; // The offset from the BAR register which is used for HPM to point to the base of the discovery entry. i.e. the PFS (PM Feature Structure) |
| 130 | UINT8 tBIR; // Which one of he function's BAR is used for the PFS offset |
| 131 | } HPM_INFO; |
| 132 | |
| 133 | // |
| 134 | //-------------------------------- - PFS Entry-------------------------------- |
| 135 | //| EntrySize(16b) | NumEntries(8b) | VSEC_SubID(8b) | |
| 136 | //---------------------------------------------------------------------------- |
| 137 | //| RSVD(14b) | Attr(2b) | CapOffset(16b) | |
| 138 | //---------------------------------------------------------------------------- |
| 139 | // |
| 140 | typedef struct { |
| 141 | UINT32 TpmiId : 8; |
| 142 | UINT32 NumEntries : 8; |
| 143 | UINT32 EntrySize : 16; |
| 144 | UINT32 CapOffset : 16; |
| 145 | UINT32 Attribute : 2; |
| 146 | UINT32 EntryBitMap : 8; |
| 147 | UINT32 Rsvd : 6; |
| 148 | } PFS_ENTRY; |
| 149 | |
| 150 | // |
| 151 | // HPM (Hierarchical Power Management) VSEC resource allocation info |
| 152 | // |
| 153 | typedef struct { |
| 154 | BOOLEAN HpmEnabled; // HPM enabled or not in BIOS knob |
| 155 | BOOLEAN HpmInfraReady; // All the HPM infrastructure data is buffered |
| 156 | UINT32 OobMsmHpmBarBase; // The base of OOBMSM BAR1 for HPM PFS and LUT tables |
| 157 | UINT32 OobMsmHpmBarLimit; // The limit of OOBMSM BAR1 from where the required size will be allocated |
| 158 | UINT32 OobMsmHpmBarMmcfgAddress; // The OOBMSM BAR1 MMCFG address |
| 159 | UINT32 OobMsmHpmBarRequiredSize; // The required size of OOBMSM BAR1 |
| 160 | |
| 161 | HPM_INFO HpmVsecInfo; // For now, single VSEC is assumed |
| 162 | PFS_ENTRY Pfs[MAX_HPM_PFS_ENTRY_NUM]; // The buffered PFS structure |
| 163 | |
| 164 | } HPM_VSEC_RESOURCE; |
| 165 | |
| 166 | // |
| 167 | // Stack id swap information, which includes stack swap flag and the new stack id swap array. |
| 168 | // |
| 169 | typedef struct { |
| 170 | BOOLEAN StackSwapFlag; |
| 171 | UINT8 StackIdSwapArray[MAX_IIO_STACK]; |
| 172 | } STACKID_SWAP_INFO; |
| 173 | |
| 174 | typedef struct { |
| 175 | UINT64 Cxl1p1RcrbBase; |
| 176 | BOOLEAN Cxl1p1RcrbValid; |
| 177 | } CXL_1P1_RCRB; |
| 178 | |
| 179 | typedef struct { |
| 180 | UINT32 StackPresentBitmap[MAX_SOCKET]; ///< bitmap of present stacks per socket |
| 181 | UINT8 StackBus[MAX_SOCKET][MAX_LOGIC_IIO_STACK];///< Bus of each stack |
| 182 | UINT32 StackMmiol[MAX_SOCKET][MAX_IIO_STACK]; ///< mmiol of each IIO stack, if it works as CXL, the mmiol base is RCRBBAR |
| 183 | UINT8 SocketFirstBus[MAX_SOCKET]; |
| 184 | UINT8 Socket10nmUboxBus0[MAX_SOCKET]; //10nm CPU use only |
| 185 | UINT8 TotIoDie[MAX_SOCKET]; //GNR & SRF CPU use only |
| 186 | UINT8 TotCmpDie[MAX_SOCKET]; //GNR & SRF CPU use only |
| 187 | UINT8 SocketLastBus[MAX_SOCKET]; |
| 188 | UINT8 segmentSocket[MAX_SOCKET]; |
| 189 | UINT8 KtiPortCnt; |
| 190 | UINT32 socketPresentBitMap; |
| 191 | UINT32 SecondaryNodeBitMap; |
| 192 | UINT32 FpgaPresentBitMap; |
| 193 | UINT32 mmCfgBase; |
| 194 | UINT64 SocketMmCfgBase[MAX_SOCKET]; |
| 195 | UINT8 DdrMaxCh; |
| 196 | UINT8 DdrMaxImc; ///< Logical number of IMC count, ignoring logical holes |
| 197 | UINT8 DdrPhysicalMaxImc; ///< Physical number of IMC count from Capid |
| 198 | UINT8 DdrNumChPerMc; |
| 199 | UINT8 DdrNumPseudoChPerCh; |
| 200 | UINT8 imcEnabled[MAX_SOCKET][MAX_IMC]; |
| 201 | UINT8 mcId[MAX_SOCKET][MAX_CH]; |
| 202 | MRC_MST MemSsType[MAX_SOCKET]; ///< MemSsType global identifier for DDR vs. HBM |
| 203 | UINT32 MmioBar[MAX_SOCKET][TYPE_MAX_MMIO_BAR]; |
| 204 | UINT8 HbmMaxCh; |
| 205 | UINT8 HbmMaxIoInst; |
| 206 | UINT8 HbmNumChPerMc; |
| 207 | UINT8 HbmNumChPerIo; |
| 208 | UINT32 LastCsrAddress[2]; |
| 209 | UINT32 LastCsrMmioAddr; |
| 210 | UINT8 CsrCachingEnable; |
| 211 | UINT32 LastCsrMcAddress[2]; |
| 212 | UINT32 LastCsrMcMmioPhyAddr; |
| 213 | UINT8 CsrPciBarCachingEnable; |
| 214 | UINT32 LastCsrPciBarAddr[2]; |
| 215 | UINT64 LastCsrPciBarPhyAddr; |
| 216 | UINT32 LastSBPortId[MAX_SOCKET]; |
| 217 | UPI_CONNECTION_TYPE UpiConnectionType[MAX_SOCKET]; |
| 218 | BOOLEAN PostedCsrAccessAllowed; // SW is allowed to use posted CSR writes method when TRUE |
| 219 | BOOLEAN PostedWritesEnabled; // All CSR writes use posted method when TRUE, non-posted when FALSE |
| 220 | BOOLEAN DataPopulated; // CPU_CSR_ACCESS_VAR is unavailable when FALSE |
| 221 | HPM_VSEC_RESOURCE SocketHpmVsecRes[MAX_SOCKET]; // HPM VSEC info for all sockets |
| 222 | BOOLEAN HbmSku; |
| 223 | UINT8 HcxType[MAX_SOCKET]; |
| 224 | STACKID_SWAP_INFO StackIdSwapInfo[MAX_SOCKET]; //StackID sync after do StackId swap,including Stack swap table and whether do stack swap |
| 225 | CXL_1P1_RCRB Cxl1p1Rcrb[MAX_SOCKET][MAX_IIO_STACK]; // CXL 1.1 RCRB, one per PI5 stack |
| 226 | UINT32 DmiRcrb[MAX_SOCKET]; // DMI RCRB region, one per socket |
| 227 | UINT8 FabricType; //Compute die 10x6, 10x5, and 6x5 type is stored |
| 228 | UINT8 ChopType; //Compute Die Chop Type |
| 229 | UINT8 MdfInstCount; |
| 230 | } CPU_CSR_ACCESS_VAR; |
| 231 | |
| 232 | typedef struct { |
| 233 | UINT32 MeRequestedSizeNv; |
| 234 | UINT32 MeRequestedAlignmentNv; |
| 235 | UINT8 SbspSocketIdNv; |
| 236 | } SYS_INFO_VAR_NVRAM; |
| 237 | |
| 238 | typedef struct _CPUID_REGISTER_INFO { |
| 239 | UINT32 Eax; |
| 240 | UINT32 Ebx; |
| 241 | UINT32 Ecx; |
| 242 | UINT32 Edx; |
| 243 | } CPUID_REGISTER_INFO; |
| 244 | |
| 245 | typedef struct _PROCESSOR_COMMON_INFO { |
| 246 | UINT32 capid0; |
| 247 | UINT32 capid1; |
| 248 | UINT32 capid2; |
| 249 | UINT32 capid3; |
| 250 | UINT32 capid4; |
| 251 | UINT32 capid5; |
| 252 | UINT32 capid6lo; |
| 253 | UINT32 capid6hi; |
| 254 | CPUID_REGISTER_INFO ExtCpuid7; |
| 255 | CPUID_REGISTER_INFO ExtCpuid1B; |
| 256 | } PROCESSOR_COMMON_INFO; |
| 257 | |
| 258 | typedef struct { |
| 259 | UINT32 MeRequestedSize; |
| 260 | UINT32 MeRequestedAlignment; |
| 261 | UINT32 CheckPoint; |
| 262 | UINT8 ResetRequired; |
| 263 | UINT8 Emulation; |
| 264 | BootMode SysBootMode; |
| 265 | CPU_CSR_ACCESS_VAR CpuCsrAccessVarHost; // Common resource for CsrAccessRoutines |
| 266 | UINT64 CpuFreq; |
| 267 | UINT8 SocketId; |
| 268 | SYS_INFO_VAR_NVRAM SysInfoVarNvram; |
| 269 | BOOLEAN UsraTraceControl; |
| 270 | UINT16 UsraTraceConfiguration; // Bit 7 6 5 4 3:0 |
| 271 | // Write, Modify, GetAddr, Long/Short, Trace 0x5 as signature |
| 272 | // Bit 15 14:11 10 9 8 |
| 273 | // DumpCpuCsrAccessVar, TBD, CSR, PCIE, Read |
| 274 | BOOLEAN CpuCsrAccessVarInfoDumped; |
| 275 | PROCESSOR_COMMON_INFO ProcessorCommonInfo[MAX_SOCKET]; |
| 276 | EFI_PHYSICAL_ADDRESS SocAddrMapData; |
| 277 | UINTN UsraPpiPtr; |
| 278 | } SYSTEM_INFO_VAR; |
| 279 | |
| 280 | |
| 281 | #pragma pack () |
| 282 | |
| 283 | #endif //#ifndef _SYSTEM_INFO_HOB_H_ |