Jincheng Li | 6195357 | 2023-08-01 09:47:48 +0800 | [diff] [blame^] | 1 | /** @file |
| 2 | |
| 3 | Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR> |
| 4 | |
| 5 | Redistribution and use in source and binary forms, with or without modification, |
| 6 | are permitted provided that the following conditions are met: |
| 7 | |
| 8 | * Redistributions of source code must retain the above copyright notice, this |
| 9 | list of conditions and the following disclaimer. |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, this |
| 11 | list of conditions and the following disclaimer in the documentation and/or |
| 12 | other materials provided with the distribution. |
| 13 | * Neither the name of Intel Corporation nor the names of its contributors may |
| 14 | be used to endorse or promote products derived from this software without |
| 15 | specific prior written permission. |
| 16 | |
| 17 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 18 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 19 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 20 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
| 21 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 22 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 23 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 24 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 25 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 26 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF |
| 27 | THE POSSIBILITY OF SUCH DAMAGE. |
| 28 | |
| 29 | **/ |
| 30 | |
| 31 | #ifndef _MEMORY_MAP_DATA_HOB_H_ |
| 32 | #define _MEMORY_MAP_DATA_HOB_H_ |
| 33 | |
| 34 | #define MEMORY_MAP_HOB_GUID { 0xf8870015, 0x6994, 0x4b98, { 0x95, 0xa2, 0xbd, 0x56, 0xda, 0x91, 0xc0, 0x7f } } |
| 35 | |
| 36 | #ifndef MAX_SOCKET |
| 37 | #define MAX_SOCKET 4 |
| 38 | #endif |
| 39 | |
| 40 | #ifndef MAX_IMC |
| 41 | #define MAX_IMC 4 // Maximum memory controllers per socket |
| 42 | #endif |
| 43 | |
| 44 | #ifndef MAX_MC_CH |
| 45 | #define MAX_MC_CH 2 // Max number of channels per MC (3 for EP) |
| 46 | #endif |
| 47 | |
| 48 | #ifndef MAX_CH |
| 49 | #define MAX_CH ((MAX_IMC)*(MAX_MC_CH)) // Max channels per socket (worst case EP * EX combination = 16) |
| 50 | #endif |
| 51 | |
| 52 | #define MAX_CXL_AMT 0 |
| 53 | |
| 54 | #ifndef MAX_UNIQUE_NGN_DIMM_INTERLEAVE |
| 55 | #define MAX_UNIQUE_NGN_DIMM_INTERLEAVE 2 // Max number of unique interleaves for NGN DIMM |
| 56 | #endif |
| 57 | |
| 58 | #ifndef MAX_SPARE_RANK |
| 59 | #define MAX_SPARE_RANK 2 // Max number of spare ranks in a channel |
| 60 | #endif |
| 61 | |
| 62 | #ifndef MAX_HBM_IO |
| 63 | #define MAX_HBM_IO 4 |
| 64 | #endif |
| 65 | |
| 66 | #ifndef MAX_DIMM |
| 67 | #define MAX_DIMM 2 // Max DIMM per channel |
| 68 | #endif |
| 69 | |
| 70 | #ifndef MAX_RANK_DIMM |
| 71 | #define MAX_RANK_DIMM 2 |
| 72 | #endif |
| 73 | |
| 74 | #ifndef MAX_DRAM_CLUSTERS |
| 75 | #define MAX_DRAM_CLUSTERS 4 |
| 76 | #endif |
| 77 | |
| 78 | #ifndef MAX_SAD_RULES |
| 79 | #define MAX_SAD_RULES 16 |
| 80 | #endif |
| 81 | |
| 82 | #ifndef MAX_FPGA_REMOTE_SAD_RULES |
| 83 | #define MAX_FPGA_REMOTE_SAD_RULES 2 // Maximum FPGA sockets exists on ICX platform |
| 84 | #endif |
| 85 | |
| 86 | #define MAX_SI_SOCKET 8 // Maximum silicon supported socket number |
| 87 | |
| 88 | #define MAX_AMT (MAX_IMC+MAX_CXL_AMT) // Max abstract memory target per socket |
| 89 | #define AMT_MAX_NODE ((MAX_AMT)*(MAX_SOCKET)) // Max abstract memory target for all sockets |
| 90 | |
| 91 | // NGN |
| 92 | #define NGN_MAX_SERIALNUMBER_STRLEN 4 |
| 93 | #define NGN_MAX_PARTNUMBER_STRLEN 30 |
| 94 | #define NGN_FW_VER_LEN 4 |
| 95 | #define NGN_LOG_TYPE_NUM 2 |
| 96 | #define NGN_LOG_LEVEL_NUM 2 |
| 97 | |
| 98 | /** |
| 99 | * Memory channel index conversion macros. |
| 100 | * |
| 101 | * We got two types of memory channel indexes: |
| 102 | * - socket channel - indexes 0..MAX_CH, used in [socket][channel] indexing |
| 103 | * - IMC channel - indexes 0..MAX_MC_CH, used in [socket][IMC][channel] indexing |
| 104 | * The below defined macros convert one channel index to the other one. |
| 105 | */ |
| 106 | #define MEM_SKTCH_TO_IMC(SktCh) ((SktCh) / MAX_MC_CH) |
| 107 | #define MEM_SKTCH_TO_IMCCH(SktCh) ((SktCh) % MAX_MC_CH) |
| 108 | #define MEM_IMCCH_TO_SKTCH(Imc, Ch) ((Imc) * MAX_MC_CH + (Ch)) |
| 109 | |
| 110 | #define MEM_64MB_TO_BYTES(Size64M) ((UINT64)(Size64M) << 26) |
| 111 | #define MEM_64MB_TO_KBYTES(Size64M) ((UINT64)(Size64M) << 16) |
| 112 | #define MEM_64MB_TO_MBYTES(Size64M) ((UINT64)(Size64M) << 6) |
| 113 | #define MEM_64MB_TO_GBYTES(Size64M) ((Size64M) >> 4) |
| 114 | #define MEM_BYTES_TO_64MB(SizeB) ((SizeB) >> 26) |
| 115 | #define MEM_KBYTES_TO_64MB(SizeKB) ((SizeKB) >> 16) |
| 116 | #define MEM_MBYTES_TO_64MB(SizeMB) ((SizeMB) >> 6) |
| 117 | |
| 118 | typedef UINT8 CXL_INTLV_SET_KEY; |
| 119 | |
| 120 | #define FSP_RESERVED1_LEN 77 |
| 121 | #define FSP_RESERVED2_LEN 2174 |
| 122 | #define FSP_RESERVED3_LEN 21 |
| 123 | #define FSP_RESERVED4_LEN 130 |
| 124 | #define FSP_RESERVED5_LEN 10 |
| 125 | #define FSP_RESERVED6_LEN 800 |
| 126 | #pragma pack(1) |
| 127 | |
| 128 | typedef enum { |
| 129 | DIMM_RANK_MAP_OUT_UNKNOWN = 0, |
| 130 | DIMM_RANK_MAP_OUT_MEM_DECODE, |
| 131 | DIMM_RANK_MAP_OUT_POP_POR_VIOLATION, |
| 132 | DIMM_RANK_MAP_OUT_RANK_DISABLED, |
| 133 | DIMM_RANK_MAP_OUT_ADVMEMTEST_FAILURE, |
| 134 | DIMM_RANK_MAP_OUT_MAX |
| 135 | } DIMM_RANK_MAP_OUT_REASON; |
| 136 | |
| 137 | struct RankDevice { |
| 138 | UINT8 enabled; // 0 = disabled, 1 = enabled |
| 139 | UINT8 logicalRank; // Logical Rank number (0 - 7) |
| 140 | UINT16 rankSize; // Units of 64 MB |
| 141 | }; |
| 142 | |
| 143 | struct PersisentDpaMap |
| 144 | { |
| 145 | UINT32 perRegionDPAOffset; |
| 146 | UINT32 SPALimit; |
| 147 | }; |
| 148 | |
| 149 | typedef struct firmwareRev { |
| 150 | UINT8 majorVersion; |
| 151 | UINT8 minorVersion; |
| 152 | UINT8 hotfixVersion; |
| 153 | UINT16 buildVersion; |
| 154 | } FIRMWARE_REV; |
| 155 | |
| 156 | typedef struct DimmDevice { |
| 157 | UINT8 Present; |
| 158 | BOOLEAN Enabled; |
| 159 | UINT8 DcpmmPresent; // 1 - This is a DCPMM |
| 160 | UINT8 X4Present; |
| 161 | UINT8 DramIoWidth; // Actual DRAM IO Width (4, 8, 16) |
| 162 | UINT8 NumRanks; |
| 163 | UINT8 keyByte; |
| 164 | UINT8 actKeyByte2; // Actual module type reported by SPD |
| 165 | UINT8 actSPDModuleOrg; // Actual number of DRAM ranks and device width |
| 166 | UINT8 dimmTs; // Thermal sensor data. |
| 167 | UINT16 VolCap; // Volatile capacity (AEP DIMM only) |
| 168 | UINT16 nonVolCap; // Non-volatile capacity (AEP DIMM only) |
| 169 | UINT16 DimmSize; |
| 170 | UINT32 NVmemSize; |
| 171 | UINT16 SPDMMfgId; // Module Mfg Id from SPD |
| 172 | UINT16 VendorID; |
| 173 | UINT16 DeviceID; |
| 174 | UINT16 RevisionID; |
| 175 | UINT32 perRegionDPA; // DPA of PMEM that Nfit needs |
| 176 | struct PersisentDpaMap perDPAMap[MAX_UNIQUE_NGN_DIMM_INTERLEAVE]; // DPA map |
| 177 | UINT8 serialNumber[NGN_MAX_SERIALNUMBER_STRLEN]; // Serial Number |
| 178 | UINT8 PartNumber[NGN_MAX_PARTNUMBER_STRLEN]; // Part Number |
| 179 | UINT8 FirmwareVersionStr[NGN_FW_VER_LEN]; // Used to update the SMBIOS TYPE 17 |
| 180 | struct firmwareRev FirmwareVersion; // Firmware revision |
| 181 | struct RankDevice rankList[MAX_RANK_DIMM]; |
| 182 | UINT16 InterfaceFormatCode; |
| 183 | UINT16 SubsystemVendorID; |
| 184 | UINT16 SubsystemDeviceID; |
| 185 | UINT16 SubsystemRevisionID; |
| 186 | UINT16 FisVersion; // Firmware Interface Specification version |
| 187 | UINT8 DimmSku; // Dimm SKU info |
| 188 | UINT8 manufacturingLocation; // Manufacturing location for the NVDIMM |
| 189 | UINT16 manufacturingDate; // Date the NVDIMM was manufactured |
| 190 | INT32 commonTck; |
| 191 | UINT8 EnergyType; // 0: 12V aux power; 1: dedicated backup energy source; 2: no backup energy source |
| 192 | BOOLEAN NvDimmNPresent; // JEDEC NVDIMM-N Type Memory Present |
| 193 | UINT8 CidBitMap; // SubRankPer CS for DIMM device |
| 194 | UINT16 SPDRegVen; // Register Vendor ID in SPD |
| 195 | DIMM_RANK_MAP_OUT_REASON MapOutReason; |
| 196 | } MEMMAP_DIMM_DEVICE_INFO_STRUCT; |
| 197 | |
| 198 | struct ChannelDevice { |
| 199 | UINT8 Enabled; // 0 = channel disabled, 1 = channel enabled |
| 200 | UINT8 Features; // Bit mask of features to enable or disable |
| 201 | UINT8 MaxDimm; // Number of DIMM |
| 202 | UINT8 NumRanks; // Number of ranks on this channel |
| 203 | UINT8 chFailed; |
| 204 | UINT8 ngnChFailed; |
| 205 | UINT8 Is9x4DimmPresent; // 9x4 dimm present indicator |
| 206 | UINT8 SpareLogicalRank[MAX_SPARE_RANK]; // Logical rank, selected as Spare |
| 207 | UINT8 SparePhysicalRank[MAX_SPARE_RANK]; // Physical rank, selected as spare |
| 208 | UINT16 SpareRankSize[MAX_SPARE_RANK]; // spare rank size |
| 209 | UINT8 EnabledLogicalRanks; // Bitmap of Logical ranks that are enabled |
| 210 | UINT8 DdrPopulationMap; // Bitmap to indicate location of DDR DIMMs within the channel memory slots (BIT0: Ch.D0, BIT1: CH.D1) |
| 211 | UINT8 PmemPopulationMap; // Bitmap to indicate location of PMem modules within the channel memory slots (BIT0: Ch.D0, BIT1: CH.D1) |
| 212 | MEMMAP_DIMM_DEVICE_INFO_STRUCT DimmInfo[MAX_DIMM]; |
| 213 | }; |
| 214 | |
| 215 | struct memcontroller { |
| 216 | UINT32 MemSize; |
| 217 | }; |
| 218 | |
| 219 | typedef enum { |
| 220 | MemTypeNone = 0, |
| 221 | MemType1lmDdr, |
| 222 | MemType1lmAppDirect, |
| 223 | MemType1lmAppDirectReserved, |
| 224 | MemType1lmCtrl, |
| 225 | MemType1lmHbm, |
| 226 | MemTypeNxm, |
| 227 | MemType2lmDdrCacheMemoryMode, |
| 228 | MemType2lmDdrWbCacheAppDirect, |
| 229 | MemType2lmHbmCacheDdr, |
| 230 | MemType2lmHbmCacheMemoryMode, |
| 231 | MemTypeCxlAccVolatileMem, |
| 232 | MemTypeCxlAccPersistentMem, |
| 233 | MemTypeFpga, |
| 234 | MemTypeCxlExpVolatileMem, |
| 235 | MemTypeCxlExpPersistentMem, |
| 236 | MemTypeCxl2lmDdrCacheMem, |
| 237 | MemTypeCxlHetero, |
| 238 | MemTypeMax |
| 239 | } MEM_TYPE; |
| 240 | |
| 241 | typedef struct SADTable { |
| 242 | UINT8 Enable; // Rule enable |
| 243 | MEM_TYPE type; // Bit map of memory region types, See defines 'MEM_TYPE_???' above for bit definitions of the ranges. |
| 244 | UINT8 granularity; // Interleave granularities for current SAD entry. Possible interleave granularity options depend on the SAD entry type. Note that SAD entry type BLK Window and CSR/Mailbox/Ctrl region do not support any granularity options |
| 245 | UINT32 Base; // Base of the current SAD entry |
| 246 | UINT32 Limit; // Limit of the current SAD entry |
| 247 | UINT8 ways; // Interleave ways for SAD |
| 248 | UINT8 channelInterBitmap[MAX_AMT]; //Bit map to denote which DDR4/NM channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved |
| 249 | UINT8 FMchannelInterBitmap[MAX_AMT]; //Bit map to denote which FM channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved |
| 250 | UINT8 NmChWays; // Channel Interleave ways for SAD. Represents channelInterBitmap ways for DDR4/NM. |
| 251 | UINT8 FmChWays; // Channel Interleave ways for SAD. Represents FMchannelInterBitmap ways for DDRT. |
| 252 | UINT16 imcInterBitmap; // Bit map to denote which IMCs are interleaved from this socket. |
| 253 | UINT16 NmImcInterBitmap; // Bit map to denote which IMCs are interleaved from this socket as NM. |
| 254 | BOOLEAN local; // 0 - Remote 1- Local |
| 255 | UINT8 IotEnabled; // To indicate if IOT is enabled |
| 256 | UINT8 mirrored; // To Indicate the SAD is mirrored while enabling partial mirroring |
| 257 | UINT8 Attr; |
| 258 | UINT8 tgtGranularity; // Interleave mode for target list |
| 259 | UINT8 Cluster; // SNC cluster, hemisphere, or quadrant index. |
| 260 | UINT8 HostBridgeGran; // Host bridge interleaving granularity. |
| 261 | UINT32 HotPlugPadSize; // Memory size padded for CXL hot plug. 0 if it is not a CXL hot plug SAD. |
| 262 | CXL_INTLV_SET_KEY CxlIntlvSetKey; // The unique key of CXL interleave set. (7nm) |
| 263 | } SAD_TABLE; |
| 264 | |
| 265 | typedef struct socket { |
| 266 | UINT8 SocketEnabled; |
| 267 | UINT32 IioStackBitmap; |
| 268 | BOOLEAN HbmIoEn[MAX_HBM_IO]; // Flag indicates if HBM IO is enabled. TRUE: HBM IO is Enabled, FALSE: HBM IO is disabled. |
| 269 | UINT8 imcEnabled[MAX_IMC]; |
| 270 | UINT8 SadIntList[MAX_DRAM_CLUSTERS * MAX_SAD_RULES][AMT_MAX_NODE]; // SAD interleave list |
| 271 | UINT32 SktTotMemMapSPA; // Total memory mapped to SPA |
| 272 | UINT32 SktMemSize2LM; // Total memory excluded from Limit |
| 273 | SAD_TABLE SAD[MAX_DRAM_CLUSTERS * MAX_SAD_RULES]; // SAD table |
| 274 | struct memcontroller imc[MAX_IMC]; |
| 275 | struct ChannelDevice ChannelInfo[MAX_CH]; |
| 276 | } MEMMAP_SOCKET; |
| 277 | |
| 278 | typedef struct { |
| 279 | UINT8 Enabled; // Indicates if this EDC is enabled |
| 280 | UINT32 MemAsCache; // Memory used as Cache, in 64MB units |
| 281 | UINT32 MemAsFlat; // Memory used as Flat memory, in 64MB units |
| 282 | } EDC_INFO; |
| 283 | |
| 284 | typedef struct SystemMemoryMapElement { |
| 285 | UINT16 Type; // Type of this memory element; Bit0: 1LM Bit1: 2LM Bit2: PMEM Bit3: PMEM-cache Bit4: BLK Window Bit5: CSR/Mailbox/Ctrl region |
| 286 | UINT8 NodeId; // Node ID of the HA Owning the memory |
| 287 | UINT8 SocketId; // Socket Id of socket that has his memory - ONLY IN NUMA |
| 288 | UINT8 SktInterBitmap; // Socket interleave bitmap, if more that on socket then ImcInterBitmap and ChInterBitmap are identical in all sockets |
| 289 | UINT16 ImcInterBitmap; // IMC interleave bitmap for this memory |
| 290 | UINT8 ChInterBitmap[MAX_IMC];//Bit map to denote which channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved |
| 291 | UINT32 BaseAddress; // Base Address of the element in 64MB chunks |
| 292 | UINT32 ElementSize; // Size of this memory element in 64MB chunks |
| 293 | } SYSTEM_MEMORY_MAP_ELEMENT; |
| 294 | |
| 295 | typedef struct SystemMemoryMapHob { |
| 296 | // |
| 297 | // Total Clusters. In SNC2 mode there are 2 clusters and SNC4 mode has 4 clusters. |
| 298 | // All2All/Quad/Hemi modes can be considered as having only one cluster (i.e SNC1). |
| 299 | // |
| 300 | UINT8 TotalClusters; |
| 301 | |
| 302 | UINT8 reserved1[FSP_RESERVED1_LEN]; // MEMORY_MAP_BLOCK_DECODER_DATA BlockDecoderData; // block decoder data structure |
| 303 | UINT32 lowMemBase; // Mem base in 64MB units for below 4GB mem. |
| 304 | UINT32 lowMemSize; // Mem size in 64MB units for below 4GB mem. |
| 305 | UINT32 highMemBase; // Mem base in 64MB units for above 4GB mem. |
| 306 | UINT32 highMemSize; // Mem size in 64MB units for above 4GB mem. |
| 307 | UINT32 memSize; // Total physical memory size |
| 308 | UINT16 memFreq; // Mem Frequency |
| 309 | UINT16 HbmFreq; // HBM Frequency in MHz. |
| 310 | UINT8 memMode; // 0 - Independent, 1 - Lockstep |
| 311 | UINT8 volMemMode; // 0 - 1LM, 1 - 2LM |
| 312 | UINT8 CacheMemType; // 0 - DDR$DDRT, 1 - HBM$DDR. Only valid if volMemMode is 2LM |
| 313 | UINT16 DramType; |
| 314 | UINT8 DdrVoltage; |
| 315 | BOOLEAN SupportedPMemPresent; // TRUE if at least one PMem is present and supported by BIOS |
| 316 | BOOLEAN EkvPresent; // Set if EKV controller on system |
| 317 | BOOLEAN BwvPresent; // Set if BWV controller on system |
| 318 | BOOLEAN CwvPresent; // Set if CWV controller on system |
| 319 | UINT8 XMPProfilesSup; |
| 320 | UINT8 XMPCapability; |
| 321 | // |
| 322 | // HBM Specific Info. |
| 323 | // |
| 324 | UINT16 HbmInstances[MAX_SOCKET]; // Total HBM instances |
| 325 | UINT32 HbmFlatMemSize; // Total HBM memory size in 64MB units, if HBM used as Flat memory |
| 326 | UINT32 HbmCacheMemSize; // Total HBM memory used as cache, if HBM used as Cache memory |
| 327 | UINT16 HbmSpeed; // Configured HBM (i.e OPIO channel) speed in MT/s. |
| 328 | UINT16 MaxHbmSpeed; // Max HBM (i.e OPIO channel) speed in MT/s. |
| 329 | UINT8 SystemRasType; |
| 330 | UINT8 RasModesEnabled; // RAS modes that are enabled |
| 331 | UINT16 ExRasModesEnabled; // Extended RAS modes that are enabled |
| 332 | UINT8 sncEnabled; // 0 - SNC disabled for this configuration, 1 - SNC enabled for this configuration |
| 333 | UINT8 NumOfCluster; |
| 334 | UINT8 NumChPerMC; |
| 335 | UINT8 numberEntries; // Number of Memory Map Elements |
| 336 | SYSTEM_MEMORY_MAP_ELEMENT Element[(MAX_SOCKET * MAX_DRAM_CLUSTERS * MAX_SAD_RULES) + MAX_FPGA_REMOTE_SAD_RULES]; |
| 337 | UINT8 reserved2[FSP_RESERVED2_LEN]; // struct memSetup MemSetup; |
| 338 | UINT8 reserved3[FSP_RESERVED3_LEN]; // MEM_DFXMEMVARS DfxMemVar; |
| 339 | MEMMAP_SOCKET Socket[MAX_SOCKET]; |
| 340 | UINT8 reserved4[FSP_RESERVED4_LEN]; // struct memTiming profileMemTime[XMP_MAX_PROFILES]; |
| 341 | |
| 342 | UINT8 reserved5[FSP_RESERVED5_LEN]; // RASMEMORYINFO RasMeminfo; |
| 343 | UINT8 LatchSystemShutdownState; |
| 344 | BOOLEAN IsWpqFlushSupported; |
| 345 | UINT8 EadrSupport; |
| 346 | UINT8 EadrCacheFlushMode; |
| 347 | UINT8 SetSecureEraseSktChHob[MAX_SOCKET][MAX_CH]; //MAX_CH * MAX_SOCKET * MAX_DCPMM_CH |
| 348 | UINT8 reserved6[FSP_RESERVED6_LEN]; // HOST_DDRT_DIMM_DEVICE_INFO_STRUCT HostDdrtDimmInfo[MAX_SOCKET][MAX_CH]; |
| 349 | UINT32 DdrCacheSize[MAX_SOCKET][MAX_CH]; // Size of DDR memory reserved for 2LM cache (64MB granularity) |
| 350 | BOOLEAN AdrStateForPmemModule[MAX_SOCKET][MAX_CH]; // ADR state for Intel PMEM Modules |
| 351 | UINT16 BiosFisVersion; // Firmware Interface Specification version currently supported by BIOS |
| 352 | UINT16 MaxAveragePowerLimit; // Max Power limit in mW used for averaged power ( Valid range ends at 15000mW) |
| 353 | UINT16 MinAveragePowerLimit; // Min Power limit in mW used for averaged power ( Valid range starts from 10000mW) |
| 354 | UINT16 CurrAveragePowerLimit; // Current Power limit in mW used for average power |
| 355 | UINT16 MaxMbbPowerLimit; // Max MBB power limit ( Valid range ends at 18000mW). |
| 356 | UINT16 MinMbbPowerLimit; // Min MBB power limit ( Valid range starts from 15000mW). |
| 357 | UINT16 CurrMbbPowerLimit; // Current Power limit in mW used for MBB power |
| 358 | UINT32 MaxMbbAveragePowerTimeConstant; // Max MBB Average Power Time Constant |
| 359 | UINT32 MinMbbAveragePowerTimeConstant; // Min MBB Average Power Time Constant |
| 360 | UINT32 CurrMbbAveragePowerTimeConstant; // Current MBB Average Power Time Constant |
| 361 | UINT32 MmiohBase; // MMIOH base in 64MB granularity |
| 362 | UINT8 MaxSadRules; // Maximum SAD entries supported by silicon (24 for 14nm silicon, 16 for 10nm silicon) |
| 363 | UINT8 NumberofChaDramClusters; // Number of CHA DRAM decoder clusters |
| 364 | BOOLEAN VirtualNumaEnable; // Enable or Disable Virtual NUMA |
| 365 | UINT8 VirtualNumOfCluster; // Number of Virtual NUMA nodes in each physical NUMA node (Socket or SNC cluster) |
| 366 | } SYSTEM_MEMORY_MAP_HOB; |
| 367 | |
| 368 | #pragma pack() |
| 369 | |
| 370 | #endif // _MEMORY_MAP_DATA_H_ |