Gitiles
Code Review Sign In
review.coreboot.org / coreboot / 619535778cf7c6b141f8c13b967995327108a50a / . / src / vendorcode / intel / fsp / fsp2_0 / graniterapids / sp / IioPcieConfigUpd.h
blob: 65c2a42ff9edd831520d6ea698740e58e3eb4db7 [file] [log] [blame]
Jincheng Li61953572023-08-01 09:47:48 +0800[diff] [blame^]1/** @file
2
3Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR>
4
5Redistribution and use in source and binary forms, with or without modification,
6are permitted provided that the following conditions are met:
7
8* Redistributions of source code must retain the above copyright notice, this
9 list of conditions and the following disclaimer.
10* Redistributions in binary form must reproduce the above copyright notice, this
11 list of conditions and the following disclaimer in the documentation and/or
12 other materials provided with the distribution.
13* Neither the name of Intel Corporation nor the names of its contributors may
14 be used to endorse or promote products derived from this software without
15 specific prior written permission.
16
17 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
21 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 THE POSSIBILITY OF SUCH DAMAGE.
28
29**/
30
31#ifndef _IIO_PCIE_CONFIG_UPD_H_
32#define _IIO_PCIE_CONFIG_UPD_H_
33
34#ifndef MAX_SOCKET
35#define MAX_SOCKET 4
36#endif
37
38#ifndef MAX_LOGIC_IIO_STACK
39#define MAX_LOGIC_IIO_STACK 14
40#endif
41
42#ifndef MAX_IIO_PORTS_PER_SOCKET
43#define MAX_IIO_PORTS_PER_SOCKET 57
44#endif
45
46#ifndef MAX_IOU_PER_SOCKET
47#define MAX_IOU_PER_SOCKET 7
48#endif
49
50#define MAX_VMD_STACKS_PER_SOCKET 8 // Max number of stacks per socket supported by VMD
51
52#pragma pack(1)
53
54typedef enum {
55 PE0 = 0,
56 PE_MAX,
57 PE_ = 0xFF // temporary unknown value
58} IIO_PACKAGE_PE;
59
60typedef struct {
61 UINT8 SLOTEIP[MAX_IIO_PORTS_PER_SOCKET]; // Electromechanical Interlock Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B17)
62 UINT8 SLOTHPCAP[MAX_IIO_PORTS_PER_SOCKET]; // Slot Hot Plug capable - Slot Capabilities (D0-10 / F0 / R0xA4 / B6)
63 UINT8 SLOTHPSUP[MAX_IIO_PORTS_PER_SOCKET]; // Hot Plug surprise supported - Slot Capabilities (D0-10 / F0 / R0xA4 / B5)
64 UINT8 SLOTPIP[MAX_IIO_PORTS_PER_SOCKET]; // Power Indicator Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B4)
65 UINT8 SLOTAIP[MAX_IIO_PORTS_PER_SOCKET]; // Attention Inductor Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B3)
66 UINT8 SLOTMRLSP[MAX_IIO_PORTS_PER_SOCKET]; // MRL Sensor Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B2)
67 UINT8 SLOTPCP[MAX_IIO_PORTS_PER_SOCKET]; // Power Controller Present - Slot Capabilities (D0-10 / F0 / R0xA4 /B1)
68 UINT8 SLOTABP[MAX_IIO_PORTS_PER_SOCKET]; // Attention Button Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B0)
69 UINT8 SLOTIMP[MAX_IIO_PORTS_PER_SOCKET];
70 UINT8 SLOTSPLS[MAX_IIO_PORTS_PER_SOCKET];
71 UINT8 SLOTSPLV[MAX_IIO_PORTS_PER_SOCKET];
72 UINT16 SLOTPSP[MAX_IIO_PORTS_PER_SOCKET];
73 BOOLEAN VppEnabled[MAX_IIO_PORTS_PER_SOCKET]; // 00 -- Disable, 01 -- Enable //no setup option defined- aj
74 UINT8 VppPort[MAX_IIO_PORTS_PER_SOCKET]; // 00 -- Port 0, 01 -- Port 1 //no setup option defined- aj
75 UINT8 VppAddress[MAX_IIO_PORTS_PER_SOCKET]; // 01-07 for SMBUS address of Vpp //no setup option defined- aj
76 UINT8 MuxAddress[MAX_IIO_PORTS_PER_SOCKET]; // SMBUS address of MUX //no setup option defined
77 UINT8 ChannelID[MAX_IIO_PORTS_PER_SOCKET]; // 00 -- channel 0, 01 -- channel 1 //no setup option defined
78
79 UINT8 PciePortEnable[MAX_IIO_PORTS_PER_SOCKET];
80 UINT8 PEXPHIDE[MAX_IIO_PORTS_PER_SOCKET]; // Hide any of the DMI or PCIE devices - SKT 0,1,2,3; Device 0-10 PRD
81 UINT8 HidePEXPMenu[MAX_IIO_PORTS_PER_SOCKET]; // to suppress /display the PCIe port menu
82 UINT8 PciePortOwnership[MAX_IIO_PORTS_PER_SOCKET];
83 UINT8 RetimerConnectCount[MAX_IIO_PORTS_PER_SOCKET];
84 UINT8 ConfigIOU[MAX_IOU_PER_SOCKET]; // 00-x4x4x4x4, 01-x4x4x8NA, 02-x8NAx4x4, 03-x8NAx8NA, 04-x16 (P1p2p3p4)
85 UINT8 PcieHotPlugOnPort[MAX_IIO_PORTS_PER_SOCKET]; // Manual override of hotplug for port
86 UINT8 VMDEnabled[MAX_VMD_STACKS_PER_SOCKET];
87 UINT8 VMDPortEnable[MAX_IIO_PORTS_PER_SOCKET];
88 UINT8 VMDHotPlugEnable[MAX_VMD_STACKS_PER_SOCKET];
89 UINT8 PcieMaxPayload[MAX_IIO_PORTS_PER_SOCKET];
90 UINT8 PciePortLinkSpeed[MAX_IIO_PORTS_PER_SOCKET]; // auto - 0(default); gen1 -1; gen2 -2; ... gen5 -5.
91 UINT8 DfxDnTxPresetGen3[MAX_IIO_PORTS_PER_SOCKET]; //auto - 0xFF(default); p0 - 0; p1 -1; ... p9 - 9.
92 UINT8 PcieGlobalAspm;
93 UINT8 PcieMaxReadRequestSize;
94} UPD_IIO_PCIE_PORT_CONFIG;
95
96typedef struct {
97 UINT8 Address;
98 UINT8 Port;
99 UINT8 MuxAddress;
100 UINT8 MuxChannel;
101} IIO_VPP_CFG;
102
103typedef struct {
104 UINT8 Eip : 1; // Electromechanical Interlock Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B17)
105 UINT8 HotPlugSurprise : 1; // Hot Plug surprise supported - Slot Capabilities (D0-10 / F0 / R0xA4 / B5)
106 UINT8 PowerInd : 1; // Power Indicator Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B4)
107 UINT8 AttentionInd : 1; // Attention Inductor Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B3)
108 UINT8 PowerCtrl : 1; // Power Controller Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B1)
109 UINT8 AttentionBtn : 1; // Attention Button Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B0)
110
111 UINT8 Reserved : 2;
112} IIO_SLOT_CFG;
113
114typedef struct {
115
116 IIO_VPP_CFG Vpp;
117 IIO_SLOT_CFG Slot;
118
119 UINT8 VppEnabled :1;
120 UINT8 VppExpType :1;
121
122 UINT8 SlotImplemented :1;
123 UINT8 Reserved :4;
124
125 UINT16 HotPlug : 1; // If hotplug is supported on slot connected to this port
126 UINT16 MrlSensorPresent : 1; // If MRL is present on slot connected to this port
127 UINT16 SlotPowerLimitScale : 2; // Slot Power Scale for slot connected to this port
128 UINT16 SlotPowerLimitValue : 12; // Slot Power Value for slot connected to this port
129
130 UINT16 PhysicalSlotNumber; // Slot number for slot connected to this port
131} IIO_BOARD_SETTINGS_PER_PORT;
132
133typedef struct {
134 struct {
135 UINT8 Segment; ///< Remember segment, if it changes reset everything
136 UINT8 StackPciBusPoolSize[MAX_LOGIC_IIO_STACK]; ///< Number of bus numbers needed for IIO stack
137 } Socket[MAX_SOCKET];
138} SYSTEM_PCI_BUS_CONFIGURATION;
139
140typedef struct {
141 UINT64 Base; ///< Base (starting) address of a range (I/O, 32 and 64-bit mmio regions)
142 UINT64 Limit; ///< Limit (last valid) address of a range
143} PCIE_BASE_LIMIT;
144
145typedef struct {
146 UINT32 MmioLSize;
147 UINT64 MmioHSize;
148} CXL11_LIMITS;
149
150typedef struct {
151 PCIE_BASE_LIMIT Io; ///< Base and limit of I/O range assigned to entity
152 PCIE_BASE_LIMIT LowMmio; ///< Base and limit of low MMIO region for entity
153 PCIE_BASE_LIMIT HighMmio; ///< Base and limit of high (64-bit) MMIO region for entity
154} PCI_BASE_LIMITS;
155
156typedef struct {
157 PCI_BASE_LIMITS SocketLimits; ///< Base and Limit of all PCIe resources for the socket
158 PCI_BASE_LIMITS StackLimits[MAX_LOGIC_IIO_STACK]; ///< Base and Limit of all PCIe resources for each stack of the socket
159 CXL11_LIMITS CxlStackReq[MAX_LOGIC_IIO_STACK]; ///< Base and Limit of CXL11 resources for each stack of the socket
160} SOCKET_PCI_BASE_LIMITS;
161
162typedef struct {
163 //
164 // Save basic system configuration parameters along with the resource map to detect a change.
165 // Remember low and high I/O memory range when saving recource configuration. It is used to verify
166 // whether system memory map changed. Remember also stacks configured when creating the map.
167 // If anything changed reset the system PCI resource configuration.
168 //
169 UINT64 MmioHBase;
170 UINT64 MmioHGranularity;
171 UINT32 MmioLBase;
172 UINT32 MmioLLimit;
173 UINT32 MmioLGranularity;
174 UINT16 IoBase;
175 UINT16 IoLimit;
176 UINT16 IoGranularity;
177 UINT32 StackPresentBitmap[MAX_SOCKET];
178 //
179 // Used by the PciHostBridge DXE driver, these variables don't need to be exposed through setup options
180 // The variables are used as a communication vehicle from the PciHostBridge DXE driver to an OEM hook
181 // which updates the KTI resource map.
182 //
183 SOCKET_PCI_BASE_LIMITS Socket[MAX_SOCKET]; ///< Base and limit of all PCIe resources for each socket
184} SYSTEM_PCI_BASE_LIMITS;
185
186#define IIO_BIFURCATE_xxxxxxxx 0xFE
187#define IIO_BIFURCATE_x4x4x4x4 0x0
188#define IIO_BIFURCATE_x4x4xxx8 0x1
189#define IIO_BIFURCATE_xxx8x4x4 0x2
190#define IIO_BIFURCATE_xxx8xxx8 0x3
191#define IIO_BIFURCATE_xxxxxx16 0x4
192#define IIO_BIFURCATE_x2x2x4x8 0x5
193#define IIO_BIFURCATE_x4x2x2x8 0x6
194#define IIO_BIFURCATE_x8x2x2x4 0x7
195#define IIO_BIFURCATE_x8x4x2x2 0x8
196#define IIO_BIFURCATE_x2x2x4x4x4 0x9
197#define IIO_BIFURCATE_x4x2x2x4x4 0xA
198#define IIO_BIFURCATE_x4x4x2x2x4 0xB
199#define IIO_BIFURCATE_x4x4x4x2x2 0xC
200#define IIO_BIFURCATE_x2x2x2x2x8 0xD
201#define IIO_BIFURCATE_x8x2x2x2x2 0xE
202#define IIO_BIFURCATE_x2x2x2x2x4x4 0xF
203#define IIO_BIFURCATE_x2x2x4x2x2x4 0x10
204#define IIO_BIFURCATE_x2x2x4x4x2x2 0x11
205#define IIO_BIFURCATE_x4x2x2x2x2x4 0x12
206#define IIO_BIFURCATE_x4x2x2x4x2x2 0x13
207#define IIO_BIFURCATE_x4x4x2x2x2x2 0x14
208#define IIO_BIFURCATE_x2x2x2x2x2x2x4 0x15
209#define IIO_BIFURCATE_x2x2x2x2x4x2x2 0x16
210#define IIO_BIFURCATE_x2x2x4x2x2x2x2 0x17
211#define IIO_BIFURCATE_x4x2x2x2x2x2x2 0x18
212#define IIO_BIFURCATE_x2x2x2x2x2x2x2x2 0x19
213#define IIO_BIFURCATE_AUTO 0xFF
214
215typedef enum {
216 IioBifurcation_UNKNOWN = IIO_BIFURCATE_xxxxxxxx,
217 IioBifurcation_x4x4x4x4 = IIO_BIFURCATE_x4x4x4x4,
218 IioBifurcation_x4x4xxx8 = IIO_BIFURCATE_x4x4xxx8,
219 IioBifurcation_xxx8x4x4 = IIO_BIFURCATE_xxx8x4x4,
220 IioBifurcation_xxx8xxx8 = IIO_BIFURCATE_xxx8xxx8,
221 IioBifurcation_xxxxxx16 = IIO_BIFURCATE_xxxxxx16,
222 IioBifurcation_x2x2x4x8 = IIO_BIFURCATE_x2x2x4x8,
223 IioBifurcation_x4x2x2x8 = IIO_BIFURCATE_x4x2x2x8,
224 IioBifurcation_x8x2x2x4 = IIO_BIFURCATE_x8x2x2x4,
225 IioBifurcation_x8x4x2x2 = IIO_BIFURCATE_x8x4x2x2,
226 IioBifurcation_x2x2x4x4x4 = IIO_BIFURCATE_x2x2x4x4x4,
227 IioBifurcation_x4x2x2x4x4 = IIO_BIFURCATE_x4x2x2x4x4,
228 IioBifurcation_x4x4x2x2x4 = IIO_BIFURCATE_x4x4x2x2x4,
229 IioBifurcation_x4x4x4x2x2 = IIO_BIFURCATE_x4x4x4x2x2,
230 IioBifurcation_x2x2x2x2x8 = IIO_BIFURCATE_x2x2x2x2x8,
231 IioBifurcation_x8x2x2x2x2 = IIO_BIFURCATE_x8x2x2x2x2,
232 IioBifurcation_x2x2x2x2x4x4 = IIO_BIFURCATE_x2x2x2x2x4x4,
233 IioBifurcation_x2x2x4x2x2x4 = IIO_BIFURCATE_x2x2x4x2x2x4,
234 IioBifurcation_x2x2x4x4x2x2 = IIO_BIFURCATE_x2x2x4x4x2x2,
235 IioBifurcation_x4x2x2x2x2x4 = IIO_BIFURCATE_x4x2x2x2x2x4,
236 IioBifurcation_x4x2x2x4x2x2 = IIO_BIFURCATE_x4x2x2x4x2x2,
237 IioBifurcation_x4x4x2x2x2x2 = IIO_BIFURCATE_x4x4x2x2x2x2,
238 IioBifurcation_x2x2x2x2x2x2x4 = IIO_BIFURCATE_x2x2x2x2x2x2x4,
239 IioBifurcation_x2x2x2x2x4x2x2 = IIO_BIFURCATE_x2x2x2x2x4x2x2,
240 IioBifurcation_x2x2x4x2x2x2x2 = IIO_BIFURCATE_x2x2x4x2x2x2x2,
241 IioBifurcation_x4x2x2x2x2x2x2 = IIO_BIFURCATE_x4x2x2x2x2x2x2,
242 IioBifurcation_x2x2x2x2x2x2x2x2 = IIO_BIFURCATE_x2x2x2x2x2x2x2x2,
243 IioBifurcation_Auto = IIO_BIFURCATE_AUTO
244} IIO_BIFURCATION;
245
246typedef struct {
247 IIO_BIFURCATION Bifurcation;
248 UINT8 CxlSupportInUba :1;
249 UINT8 Reserved :7;
250
251 IIO_BOARD_SETTINGS_PER_PORT Port[MAX_IIO_PORTS_PER_STACK];
252} IIO_BOARD_SETTINGS_PER_PE;
253
254typedef struct {
255 IIO_BOARD_SETTINGS_PER_PE Pe[MAX_IIO_PCIE_PER_SOCKET];
256} IIO_BOARD_SETTINGS_PER_SOCKET;
257
258typedef struct {
259 IIO_BOARD_SETTINGS_PER_SOCKET Socket[MAX_SOCKET];
260} IIO_BOARD_SETTINGS_HOB;
261
262#pragma pack()
263
264#endif // _IIO_PCIE_CONFIG_UPD_H_