Jincheng Li | 6195357 | 2023-08-01 09:47:48 +0800 | [diff] [blame^] | 1 | /** @file |
| 2 | |
| 3 | Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> |
| 4 | |
| 5 | Redistribution and use in source and binary forms, with or without modification, |
| 6 | are permitted provided that the following conditions are met: |
| 7 | |
| 8 | * Redistributions of source code must retain the above copyright notice, this |
| 9 | list of conditions and the following disclaimer. |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, this |
| 11 | list of conditions and the following disclaimer in the documentation and/or |
| 12 | other materials provided with the distribution. |
| 13 | * Neither the name of Intel Corporation nor the names of its contributors may |
| 14 | be used to endorse or promote products derived from this software without |
| 15 | specific prior written permission. |
| 16 | |
| 17 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 18 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 19 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 20 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
| 21 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 22 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 23 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 24 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 25 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 26 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF |
| 27 | THE POSSIBILITY OF SUCH DAMAGE. |
| 28 | |
| 29 | This file is automatically generated. Please do NOT modify !!! |
| 30 | |
| 31 | **/ |
| 32 | |
| 33 | #ifndef __FSPMUPD_H__ |
| 34 | #define __FSPMUPD_H__ |
| 35 | |
| 36 | #include <FspUpd.h> |
| 37 | |
| 38 | #pragma pack(1) |
| 39 | |
| 40 | |
| 41 | /** FSP-M Configuration |
| 42 | **/ |
| 43 | typedef struct { |
| 44 | |
| 45 | /** Offset 0x0040 - Customer Revision |
| 46 | The Customer can set this revision string for their own purpose. |
| 47 | **/ |
| 48 | UINT8 CustomerRevision[32]; |
| 49 | |
| 50 | /** Offset 0x0060 - Bus Ratio |
| 51 | Indicates the ratio of Bus/MMIOL/IO resource to be allocated for each CPU's IIO |
| 52 | **/ |
| 53 | UINT8 BusRatio[8]; |
| 54 | |
| 55 | /** Offset 0x0068 - D2K Credit Config |
| 56 | Set the D2K Credit Config - 1: Min, <b>2: Med(Default)</b>, 3: Max. |
| 57 | 1:Min, 2:Med, 3:Max |
| 58 | **/ |
| 59 | UINT8 D2KCreditConfig; |
| 60 | |
| 61 | /** Offset 0x0069 - Snoop Throttle Config |
| 62 | Set the Snoop Throttle Config - <b>0: DIS(Default)</b>, 1: Min, 2: Med, 3: Max. |
| 63 | 0:DIS, 1:Min, 2:Med, 3:Max |
| 64 | **/ |
| 65 | UINT8 SnoopThrottleConfig; |
| 66 | |
| 67 | /** Offset 0x006A - Legacy VGA Soc |
| 68 | Socket that claims the legacy VGA range |
| 69 | **/ |
| 70 | UINT8 LegacyVgaSoc; |
| 71 | |
| 72 | /** Offset 0x006B - Legacy VGA Stack |
| 73 | Stack that claims the legacy VGA range |
| 74 | **/ |
| 75 | UINT8 LegacyVgaStack; |
| 76 | |
| 77 | /** Offset 0x006C - Pcie P2P Performance Mode |
| 78 | Determine if to enable PCIe P2P Performance Mode - <b>0: Disable(Default)</b>, 1: Enable. |
| 79 | 0:Disable, 1:Enable |
| 80 | **/ |
| 81 | UINT8 P2pRelaxedOrdering; |
| 82 | |
| 83 | /** Offset 0x006D - UPI Debug Print Level |
| 84 | UPI Debug Print Level Bitmask - 0: Disable, 1: Fatal, 2: Warning, 4: Summary, 8: |
| 85 | Detail, <b>0x0F: All(Default)</b>. |
| 86 | 1:Fatal, 2:Warning, 4:Summary, 8:Detail, 0x0F:All |
| 87 | **/ |
| 88 | UINT8 DebugPrintLevel; |
| 89 | |
| 90 | /** Offset 0x006E - NumaEn |
| 91 | NumaEn - <b>1: Enable Numa(Default)</b>, 0: Disable Numa. |
| 92 | 0:Disable, 1:Enable |
| 93 | **/ |
| 94 | UINT8 NumaEn; |
| 95 | |
| 96 | /** Offset 0x006F - SNC |
| 97 | Enable or Disable SNC - 0: Disable, 2: Snc2, 4: Snc4, <b>0x0F: Auto(Default)</b>. |
| 98 | 0: Disable, 2: Snc2, 4: Snc4, 0x0F: Auto |
| 99 | **/ |
| 100 | UINT8 SncEn; |
| 101 | |
| 102 | /** Offset 0x0070 - UMA Clustering |
| 103 | Set UMA Clusters - 0: Disable, 2: Two Clusters, <b>4: Four Clusters(Default)</b>. |
| 104 | 0:Disable, 2:Two Clusters, 4:Four Clusters |
| 105 | **/ |
| 106 | UINT8 UmaClustering; |
| 107 | |
| 108 | /** Offset 0x0071 - IODC Mode |
| 109 | IODC Mode - 0: Disable, <b>1: Auto(Default)</b>, 2: Push, 3: AllocFlow, 4: NonAlloc, |
| 110 | 5: WCILF. |
| 111 | 0:Disable, 1:Auto, 2:Push, 3:AllocFlow, 4:NonAlloc, 5:WCILF |
| 112 | **/ |
| 113 | UINT8 IoDcMode; |
| 114 | |
| 115 | /** Offset 0x0072 - Degrade Precedence |
| 116 | Setup Degrade Precedence - <b>0: Topology(Default)</b>, 1: Feature. |
| 117 | 0:Topology, 1:Feature |
| 118 | **/ |
| 119 | UINT8 DegradePrecedence; |
| 120 | |
| 121 | /** Offset 0x0073 - Degrade 4 Socket Preference |
| 122 | Setup Degrade 4 Socket Preference - <b>0: Fully Connect(Default)</b>, 1: Dual Link Ring. |
| 123 | 0:Fully Connect, 1:Dual Link Ring |
| 124 | **/ |
| 125 | UINT8 Degrade4SPreference; |
| 126 | |
| 127 | /** Offset 0x0074 - Directory Mode |
| 128 | Enable or Disable Directory Mode - 0: Disable, 1: Enable, <b>2: Auto(Default)</b>. |
| 129 | 0:Disable, 1:Enable, 2:Auto |
| 130 | **/ |
| 131 | UINT8 DirectoryModeEn; |
| 132 | |
| 133 | /** Offset 0x0075 - XPT Prefetch Enable |
| 134 | Enable or Disable XPT Prefetch - 0: Disable, 1: Enable, <b>2: Auto(Default)</b>. |
| 135 | 0:Disable, 1:Enable, 2:Auto |
| 136 | **/ |
| 137 | UINT8 XptPrefetchEn; |
| 138 | |
| 139 | /** Offset 0x0076 - KTI Prefetch Enable |
| 140 | Enable or Disable KTI Prefetch - 0: Disable, 1: Enable, <b>2: Auto(Default)</b>. |
| 141 | 0:Disable, 1:Enable, 2:Auto |
| 142 | **/ |
| 143 | UINT8 KtiPrefetchEn; |
| 144 | |
| 145 | /** Offset 0x0077 - XPT Remote Prefetch Enable |
| 146 | Enable or Disable XPT Remote Prefetch Enable - 0: Disable, 1: Enable, <b>2: Auto(Default)</b>. |
| 147 | 0:Disable, 1:Enable, 2:Auto |
| 148 | **/ |
| 149 | UINT8 XptRemotePrefetchEn; |
| 150 | |
| 151 | /** Offset 0x0078 - KTI FPGA |
| 152 | Enable or Disable KTI FPGA |
| 153 | **/ |
| 154 | UINT8 KtiFpgaEnable[8]; |
| 155 | |
| 156 | /** Offset 0x0080 - DDRT QoS Mode |
| 157 | DDRT QoS - <b>0: Mode 0(Default)</b>, 1: Mode 1, 2: Mode 2. |
| 158 | 0:Mode 0, 1:Mode 1, 2:Mode 2 |
| 159 | **/ |
| 160 | UINT8 DdrtQosMode; |
| 161 | |
| 162 | /** Offset 0x0081 - KTI Link Speed Mode |
| 163 | Choose KTI Link Speed Mode - 0: Slow, <b>1: Full(Default)</b>. |
| 164 | 0:Slow, 1:Full |
| 165 | **/ |
| 166 | UINT8 KtiLinkSpeedMode; |
| 167 | |
| 168 | /** Offset 0x0082 - KTI Link Speed |
| 169 | Setup KTI Link Speed - 0: 128GT, 1: 144GT, 2: 160GT, 3: 200GT, <b>0x7F: Max KTI |
| 170 | Link Speed (Default)</b>, 0x8F: Frequency Per Link. |
| 171 | 0:128GT, 1:144GT, 2:160GT, 3:200GT, 0x7F:Max KTI Link Speed, 0x8F:Frequency Per Link |
| 172 | **/ |
| 173 | UINT8 KtiLinkSpeed; |
| 174 | |
| 175 | /** Offset 0x0083 - KTI Link L0p |
| 176 | Enable or Disable KTI Link L0p - 0: Disable, 1: Enable, <b>2: Auto(Default)</b>. |
| 177 | 0:Disable, 1:Enable, 2: Auto |
| 178 | **/ |
| 179 | UINT8 KtiLinkL0pEn; |
| 180 | |
| 181 | /** Offset 0x0084 - KTI Link L1 |
| 182 | Enable or Disable KTI Link L1 - 0: Disable, 1: Enable, <b>2: Auto(Default)</b>. |
| 183 | 0:Disable, 1:Enable, 2: Auto |
| 184 | **/ |
| 185 | UINT8 KtiLinkL1En; |
| 186 | |
| 187 | /** Offset 0x0085 - Kti Link Speed Per Port |
| 188 | Setup KTI Link Speed to be allocated for each port - 0: 128GT, 1: 144GT, 2: 160GT, |
| 189 | 3: 200GT, <b>0x7f: Max KTI Link Speed(Default)</b>. |
| 190 | 0:128GT, 1:144GT, 2:160GT, 3:200GT, 0x7f:Max KTI Link Speed |
| 191 | **/ |
| 192 | UINT8 KtiLinkSpeedPerPort[48]; |
| 193 | |
| 194 | /** Offset 0x00B5 - DfxL0p Enable |
| 195 | Indicates the DfxL0p Enable to be allocated for each port - 0: Disable, <b>1: Enable(Default)</b>. |
| 196 | 0:Disable, 1:Enable |
| 197 | **/ |
| 198 | UINT8 DfxL0pEnable[48]; |
| 199 | |
| 200 | /** Offset 0x00E5 - DfxL1 Enable |
| 201 | Indicates the DfxL1 Enable to be allocated for each port - 0: Disable, <b>1: Enable(Default)</b>. |
| 202 | 0:Disable, 1:Enable |
| 203 | **/ |
| 204 | UINT8 DfxL1Enable[48]; |
| 205 | |
| 206 | /** Offset 0x0115 - KTI Failover |
| 207 | Enable or Disable KTI Failover - 0: Disable, 1: Enable, <b>2: Auto(Default)</b>. |
| 208 | 0:Disable, 1:Enable, 2: Auto |
| 209 | **/ |
| 210 | UINT8 KtiFailoverEn; |
| 211 | |
| 212 | /** Offset 0x0116 - KTI LB Enable |
| 213 | Enable or Disable KTI LB - <b>0:Disable(Default)</b>, 1:Enable. |
| 214 | 0:Disable, 1:Enable |
| 215 | **/ |
| 216 | UINT8 KtiLbEn; |
| 217 | |
| 218 | /** Offset 0x0117 - KTI CRC Mode |
| 219 | Select KTI CRC Mode - <b>0: 16bit(Default)</b>, 1: 32bit, 2: Auto. |
| 220 | 0:16bit, 1:32bit, 2:Auto |
| 221 | **/ |
| 222 | UINT8 KtiCrcMode; |
| 223 | |
| 224 | /** Offset 0x0118 - KTI CPU Socket Hotplug |
| 225 | Enable or Disable KTI CPU Socket Hotplug - <b>0: Disable(Default)</b>, 1: Enable. |
| 226 | 0:Disable, 1:Enable |
| 227 | **/ |
| 228 | UINT8 KtiCpuSktHotPlugEn; |
| 229 | |
| 230 | /** Offset 0x0119 - KTI CPU Socket HotPlug Topology |
| 231 | Select KTI CPU Socket HotPlug Topology - <b>0: 4Socket(Default)</b>, 1: 8Socket. |
| 232 | 0:4Socket, 1:8Socket |
| 233 | **/ |
| 234 | UINT8 KtiCpuSktHotPlugTopology; |
| 235 | |
| 236 | /** Offset 0x011A - KTI SKU Mismatch Check |
| 237 | Enable or Disable KTI SKU Mismatch Check - 0: Disable, <b>1 :Enable(Default)</b>. |
| 238 | 0:Disable, 1:Enable |
| 239 | **/ |
| 240 | UINT8 KtiSkuMismatchCheck; |
| 241 | |
| 242 | /** Offset 0x011B - TOR Threshold - Loctorem threshold Normal |
| 243 | Select TOR Threshold - Loctorem threshold Normal - 0: Disable, <b>1: Auto(Default)</b>, |
| 244 | 2: Low, 3: Medium, 4: High. |
| 245 | 0:Disable, 1:Auto, 2:Low, 3:Medium, 4:High |
| 246 | **/ |
| 247 | UINT8 TorThresLoctoremNorm; |
| 248 | |
| 249 | /** Offset 0x011C - TOR threshold - Loctorem threshold empty |
| 250 | Select TOR threshold - Loctorem threshold empty - 0: Disable, <b>1: Auto(Default)</b>, |
| 251 | 2: Low, 3: Medium, 4:High. |
| 252 | 0:Disable, 1:Auto, 2:Low, 3:Medium, 4:High |
| 253 | **/ |
| 254 | UINT8 TorThresLoctoremEmpty; |
| 255 | |
| 256 | /** Offset 0x011D - TSC Sync in Sockets |
| 257 | Enable or Disable TSC Sync in Sockets - 0: Disable, <b>1: Enable(Default)</b>, 2: Auto. |
| 258 | 0:Disable, 1:Enable, 2:Auto |
| 259 | **/ |
| 260 | UINT8 TscSyncEn; |
| 261 | |
| 262 | /** Offset 0x011E - HA A to S directory optimization |
| 263 | Enable or Disable HA A to S directory optimization - 0: Disable, 1: Enable, <b>2: |
| 264 | Auto(Default)</b>. |
| 265 | 0:Disable, 1:Enable, 2:Auto |
| 266 | **/ |
| 267 | UINT8 StaleAtoSOptEn; |
| 268 | |
| 269 | /** Offset 0x011F - LLC Deadline Allocation |
| 270 | Enable or Disable LLC Deadline Allocation - 0: Disable, <b>1: Enable(Default)</b>, 2: Auto. |
| 271 | 0:Disable, 1:Enable, 2:Auto |
| 272 | **/ |
| 273 | UINT8 LLCDeadLineAlloc; |
| 274 | |
| 275 | /** Offset 0x0120 - MBA BW Calibration Profiles |
| 276 | Choice of MBA BW throttling curve - 0: Linear BW shaping, 1: Biased BW shaping, |
| 277 | 2: Legacy BW shaping, <b>3: Auto(Default)</b>. |
| 278 | 0:Linear BW shaping, 1:Biased BW shaping, 2:Legacy BW shaping, 3:Auto |
| 279 | **/ |
| 280 | UINT8 MbeBWCalChoice; |
| 281 | |
| 282 | /** Offset 0x0121 - Split Lock |
| 283 | Enable or Disable Split Lock - <b>0: Disable(Default)</b>, 1: Enable, 2: Auto. |
| 284 | 0:Disable, 1:Enable, 2:Auto |
| 285 | **/ |
| 286 | UINT8 SplitLock; |
| 287 | |
| 288 | /** Offset 0x0122 - Affinitize M2Iosf to Upi for 2-Socket |
| 289 | Affinitize M2IOSF traffic to proper UPI links to improve 2-Socket P2P perf - 0: |
| 290 | Disable, 1: Enable, <b>2: Auto(Default)</b>. |
| 291 | 0:Disable, 1:Enable, 2:Auto |
| 292 | **/ |
| 293 | UINT8 M2iosfToUpiAffinity; |
| 294 | |
| 295 | /** Offset 0x0123 - MMCFG Base Address |
| 296 | Setup MMCFG Base Address - 0: 1G, 1: 1.5G, 2: 1.75G, 3: 2G, 4: 2.25G, 5: 3G, <b>6: |
| 297 | Auto(Default)</b>. |
| 298 | 0:1G, 1:1.5G, 2:1.75G, 3:2G, 4:2.25G, 5:3G, 6:Auto |
| 299 | **/ |
| 300 | UINT8 mmCfgBase; |
| 301 | |
| 302 | /** Offset 0x0124 - MMCFG Size |
| 303 | Select MMCFG Size - 0: 64M, 1: 128M, 2: 256M, 3: 512M, 4: 1G, 5: 2G, <b>6: Auto(Default)</b>. |
| 304 | 0:64M, 1:128M, 2:256M, 3:512M, 4:1G, 5:2G, 6:Auto |
| 305 | **/ |
| 306 | UINT8 mmCfgSize; |
| 307 | |
| 308 | /** Offset 0x0125 |
| 309 | **/ |
| 310 | UINT8 UnusedUpdSpace0[3]; |
| 311 | |
| 312 | /** Offset 0x0128 - MMIO High Base Address |
| 313 | MMIO High Base Address, a hex number for Bit[51:32] |
| 314 | **/ |
| 315 | UINT32 mmiohBase; |
| 316 | |
| 317 | /** Offset 0x012C - CPU Physical Address Limit |
| 318 | CPU Physical Address Limit - <b>0: Disable(Default)</b>, 1: Enable. |
| 319 | 0:Disable, 1:Enable |
| 320 | **/ |
| 321 | UINT8 CpuPaLimit; |
| 322 | |
| 323 | /** Offset 0x012D |
| 324 | **/ |
| 325 | UINT8 UnusedUpdSpace1; |
| 326 | |
| 327 | /** Offset 0x012E - MMIO High Size |
| 328 | MMIO High Size, Number of 1GB contiguous regions to be assigned for MMIOH space |
| 329 | per CPU. Range 1-1024 |
| 330 | **/ |
| 331 | UINT16 mmiohSize; |
| 332 | |
| 333 | /** Offset 0x0130 - isocEn |
| 334 | Enable or Disable isocEn - <b>0: Disable(Default)</b>, 1: Enable, 2: Auto. |
| 335 | 0:Disable, 1:Enable, 2:Auto |
| 336 | **/ |
| 337 | UINT8 isocEn; |
| 338 | |
| 339 | /** Offset 0x0131 - DCA |
| 340 | Enable or Disable DCA - <b>0: Disable(Default)</b>, 1: Enable. |
| 341 | 0:Disable, 1:Enable |
| 342 | **/ |
| 343 | UINT8 dcaEn; |
| 344 | |
| 345 | /** Offset 0x0132 |
| 346 | **/ |
| 347 | UINT8 UnusedUpdSpace2[2]; |
| 348 | |
| 349 | /** Offset 0x0134 - BoardTypeBitmask |
| 350 | BoardTypeBitmask |
| 351 | **/ |
| 352 | UINT32 BoardTypeBitmask; |
| 353 | |
| 354 | /** Offset 0x0138 - AllLanesPtr |
| 355 | Pointer to array of ALL_LANES_EPARAM_LINK_INFO |
| 356 | **/ |
| 357 | UINT32 AllLanesPtr; |
| 358 | |
| 359 | /** Offset 0x013C - PerLanePtr |
| 360 | Pointer to array of PER_LANE_EPARAM_LINK_INFO |
| 361 | **/ |
| 362 | UINT32 PerLanePtr; |
| 363 | |
| 364 | /** Offset 0x0140 - AllLanesSizeOfTable |
| 365 | Number of elements in AllLanesPtr array. |
| 366 | **/ |
| 367 | UINT32 AllLanesSizeOfTable; |
| 368 | |
| 369 | /** Offset 0x0144 - PerLaneSizeOfTable |
| 370 | Number of elements in PerLanePtr array. |
| 371 | **/ |
| 372 | UINT32 PerLaneSizeOfTable; |
| 373 | |
| 374 | /** Offset 0x0148 - WaitTimeForPSBP |
| 375 | Enable or Disable WaitTimeForPSBP |
| 376 | **/ |
| 377 | UINT32 WaitTimeForPSBP; |
| 378 | |
| 379 | /** Offset 0x014C - WaSerializationEn |
| 380 | Enable or Disable WaSerializationEn - <b>0: Disable(Default)</b>, 1: Enable. |
| 381 | 0:Disable, 1:Enable |
| 382 | **/ |
| 383 | UINT8 WaSerializationEn; |
| 384 | |
| 385 | /** Offset 0x014D - KtiInEnableMktme |
| 386 | Enable or Disable KtiInEnableMktme - <b>0: Disable(Default)</b>, 1: Enable. |
| 387 | 0:Disable, 1:Enable |
| 388 | **/ |
| 389 | UINT8 KtiInEnableMktme; |
| 390 | |
| 391 | /** Offset 0x014E - HIOP STACK DISABLE |
| 392 | Enables/Disables given HIOP STACK. Default is AUTO no stack is disabled. 1 - The |
| 393 | stacks indicated by the bit locations are disabled. 0 - The stacks indicated by |
| 394 | the bit locations are not modified. The stack order is abstracted each bit 0 = |
| 395 | stack 0 ... bit n = stack n. The bit setting for each stack can be overriden by |
| 396 | BIOS based on part-knob compatibility. The array size must be MAX_SOCKET x UINT32. |
| 397 | **/ |
| 398 | UINT8 StackDisableBitMap[32]; |
| 399 | |
| 400 | /** Offset 0x016E - CFRS3mProvision |
| 401 | Enable or Disable Provision S3M CFR - <b>0: Disable(Default)</b>, 1: Enable. |
| 402 | 0:Disable, 1:Enable |
| 403 | **/ |
| 404 | UINT8 CFRS3mProvision; |
| 405 | |
| 406 | /** Offset 0x016F - CFRS3mManualCommit |
| 407 | Enable or Disable Manual Commit S3M FW CFR - <b>0:Disable(Default)</b>, 1:Enable. |
| 408 | 0:Disable, 1:Enable |
| 409 | **/ |
| 410 | UINT8 CFRS3mManualCommit; |
| 411 | |
| 412 | /** Offset 0x0170 - CFRPucodeProvision |
| 413 | Enable or Disable Provision PUcode CFR - <b>0:Disable(Default)</b>, 1:Enable. |
| 414 | 0:Disable, 1:Enable |
| 415 | **/ |
| 416 | UINT8 CFRPucodeProvision; |
| 417 | |
| 418 | /** Offset 0x0171 - CFRPucodeManualCommit |
| 419 | Enable or Disable Manual Commit PUcode CFR - <b>0:Disable(Default)</b>, 1:Enable. |
| 420 | 0:Disable, 1:Enable |
| 421 | **/ |
| 422 | UINT8 CFRPucodeManualCommit; |
| 423 | |
| 424 | /** Offset 0x0172 |
| 425 | **/ |
| 426 | UINT8 UnusedUpdSpace3[2]; |
| 427 | |
| 428 | /** Offset 0x0174 - CFRImagePtr |
| 429 | Pointer to array of CFR Image |
| 430 | **/ |
| 431 | UINT32 CFRImagePtr; |
| 432 | |
| 433 | /** Offset 0x0178 - Processor VmxEnable Function |
| 434 | Enable(Default) or Disable Processor VmxEnable Function - 0: Disable, <b>1: Enable(Default)</b>. |
| 435 | 0:Disable, 1:Enable |
| 436 | **/ |
| 437 | UINT8 VmxEnable; |
| 438 | |
| 439 | /** Offset 0x0179 - Processor X2apic Function |
| 440 | Enable(Default) or Disable Processor X2apic Function - 0: Disable, <b>1: Enable(Default)</b>. |
| 441 | 0:Disable, 1:Enable |
| 442 | **/ |
| 443 | UINT8 X2apic; |
| 444 | |
| 445 | /** Offset 0x017A - Processor HyperThreading Function |
| 446 | Enable(Default) or Disable Processor HyperThreading Function - 1: Disable, <b>0: |
| 447 | Enable(Default)</b>. |
| 448 | 1:Disable, 0:Enable |
| 449 | **/ |
| 450 | UINT8 ProcessorHyperThreadingDisable; |
| 451 | |
| 452 | /** Offset 0x017B - Processor Dynamic Intel Speed Select (ISS) Function |
| 453 | Enable or Disable(Default) Processor Dynamic Intel Speed Select (ISS) Function - |
| 454 | <b>0: Disable(Default)</b>, 1: Enable. |
| 455 | 0:Disable, 1:Enable |
| 456 | **/ |
| 457 | UINT8 ProcessorDynamicIssEnable; |
| 458 | |
| 459 | /** Offset 0x017C - Enables Intel(R) TXT |
| 460 | Enable or Disable(Default) Enables Intel(R) TXT - <b>0: Disable(Default)</b>, 1: Enable. |
| 461 | 0:Disable, 1:Enable |
| 462 | **/ |
| 463 | UINT8 ProcessorLtsxEnable; |
| 464 | |
| 465 | /** Offset 0x017D - DDR frequency limit |
| 466 | Select DDR frequency limit, <b>0x00: Auto(Default)</b>, 0x13:DDR_3200, 0x16:DDR_3600, |
| 467 | 0x19:DDR_4000, 0x1C:DDR_4400, 0x1D:DDR_4800, 0x1E:DDR_5200, 0x1F:DDR_5600 |
| 468 | **/ |
| 469 | UINT8 DdrFreqLimit; |
| 470 | |
| 471 | /** Offset 0x017E - Memory Serial Debug Message Level |
| 472 | Select Memory Serial Debug Message Level - 0: Disable, 1: Minimum, 2: Normal, <b>3: |
| 473 | Maximum(Default)</b>, 4: Auto. |
| 474 | 0:Disable, 1:Minimum, 2:Normal, 3:Maximum, 4:Auto |
| 475 | **/ |
| 476 | UINT8 serialDebugMsgLvl; |
| 477 | |
| 478 | /** Offset 0x017F - IIO ConfigIOU0 |
| 479 | ConfigIOU[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, |
| 480 | 0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b> |
| 481 | **/ |
| 482 | UINT8 IioConfigIOU0[8]; |
| 483 | |
| 484 | /** Offset 0x0187 - IIO ConfigIOU1 |
| 485 | ConfigIOU[MAX_SOCKET][1]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, |
| 486 | 0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b> |
| 487 | **/ |
| 488 | UINT8 IioConfigIOU1[8]; |
| 489 | |
| 490 | /** Offset 0x018F - IIO ConfigIOU2 |
| 491 | ConfigIOU[MAX_SOCKET][2]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, |
| 492 | 0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b> |
| 493 | **/ |
| 494 | UINT8 IioConfigIOU2[8]; |
| 495 | |
| 496 | /** Offset 0x0197 - IIO ConfigIOU3 |
| 497 | ConfigIOU[MAX_SOCKET][3]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, |
| 498 | 0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b> |
| 499 | **/ |
| 500 | UINT8 IioConfigIOU3[8]; |
| 501 | |
| 502 | /** Offset 0x019F - IIO ConfigIOU4 |
| 503 | ConfigIOU[MAX_SOCKET][4]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, |
| 504 | 0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b> |
| 505 | **/ |
| 506 | UINT8 IioConfigIOU4[8]; |
| 507 | |
| 508 | /** Offset 0x01A7 - IIO ConfigIOU5 |
| 509 | ConfigIOU[MAX_SOCKET][5]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, |
| 510 | 0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b> |
| 511 | **/ |
| 512 | UINT8 IioConfigIOU5[8]; |
| 513 | |
| 514 | /** Offset 0x01AF - IIO ConfigIOU6 |
| 515 | ConfigIOU[MAX_SOCKET][6]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, |
| 516 | 0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b> |
| 517 | **/ |
| 518 | UINT8 IioConfigIOU6[8]; |
| 519 | |
| 520 | /** Offset 0x01B7 |
| 521 | **/ |
| 522 | UINT8 UnusedUpdSpace4; |
| 523 | |
| 524 | /** Offset 0x01B8 - IIO PCIE Config Table Ptr |
| 525 | Pointer to array of UPD_IIO_PCIE_PORT_CONFIG |
| 526 | **/ |
| 527 | UINT32 IioPcieConfigTablePtr; |
| 528 | |
| 529 | /** Offset 0x01BC - IIO PCIE Config Table Number |
| 530 | Number of elements in IioPcieConfigTablePtr array, socket number as unit. |
| 531 | **/ |
| 532 | UINT32 IioPcieConfigTableNumber; |
| 533 | |
| 534 | /** Offset 0x01C0 - IIO DeEmphasis Array Ptr |
| 535 | Pointer to array of DeEmphasis |
| 536 | **/ |
| 537 | UINT32 DeEmphasisPtr; |
| 538 | |
| 539 | /** Offset 0x01C4 - IIO DeEmphasis Array Number |
| 540 | Number of elements in DeEmphasis array. |
| 541 | **/ |
| 542 | UINT32 DeEmphasisNumber; |
| 543 | |
| 544 | /** Offset 0x01C8 - IIO PCIe Common Clock Array Ptr |
| 545 | Pointer to array of PCIe Common Clock |
| 546 | **/ |
| 547 | UINT32 PcieCommonClockPtr; |
| 548 | |
| 549 | /** Offset 0x01CC - IIO PCIe Common Clock Array Number |
| 550 | Number of elements in PCIe Common Clock array. |
| 551 | **/ |
| 552 | UINT32 PcieCommonClockNumber; |
| 553 | |
| 554 | /** Offset 0x01D0 - VT-d Support |
| 555 | Enable or Disable VT-d Support - 0: Disable, <b>1: Enable(Default)</b>. |
| 556 | 0:Disable, 1:Enable |
| 557 | **/ |
| 558 | UINT8 VtdSupport; |
| 559 | |
| 560 | /** Offset 0x01D1 - PCIe ACSCTL |
| 561 | Enable/Disable overwrite of PCI Access Control Services Control register in PCI |
| 562 | root ports - 0: Disable, <b>1: Enable(Default)</b>. |
| 563 | 0:Disable, 1:Enable |
| 564 | **/ |
| 565 | UINT8 VtdPciAcsCtlWaEn; |
| 566 | |
| 567 | /** Offset 0x01D2 |
| 568 | **/ |
| 569 | UINT8 UnusedUpdSpace5[2]; |
| 570 | |
| 571 | /** Offset 0x01D4 - IIO PCIe Port Hide Array Ptr |
| 572 | Pointer to array of Hide or visible for IIO Pcie Port. |
| 573 | **/ |
| 574 | UINT32 PEXPHIDEPtr; |
| 575 | |
| 576 | /** Offset 0x01D8 - IIO PCIe Port Hide Array Number |
| 577 | Number of elements in IIO PCIe Port Hide Array. |
| 578 | **/ |
| 579 | UINT32 PEXPHIDENumber; |
| 580 | |
| 581 | /** Offset 0x01DC - PcieHotPlugEnable |
| 582 | Enable or disable Pcie hot plug enable feature - <b>0: Disable(Default)</b>, 1: Enable. |
| 583 | 0:Disable, 1:Enable |
| 584 | **/ |
| 585 | UINT8 PcieHotPlugEnable; |
| 586 | |
| 587 | /** Offset 0x01DD |
| 588 | **/ |
| 589 | UINT8 UnusedUpdSpace6; |
| 590 | |
| 591 | /** Offset 0x01DE - DelayAfterPCIeLinkTraining |
| 592 | Custom delay after PCI-E link training on IIO ports |
| 593 | **/ |
| 594 | UINT16 DelayAfterPCIeLinkTraining; |
| 595 | |
| 596 | /** Offset 0x01E0 - IIO PCI bus resource Ptr |
| 597 | Pointer to array of socket PCI bus resource. |
| 598 | **/ |
| 599 | UINT32 PciBusResConfigPtr; |
| 600 | |
| 601 | /** Offset 0x01E4 - IIO PCI IO/MMIO base and limits resource Ptr |
| 602 | Pointer to array of socket PCI IO/MMIO resource. |
| 603 | **/ |
| 604 | UINT32 PciBaseLimitsResConfigPtr; |
| 605 | |
| 606 | /** Offset 0x01E8 - PCH PCIE PLL Ssc |
| 607 | Pointer to array of socket PCI IO/MMIO resource. |
| 608 | **/ |
| 609 | UINT8 PchPciePllSsc; |
| 610 | |
| 611 | /** Offset 0x01E9 - MeUmaEnable |
| 612 | Enable or disable ME UMA feature - <b>0: Disable(Default)</b>, 1: Enable. |
| 613 | 0:Disable, 1:Enable |
| 614 | **/ |
| 615 | UINT8 MeUmaEnable; |
| 616 | |
| 617 | /** Offset 0x01EA - SerialIoUartDebugEnable |
| 618 | Enable or Disable SerialIo Uart debug library in FSP - 0: Disable, <b>1: Enable(Default)</b>. |
| 619 | 0:Disable, 1:Enable |
| 620 | **/ |
| 621 | UINT8 SerialIoUartDebugEnable; |
| 622 | |
| 623 | /** Offset 0x01EB |
| 624 | **/ |
| 625 | UINT8 UnusedUpdSpace7; |
| 626 | |
| 627 | /** Offset 0x01EC - ISA Serial Base selection |
| 628 | Select ISA Serial Base address could be initialized by boot loader - 0x2F8: 0x2F8, |
| 629 | <b>0x3F8: 0x3F8(Default)</b>. |
| 630 | 0x2F8:0x2F8, 0x3F8:0x3F8 |
| 631 | **/ |
| 632 | UINT16 SerialIoUartDebugIoBase; |
| 633 | |
| 634 | /** Offset 0x01EE - MemRefreshWaterMark |
| 635 | Enable or Disable MemRefreshWaterMark in FSP - <b>0: Auto(Default)</b>, 1: Enable, |
| 636 | 2: Disable. |
| 637 | 0:Auto, 1:Enable, 2:Disable |
| 638 | **/ |
| 639 | UINT8 PanicWm; |
| 640 | |
| 641 | /** Offset 0x01EF - promoteMrcWarnings |
| 642 | Enable or Disable MRC promote warning in FSP - 0: Disable, <b>1: Enable(Default)</b>. |
| 643 | 0:Disable, 1:Enable |
| 644 | **/ |
| 645 | UINT8 promoteMrcWarnings; |
| 646 | |
| 647 | /** Offset 0x01F0 - promoteWarnings |
| 648 | <b>Enable(Default)</b> or Disable Promote warning in FSP - 0: Disable, <b>1: Enable(Default)</b>. |
| 649 | 0:Disable, 1:Enable |
| 650 | **/ |
| 651 | UINT8 promoteWarnings; |
| 652 | |
| 653 | /** Offset 0x01F1 - serialDebugMsgLvlTrainResults |
| 654 | Enable or Disable Promote warning in FSP - <b>0:Disable(Default)</b>, 8:Enable. |
| 655 | 0:Disable, 8:Enable |
| 656 | **/ |
| 657 | UINT8 serialDebugMsgLvlTrainResults; |
| 658 | |
| 659 | /** Offset 0x01F2 - MemTest |
| 660 | <b>Enable(Default)</b> or Disable memory test during normal boot in FSP - 0: Disable, |
| 661 | <b>1: Enable(Default)</b>. |
| 662 | 0:Disable, 1:Enable |
| 663 | **/ |
| 664 | UINT8 HwMemTest; |
| 665 | |
| 666 | /** Offset 0x01F3 |
| 667 | **/ |
| 668 | UINT8 UnusedUpdSpace8; |
| 669 | |
| 670 | /** Offset 0x01F4 - MemTest Loops |
| 671 | Number of memory test loops during normal boot, set to 0 to run memtest infinitely |
| 672 | in FSP - <b> 1 (Default)</b>. |
| 673 | minimum = 0, maximum = 65535 |
| 674 | **/ |
| 675 | UINT16 MemTestLoops; |
| 676 | |
| 677 | /** Offset 0x01F6 |
| 678 | **/ |
| 679 | UINT8 UnusedUpdSpace9[2]; |
| 680 | |
| 681 | /** Offset 0x01F8 - Adv MemTest Options |
| 682 | This option is a bit mask[19:0]: All 0 = disabled: bit-0=XMATS8, bit-1=XMATS16, |
| 683 | bit-2=Reserved, bit-3=Reserved, bit-4=WCMATS8, bit-5=WCMCH8, bit-6=Reserved, bit-7=MARCHCM64, |
| 684 | bit-8=Reserved, bit-9=Reserved, bit-10=Reserved, bit-11=TWR, bit-12=DATARET, bit-13=MATS8TC1, |
| 685 | bit-14=MATS8TC2, bit-15=MATS8TC3, bit-16=SK-HYNIX, bit-17=SAMSUNG, bit-18=MICRON-RMW, |
| 686 | bit-19=SCRAM_X2 in FSP. |
| 687 | **/ |
| 688 | UINT32 AdvMemTestOptions; |
| 689 | |
| 690 | /** Offset 0x01FC - SmartTestKey |
| 691 | Number of SmartTest Key |
| 692 | **/ |
| 693 | UINT32 SmartTestKey; |
| 694 | |
| 695 | /** Offset 0x0200 - Adv MemTest Pause |
| 696 | Specify a pause delay between 0 to 256000 in units of usec. This is a time period |
| 697 | where refresh is disabled between write and read sequences in FSP. |
| 698 | **/ |
| 699 | UINT32 AdvMemTestCondPause; |
| 700 | |
| 701 | /** Offset 0x0204 - Adv MemTest tREFI |
| 702 | Specify tREFI (refresh rate) timing between 1850 to 7800 in nsec. |
| 703 | **/ |
| 704 | UINT16 AdvMemTestCondTrefi; |
| 705 | |
| 706 | /** Offset 0x0206 - Adv MemTest tWR |
| 707 | Specify tWR timing between 48 to 96 in units of tCK in FSP. |
| 708 | **/ |
| 709 | UINT8 AdvMemTestCondTwr; |
| 710 | |
| 711 | /** Offset 0x0207 |
| 712 | **/ |
| 713 | UINT8 UnusedUpdSpace10; |
| 714 | |
| 715 | /** Offset 0x0208 - Adv MemTest PMIC VDD Level |
| 716 | Specify PMIC VDD level in units of mV in FSP. |
| 717 | **/ |
| 718 | UINT16 AdvMemTestCondPmicVdd; |
| 719 | |
| 720 | /** Offset 0x020A - Adv MemTest Conditions |
| 721 | Auto = set test conditions based on test type; Manual = specify global test conditions; |
| 722 | Disable = Do not apply test conditions in FSP - 0: Disable, <b>1: Auto(Default)</b>, |
| 723 | 2: Manual. |
| 724 | 0:Disable, 1:Auto, 2:Manual |
| 725 | **/ |
| 726 | UINT8 AdvMemTestCondition; |
| 727 | |
| 728 | /** Offset 0x020B - Adv MemTest Reset Failure Tracking List |
| 729 | Enable/disable Reset of the Row Failure Tracking List after each Adv MemTest option. |
| 730 | Useful for testing performance of multiple options in FSP - <b>0: Disable(Default)</b>, |
| 731 | 1: Enable. |
| 732 | 0:Disable, 1:Enable |
| 733 | **/ |
| 734 | UINT8 AdvMemTestResetList; |
| 735 | |
| 736 | /** Offset 0x020C - MemTest On Cold Fast Boot |
| 737 | Enable - Enables memory test during cold fast boot. Disable - Disables this feature. |
| 738 | Auto - Sets it to the MRC default setting; current default is Disable in FSP - |
| 739 | <b>0:Disable(Default)</b>, 1:Enable. |
| 740 | 0:Disable, 1:Enable |
| 741 | **/ |
| 742 | UINT8 MemTestOnColdFastBoot; |
| 743 | |
| 744 | /** Offset 0x020D - Attempt Fast Boot |
| 745 | Enable - Portions of memory reference code will be skipped when possible to increase |
| 746 | boot speed on warm boots. Disable - Disables this feature. Auto - Sets it to the |
| 747 | MRC default setting - 0:Disable, <b>1:Enable(Default)</b>. |
| 748 | 0:Disable, 1:Enable |
| 749 | **/ |
| 750 | UINT8 AttemptFastBoot; |
| 751 | |
| 752 | /** Offset 0x020E - MemTest On Cold Fast Boot |
| 753 | Enable - Enables memory test during cold fast boot. Disable - Disables this feature. |
| 754 | Auto - Sets it to the MRC default setting - 0:Disable, <b>1:Enable(Default)</b>. |
| 755 | 0:Disable, 1:Enable |
| 756 | **/ |
| 757 | UINT8 AttemptFastBootCold; |
| 758 | |
| 759 | /** Offset 0x020F - Multithreaded Memory Training |
| 760 | Selects the number of processor sockets to train in parallel. - <b>0: All sockets |
| 761 | operate in parallel(Default)</b>. 1: At any time only one socket is executing. |
| 762 | 2: At any time only two socket are executing. 4: At any time only four socket are |
| 763 | executing in FSP. |
| 764 | 0:All Processor Sockets, 1:One Socket at a Time (No Multithreading), 2:Two Sockets |
| 765 | at a Time, 4:Four Sockets at a Time |
| 766 | **/ |
| 767 | UINT8 AllowedSocketsInParallel; |
| 768 | |
| 769 | /** Offset 0x0210 - Auto-Reset on mem Training Error |
| 770 | Enable/Disable Auto-Reset on mem Training Error in FSP - <b>0:Disable(Default)</b>, |
| 771 | 1:Enable. |
| 772 | 0:Disable, 1:Enable |
| 773 | **/ |
| 774 | UINT8 AutoResetOnMemErr; |
| 775 | |
| 776 | /** Offset 0x0211 - Rank Margin Tool |
| 777 | Enable/Disable the Rank Margin Tool in FSP - <b>0:Disable(Default)</b>, 1:Enable. |
| 778 | 0:Disable, 1:Enable |
| 779 | **/ |
| 780 | UINT8 EnableRMT; |
| 781 | |
| 782 | /** Offset 0x0212 - RMT on Fast Cold Boot |
| 783 | Enable/Disable the Rank Margin Tool on a Fast Cold Boot in FSP - <b>0:Disable(Default)</b>, |
| 784 | 1:Enable. |
| 785 | 0:Disable, 1:Enable |
| 786 | **/ |
| 787 | UINT8 EnableRMTonFCB; |
| 788 | |
| 789 | /** Offset 0x0213 - Execute Jedecinit before RMT |
| 790 | Execute Jedecinit before Rank Margin Tool in FSP - <b>0:Disable(Default)</b>, 1:Enable. |
| 791 | 0:Disable, 1:Enable |
| 792 | **/ |
| 793 | UINT8 JedecInitBeforeRMT; |
| 794 | |
| 795 | /** Offset 0x0214 - Backside Margining |
| 796 | Enable/Disable margin test on the register or buffer backside in FSP - <b>0:Disable(Default)</b>, |
| 797 | 1:Enable. |
| 798 | 0:Disable, 1:Enable |
| 799 | **/ |
| 800 | UINT8 RMTBacksideMargining; |
| 801 | |
| 802 | /** Offset 0x0215 - CmdAll |
| 803 | Step size of CmdAll. Auto: 1. Supported values: 1,2,4,8 in FSP - <b>1:Auto(Default)</b>, |
| 804 | 2:2, 4:4, 8:8. |
| 805 | 1:Auto, 2:2, 4:4, 8:8 |
| 806 | **/ |
| 807 | UINT8 RMTCmdAll; |
| 808 | |
| 809 | /** Offset 0x0216 - RMT Debug Messages |
| 810 | Enable/Disable the RMT debug messages in FSP - <b>2:Disable(Default)</b>, 5:Enable. |
| 811 | 2:Disable, 5:Enable |
| 812 | **/ |
| 813 | UINT8 RMTDebugMessages; |
| 814 | |
| 815 | /** Offset 0x0217 - RMT Display Tables |
| 816 | Enable/Disable displaying results as tables in FSP - 0:Disable, <b>1:Enable(Default)</b>. |
| 817 | 0:Disable, 1:Enable |
| 818 | **/ |
| 819 | UINT8 RMTDisplayTables; |
| 820 | |
| 821 | /** Offset 0x0218 - RMT Loop Count |
| 822 | Exponential loop count for single rank test in FSP. |
| 823 | **/ |
| 824 | UINT8 RMTLoopCount; |
| 825 | |
| 826 | /** Offset 0x0219 |
| 827 | **/ |
| 828 | UINT8 UnusedUpdSpace11[3]; |
| 829 | |
| 830 | /** Offset 0x021C - Test Signal Bit Mask For RMT |
| 831 | Test signal bit mask for RMT in FSP. |
| 832 | **/ |
| 833 | UINT32 TestSignalBitMaskRMT; |
| 834 | |
| 835 | /** Offset 0x0220 - RMT Per Bit Margining |
| 836 | Enable/Disable Per Bit Margining in FSP - 0:Disable, <b>1:Enable(Default)</b>. |
| 837 | 0:Disable, 1:Enable |
| 838 | **/ |
| 839 | UINT8 RMTPerBitMargining; |
| 840 | |
| 841 | /** Offset 0x0221 - RMT Per CA Lane Margining |
| 842 | Enable/Disable Per CA Lane Margining in FSP - 0:Disable, <b>1:Enable(Default)</b>. |
| 843 | 0:Disable, 1:Enable |
| 844 | **/ |
| 845 | UINT8 RMTPerCaLaneMargining; |
| 846 | |
| 847 | /** Offset 0x0222 - RMT Display Plots |
| 848 | Enable/Disable the display of per-bit results as plots in FSP - 0:Disable, <b>1:Enable(Default)</b>. |
| 849 | 0:Disable, 1:Enable |
| 850 | **/ |
| 851 | UINT8 RMTPerDisplayPlots; |
| 852 | |
| 853 | /** Offset 0x0223 - RMT RxDqs |
| 854 | Step size of RxDqs. Auto: 1. Supported values: 1,2,4,8 in FSP - <b>1:Auto,(Default)</b> |
| 855 | 2:2, 4:4, 8:8. |
| 856 | 1:Auto, 2:2, 4:4, 8:8 |
| 857 | **/ |
| 858 | UINT8 RMTRxDqs; |
| 859 | |
| 860 | /** Offset 0x0224 - RMT RxVref |
| 861 | Step size of RxVref. Auto: 1. Supported values: 1,2,4,8 in FSP - <b>1:Auto,(Default)</b> |
| 862 | 2:2, 4:4, 8:8. |
| 863 | 1:Auto, 2:2, 4:4, 8:8 |
| 864 | **/ |
| 865 | UINT8 RMTRxVref; |
| 866 | |
| 867 | /** Offset 0x0225 - RMT Scrambler |
| 868 | Enable or Disable scrambler during RMT test in FSP - 0:Disable, <b>1:Enable(Default)</b>. |
| 869 | 0:Disable, 1:Enable |
| 870 | **/ |
| 871 | UINT8 RMTScrambler; |
| 872 | |
| 873 | /** Offset 0x0226 - RMT Step Size Override |
| 874 | Enable or Disable overriding the default step sizes in FSP - <b>0:Disable(Default)</b>, |
| 875 | 1:Enable. |
| 876 | 0:Disable, 1:Enable |
| 877 | **/ |
| 878 | UINT8 RMTStepSizeOverride; |
| 879 | |
| 880 | /** Offset 0x0227 - RMT TxDq |
| 881 | Step size of TxDq. Auto: 1. Supported values: 1,2,4,8 in FSP - <b>1:Auto(Default)</b>, |
| 882 | 2:2, 4:4, 8:8. |
| 883 | 1:Auto, 2:2, 4:4, 8:8 |
| 884 | **/ |
| 885 | UINT8 RMTTxDq; |
| 886 | |
| 887 | /** Offset 0x0228 - RMT TxVref |
| 888 | Step size of TxVref. Auto: 1. Supported values: 1,2,4,8 in FSP - <b>1:Auto(Default)</b>, |
| 889 | 2:2, 4:4, 8:8. |
| 890 | 1:Auto, 2:2, 4:4, 8:8 |
| 891 | **/ |
| 892 | UINT8 RMTTxVref; |
| 893 | |
| 894 | /** Offset 0x0229 - DDR5 ECS |
| 895 | Enable/Disable DDR5 Error Check and Scrub (ECS) in FSP - 0:Disable, <b>1:Enable(Default)</b>. |
| 896 | 0:Disable, 1:Enable |
| 897 | **/ |
| 898 | UINT8 ErrorCheckScrub; |
| 899 | |
| 900 | /** Offset 0x022A - Enforce Memory POR |
| 901 | 0:Enforce POR - Enforces Plan Of Record restrictions for DDR5 frequency and voltage |
| 902 | programming. <b>2:Disable - Disables this feature and user is able to run at higher |
| 903 | frequencies, specified in the DDR Frequency Limit field (limited by processor support)(Default)</b>. |
| 904 | 0:Enforce POR, 2:Disabled |
| 905 | **/ |
| 906 | UINT8 EnforceDdrMemoryFreqPor; |
| 907 | |
| 908 | /** Offset 0x022B - Enforce Population POR |
| 909 | Enable Memory Population POR Enforcement. Selecting Enforce Validated Populations |
| 910 | will only allow populations that have been validated in FSP - <b>0:Disable(Default)</b>, |
| 911 | 1:Enable. |
| 912 | 0:Disable, 1:Enable |
| 913 | **/ |
| 914 | UINT8 EnforcePopulationPor; |
| 915 | |
| 916 | /** Offset 0x022C - DDR PPR Type |
| 917 | Selects DDR Post Package Repair Type - 2: Hard PPR, <b>1: Soft PPR (Default)</b>, |
| 918 | 0: Disabled. |
| 919 | 0:Disabled, 2:Hard PPR, 1:Soft PPR |
| 920 | **/ |
| 921 | UINT8 pprType; |
| 922 | |
| 923 | /** Offset 0x022D - Force PPR On All Dram for UCE |
| 924 | Force PPR on all dram for UCE in FSP - <b>0:Disable(Default)</b>, 1:Enable. |
| 925 | 0:Disabled, 1:Enabled |
| 926 | **/ |
| 927 | UINT8 ForcePprOnAllDramUce; |
| 928 | |
| 929 | /** Offset 0x022E |
| 930 | **/ |
| 931 | UINT8 UnusedUpdSpace12[2]; |
| 932 | |
| 933 | /** Offset 0x0230 - pprAddrVariablePtr |
| 934 | Pointer to array of PPR_ADDR_VARIABLE |
| 935 | **/ |
| 936 | UINT32 PprAddrVariablePtr; |
| 937 | |
| 938 | /** Offset 0x0234 - Allow Memory Test Correctable Error |
| 939 | Enable - Logs error and allows correctable errors during memory test(DIMM Rank not |
| 940 | removed). Disable - Logs error and removes DIMM Rank. Auto - Sets it to the MRC |
| 941 | default setting; current default is Enable in FSP - 0:Disable, <b>1:Enable(Default)</b>. |
| 942 | 0:Disable, 1:Enable |
| 943 | **/ |
| 944 | UINT8 allowCorrectableMemTestError; |
| 945 | |
| 946 | /** Offset 0x0235 - Memory I/O Health Check |
| 947 | Memory I/O Health Check - 0: Auto, 1: Manual, <b>2: Disable (Default)</b>. Select |
| 948 | option Auto for default values. Manual for new values. Disable for disabling feature |
| 949 | in FSP - 0:Auto, 1:Manual, <b>2:Disable(Default)</b>. |
| 950 | 0:Auto, 1:Manual, 2:Disable |
| 951 | **/ |
| 952 | UINT8 MemIOHealthCheck; |
| 953 | |
| 954 | /** Offset 0x0236 - RxDqsDelay Left Edge |
| 955 | Offset for RxDqsDelay Left Edge in FSP. |
| 956 | **/ |
| 957 | UINT8 CriticalRxDqsDelayLeftEdge; |
| 958 | |
| 959 | /** Offset 0x0237 - RxDqsDelay Right Edge |
| 960 | Offset for RxDqsDelay Right in FSP. |
| 961 | **/ |
| 962 | UINT8 CriticalRxDqsDelayRightEdge; |
| 963 | |
| 964 | /** Offset 0x0238 - RxVref Left Edge |
| 965 | Offset for RxVref Left Edge in FSP. |
| 966 | **/ |
| 967 | UINT8 CriticalRxVrefLeftEdge; |
| 968 | |
| 969 | /** Offset 0x0239 - RxVref Right Edge |
| 970 | Offset for RxVref Right Edge in FSP. |
| 971 | **/ |
| 972 | UINT8 CriticalRxVrefRightEdge; |
| 973 | |
| 974 | /** Offset 0x023A - TxDqDelay Left Edge |
| 975 | Offset for TxDqDelay Left Edge in FSP. |
| 976 | **/ |
| 977 | UINT8 CriticalTxDqDelayLeftEdge; |
| 978 | |
| 979 | /** Offset 0x023B - TxDqDelay Right Edge |
| 980 | Offset for TxDqDelay Right Edge in FSP. |
| 981 | **/ |
| 982 | UINT8 CriticalTxDqDelayRightEdge; |
| 983 | |
| 984 | /** Offset 0x023C - TxVref Left Edge |
| 985 | Offset for TxDqDelay Left Edge in FSP. |
| 986 | **/ |
| 987 | UINT8 CriticalTxVrefLeftEdge; |
| 988 | |
| 989 | /** Offset 0x023D - TxVref Right Edge |
| 990 | Offset for TxDqDelay Right Edge in FSP. |
| 991 | **/ |
| 992 | UINT8 CriticalTxVrefRightEdge; |
| 993 | |
| 994 | /** Offset 0x023E - Reboot On Critical Failure |
| 995 | Reboot System on Critical failure to do Memory Training in FSP - 0:Disable, <b>1:Enable(Default)</b>. |
| 996 | 0:Disable, 1:Enable |
| 997 | **/ |
| 998 | UINT8 ResetOnCriticalError; |
| 999 | |
| 1000 | /** Offset 0x023F - Number of Times to Reboot and Retrain |
| 1001 | Number of times to Reboot System on Critical failure to do Memory Training in FSP. |
| 1002 | **/ |
| 1003 | UINT8 CriticalRetries; |
| 1004 | |
| 1005 | /** Offset 0x0240 - Memory I/O Health Check Loop Count |
| 1006 | CPGC Test Loop Count for Memory IO Health Test |
| 1007 | **/ |
| 1008 | UINT8 MemIOHealthLoopCount; |
| 1009 | |
| 1010 | /** Offset 0x0241 - Telemetry RxDqsDelay Left Edge |
| 1011 | Offset for Telemetry RxDqsDelay Left Edge in FSP. |
| 1012 | **/ |
| 1013 | UINT8 TelemetryRxDqsDelayLeftEdge; |
| 1014 | |
| 1015 | /** Offset 0x0242 - Telemetry RxDqsDelay Right Edge |
| 1016 | Offset for Telemetry RxDqsDelay Right Edge in FSP. |
| 1017 | **/ |
| 1018 | UINT8 TelemetryRxDqsDelayRightEdge; |
| 1019 | |
| 1020 | /** Offset 0x0243 - Telemetry RxVref Left Edge |
| 1021 | Offset for Telemetry RxDqsDelay Left Edge in FSP. |
| 1022 | **/ |
| 1023 | UINT8 TelemetryRxVrefLeftEdge; |
| 1024 | |
| 1025 | /** Offset 0x0244 - Telemetry RxVref Right Edge |
| 1026 | Offset for Telemetry RxDqsDelay Right Edge in FSP. |
| 1027 | **/ |
| 1028 | UINT8 TelemetryRxVrefRightEdge; |
| 1029 | |
| 1030 | /** Offset 0x0245 - Telemetry TxDqDelay Left Edge |
| 1031 | Offset for Telemetry TxDqDelay Left Edge in FSP. |
| 1032 | **/ |
| 1033 | UINT8 TelemetryTxDqDelayLeftEdge; |
| 1034 | |
| 1035 | /** Offset 0x0246 - Telemetry TxDqDelay Right Edge |
| 1036 | Offset for Telemetry TxDqDelay Right Edge in FSP. |
| 1037 | **/ |
| 1038 | UINT8 TelemetryTxDqDelayRightEdge; |
| 1039 | |
| 1040 | /** Offset 0x0247 - Volatile Memory Mode |
| 1041 | Selects 1LM or 2LM mode for volatile memory. For 2LM memory mode, system will try |
| 1042 | to configure 2LM but if system is unable to configure 2LM, volatile memory mode |
| 1043 | will fall back to 1LM in FSP - <b>0: 1LM(Default)</b>, 1: 2LM, 2: MIX 1LM2LM. |
| 1044 | 0: 1LM, 1: 2LM, 2: MIX 1LM2LM |
| 1045 | **/ |
| 1046 | UINT8 volMemMode; |
| 1047 | |
| 1048 | /** Offset 0x0248 - Dynamic ECC Mode Selection |
| 1049 | Enable/Disable Dynamic ECC Mode Selection in FSP - 0:Disable, <b>1:Enable(Default)</b>, |
| 1050 | 2:Enable + Allow 128b ECC. |
| 1051 | 0:Disable, 1:Enable, 2:Enable + Allow 128b ECC |
| 1052 | **/ |
| 1053 | UINT8 DynamicEccModeSel; |
| 1054 | |
| 1055 | /** Offset 0x0249 - Memory Patrol Scrub |
| 1056 | Memory Patrol Scrub - 0:Disable, 1:Enable during FspMemoryInit(), <b>2:Enable during |
| 1057 | NotifyPhase(EnumInitPhaseReadyToBoot) (Default)</b>. |
| 1058 | 0:Disable, 1:Enable during FspMemoryInit(), 2:Enable during EnumInitPhaseReadyToBoot |
| 1059 | **/ |
| 1060 | UINT8 PatrolScrub; |
| 1061 | |
| 1062 | /** Offset 0x024A - Memory Patrol Scrub |
| 1063 | Memory Patrol Scrub - <b>0:Disable (Default)</b>, 1:Enable at ReadyToBootFsp(). |
| 1064 | 0:Disable, 1:Enable Enable at ReadyToBootFsp() |
| 1065 | **/ |
| 1066 | UINT8 PatrolScrubNotify; |
| 1067 | |
| 1068 | /** Offset 0x024B - Patrol Scrub Interval |
| 1069 | Patrol Scrub Interval in FSP. |
| 1070 | **/ |
| 1071 | UINT8 PatrolScrubDuration; |
| 1072 | |
| 1073 | /** Offset 0x024C - Patrol Scrub Address Mode |
| 1074 | Selects the address mode between <b>1: System Physical Address (Default)</b>, 0:Reverse |
| 1075 | Address in FSP. |
| 1076 | 0:Reverse Address, 1:System Physical Address |
| 1077 | **/ |
| 1078 | UINT8 PatrolScrubAddrMode; |
| 1079 | |
| 1080 | /** Offset 0x024D - Memory Thermal Throttling Mode |
| 1081 | Memory Configure Memory Thermal Throttling Mode in FSP - 0:Disable, <b>2:CLTT_ENABLE(Default)</b>, |
| 1082 | 3:CLTT_PECI_ENABLE. |
| 1083 | 0:Disable, 2:CLTT_ENABLE, 3:CLTT_PECI_ENABLE |
| 1084 | **/ |
| 1085 | UINT8 thermalthrottlingsupport; |
| 1086 | |
| 1087 | /** Offset 0x024E - Memory Correctable Error Threshold |
| 1088 | Memory Correctable Error Threshold (1 - 32767) used for sparing and leaky bucket in FSP. |
| 1089 | **/ |
| 1090 | UINT16 spareErrTh; |
| 1091 | |
| 1092 | /** Offset 0x0250 - WR CRC feature Control |
| 1093 | Enable/Disable Write CRC in FSP - <b>0:Disable(Default)</b>, 1:Enable. |
| 1094 | 0:Disable, 1:Enable |
| 1095 | **/ |
| 1096 | UINT8 WrCRC; |
| 1097 | |
| 1098 | /** Offset 0x0251 - Adaptive Refresh Management Level |
| 1099 | Selects Adaptive Refresh Management(ARFM) Level when refresh management(RFM) is |
| 1100 | required. <b>0:Default - RAAIMT, RAAMMT, RAADEC(Default)</b>; 1:Level A - RAAIMT-A, |
| 1101 | RAAMMT-A, RAADEC-A; 2:Level B - RAAIMT-B, RAAMMT-B, RAADEC-B; 3:Level C - RAAIMT-C, |
| 1102 | RAAMMT-C, RAADEC-C |
| 1103 | 0:Default - RAAIMT; RAAMMT; RAADEC, 1:Level A - RAAIMT-A; RAAMMT-A; RAADEC-A, 2:Level |
| 1104 | B - RAAIMT-B; RAAMMT-B; RAADEC-B, 3:Level C - RAAIMT-C; RAAMMT-C; RAADEC-C |
| 1105 | **/ |
| 1106 | UINT8 AdaptiveRefreshMgmtLevel; |
| 1107 | |
| 1108 | /** Offset 0x0252 - MEMHOT INPUT Control |
| 1109 | Enable/Disable MEMHOT INPUT in FSP - <b>0:Disable(Default)</b>, 1:Enable. |
| 1110 | 0:Disable, 1:Enable |
| 1111 | **/ |
| 1112 | UINT8 MemHotIn; |
| 1113 | |
| 1114 | /** Offset 0x0253 - MEMHOT OUTPUT Mode |
| 1115 | MEMHOT OUTPUT Mode in FSP - 0:Disable, <b>1:Enable only temphi(Default)</b>, 2:Enable |
| 1116 | temphi & mid, 3:Enable temphi & mid & low. |
| 1117 | 0:Disable, 1:Enable only temphi, 2:Enable temphi & mid, 3:Enable temphi & mid & low |
| 1118 | **/ |
| 1119 | UINT8 MemhotOutputOnlyOpt; |
| 1120 | |
| 1121 | /** Offset 0x0254 - CxlType3LegacyEn |
| 1122 | Enable or disable CXL type 3 device using CXL type 2 flow - <b>0:Disable(Default)</b>, 1:Enable. |
| 1123 | 0:Disable, 1:Enable |
| 1124 | **/ |
| 1125 | UINT8 DfxCxlType3LegacyEn; |
| 1126 | |
| 1127 | /** Offset 0x0255 - DfxPmicSecureMode |
| 1128 | 0:Disable Pmic Secure Mode, 1:Enable Pmic Secure Mode, <b>2:Auto Pmic Secure Mode(Default)</b>. |
| 1129 | 0:Disable Pmic Secure Mode, 1:Enable Pmic Secure Mode, 2:Auto Pmic Secure Mode |
| 1130 | **/ |
| 1131 | UINT8 DfxPmicSecureMode; |
| 1132 | |
| 1133 | /** Offset 0x0256 - IIO PcieSubSystemMode0 |
| 1134 | PcieSubSystemMode[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:IIO_MODE_GEN4_ONLY, 0x01:IIO_MODE_GEN5, |
| 1135 | 0x02:IIO_MODE_CXL, 0x03:IIO_MODE_FORCE_CXL, <b>0x01:IIO_MODE_GEN5(Default)</b> |
| 1136 | **/ |
| 1137 | UINT8 IioPcieSubSystemMode0[8]; |
| 1138 | |
| 1139 | /** Offset 0x025E - IIO PcieSubSystemMode1 |
| 1140 | PcieSubSystemMode[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:IIO_MODE_GEN4_ONLY, 0x01:IIO_MODE_GEN5, |
| 1141 | 0x02:IIO_MODE_CXL, 0x03:IIO_MODE_FORCE_CXL, <b>0x01:IIO_MODE_GEN5(Default)</b> |
| 1142 | **/ |
| 1143 | UINT8 IioPcieSubSystemMode1[8]; |
| 1144 | |
| 1145 | /** Offset 0x0266 - IIO PcieSubSystemMode2 |
| 1146 | PcieSubSystemMode[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:IIO_MODE_GEN4_ONLY, 0x01:IIO_MODE_GEN5, |
| 1147 | 0x02:IIO_MODE_CXL, 0x03:IIO_MODE_FORCE_CXL, <b>0x01:IIO_MODE_GEN5(Default)</b> |
| 1148 | **/ |
| 1149 | UINT8 IioPcieSubSystemMode2[8]; |
| 1150 | |
| 1151 | /** Offset 0x026E - IIO PcieSubSystemMode3 |
| 1152 | PcieSubSystemMode[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:IIO_MODE_GEN4_ONLY, 0x01:IIO_MODE_GEN5, |
| 1153 | 0x02:IIO_MODE_CXL, 0x03:IIO_MODE_FORCE_CXL, <b>0x01:IIO_MODE_GEN5(Default)</b> |
| 1154 | **/ |
| 1155 | UINT8 IioPcieSubSystemMode3[8]; |
| 1156 | |
| 1157 | /** Offset 0x0276 - IIO PcieSubSystemMode4 |
| 1158 | PcieSubSystemMode[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:IIO_MODE_GEN4_ONLY, 0x01:IIO_MODE_GEN5, |
| 1159 | 0x02:IIO_MODE_CXL, 0x03:IIO_MODE_FORCE_CXL, <b>0x01:IIO_MODE_GEN5(Default)</b> |
| 1160 | **/ |
| 1161 | UINT8 IioPcieSubSystemMode4[8]; |
| 1162 | |
| 1163 | /** Offset 0x027E - IIO PcieSubSystemMode5 |
| 1164 | PcieSubSystemMode[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:IIO_MODE_GEN4_ONLY, 0x01:IIO_MODE_GEN5, |
| 1165 | 0x02:IIO_MODE_CXL, 0x03:IIO_MODE_FORCE_CXL, <b>0x01:IIO_MODE_GEN5(Default)</b> |
| 1166 | **/ |
| 1167 | UINT8 IioPcieSubSystemMode5[8]; |
| 1168 | |
| 1169 | /** Offset 0x0286 - IIO PcieSubSystemMode6 |
| 1170 | PcieSubSystemMode[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:IIO_MODE_GEN4_ONLY, 0x01:IIO_MODE_GEN5, |
| 1171 | 0x02:IIO_MODE_CXL, 0x03:IIO_MODE_FORCE_CXL, <b>0x01:IIO_MODE_GEN5(Default)</b> |
| 1172 | **/ |
| 1173 | UINT8 IioPcieSubSystemMode6[8]; |
| 1174 | |
| 1175 | /** Offset 0x028E - CXL Header Bypass |
| 1176 | Enable/Disable the CXL header bypass in FSP - <b>0:Disabled(Default)</b>, 1:Enabled. |
| 1177 | 0:Disable, 1:Enable |
| 1178 | **/ |
| 1179 | UINT8 DfxCxlHeaderBypass; |
| 1180 | |
| 1181 | /** Offset 0x028F - CXL Security Level |
| 1182 | CXL Security Level<br>\n |
| 1183 | 0: Fully Trusted - CXL Device can get access on CXL.$ for host-attached and device |
| 1184 | attached memory ranges in the WB address space.<br>\n |
| 1185 | 1: Partially Trusted - CXL Device can get access on CXL.$ for device attached memory |
| 1186 | ranges only;<br>\n |
| 1187 | 2: Untrusted - All requests on CXL.$ will be aborted by the Host.<br>\n |
| 1188 | <b>3: Auto - Currently identical to Fully Trusted. (Default)</b> |
| 1189 | 0:Fully Trusted, 1:Partially Trusted, 2:Untrusted, 3:Auto |
| 1190 | **/ |
| 1191 | UINT8 DfxCxlSecLvl; |
| 1192 | |
| 1193 | /** Offset 0x0290 |
| 1194 | **/ |
| 1195 | UINT32 DfxCxlDebugModePtr; |
| 1196 | |
| 1197 | /** Offset 0x0294 |
| 1198 | **/ |
| 1199 | UINT32 DfxCxlDebugModeNumber; |
| 1200 | |
| 1201 | /** Offset 0x0298 - Lock Chipset |
| 1202 | Lock or Unlock chipset in FSP - <b>0:Disabled(Default)</b>, 1:Enabled. |
| 1203 | 0:Disable, 1:Enable |
| 1204 | **/ |
| 1205 | UINT8 LockChipset; |
| 1206 | |
| 1207 | /** Offset 0x0299 - MSR Lock Control |
| 1208 | Enable - MSR 3Ah and CSR 80h will be locked in FSP. Power Good reset is needed to |
| 1209 | remove lock bits - <b>0:Disabled(Default)</b>, 1:Enabled. |
| 1210 | 0:Disable, 1:Enable |
| 1211 | **/ |
| 1212 | UINT8 ProcessorMsrLockControl; |
| 1213 | |
| 1214 | /** Offset 0x029A - DFX Enable |
| 1215 | When Enabled, Expose IIO DFX devices and other CPU devices like PMON in FSP - <b>0:Disabled(Default)</b>, |
| 1216 | 1:Enabled. |
| 1217 | 0:Disable, 1:Enable |
| 1218 | **/ |
| 1219 | UINT8 DFXEnable; |
| 1220 | |
| 1221 | /** Offset 0x029B - DFX Disable Bios Done |
| 1222 | When Enabled, suppresses notifying processor via MSR 151h that boot initialization |
| 1223 | is finished in FSP - <b>0:Disabled(Default)</b>, 1:Enabled. |
| 1224 | 0:Disable, 1:Enable |
| 1225 | **/ |
| 1226 | UINT8 DfxDisableBiosDone; |
| 1227 | |
| 1228 | /** Offset 0x029C - Processor Package C State |
| 1229 | Package C State - 0: C0/C1 state, 1: C2 state, 2: C6(non Retention) state, 3: C6(Retention) |
| 1230 | state, 7: No Limit, <b>0xFF: Auto (Default)</b> |
| 1231 | 0: C0/C1 state, 1: C2 state, 2: C6(non Retention) state, 3: C6(Retention) state, |
| 1232 | 7: No Limit, 0xFF: Auto |
| 1233 | **/ |
| 1234 | UINT8 CpuPmPackageCState; |
| 1235 | |
| 1236 | /** Offset 0x029D - Enhanced Intel SpeedStep(R) Tech |
| 1237 | Enhanced Intel SpeedStep(R) Tech - <b>1: Enable(Default)</b>, 0: Disable. |
| 1238 | 0:Disabled, 1:Enabled |
| 1239 | **/ |
| 1240 | UINT8 CpuPmEistEnable; |
| 1241 | |
| 1242 | /** Offset 0x029E - C1E |
| 1243 | C1E - <b>1: Enable(Default)</b>, 0: Disable. |
| 1244 | **/ |
| 1245 | UINT8 CpuPmC1eEnable; |
| 1246 | |
| 1247 | /** Offset 0x029F - Intel SST-PP |
| 1248 | Intel SST-PP Select allows user to choose level - <b>0xFF: Choose lowest level hardware |
| 1249 | supported(Default)</b>, 0: Level 0, 3: Level 3, 4: Level 4. |
| 1250 | **/ |
| 1251 | UINT8 CpuPmIssTdpLevel; |
| 1252 | |
| 1253 | /** Offset 0x02A0 - Activate SST-BF |
| 1254 | SST-BF - <b>0: Disable (Default)</b>, 1: Enabled. |
| 1255 | 0:Disabled, 1:Enabled |
| 1256 | **/ |
| 1257 | UINT8 CpuPmProcessorActivePbf; |
| 1258 | |
| 1259 | /** Offset 0x02A1 |
| 1260 | **/ |
| 1261 | UINT8 UnusedUpdSpace13[7]; |
| 1262 | |
| 1263 | /** Offset 0x02A8 - Socket 0 Core Disable Bitmask |
| 1264 | Set bit(s) to Disable or clear bit(s) to Enable core(s) on Socket 0. NOTE: Any core |
| 1265 | disabled by user will force static SST-PP. |
| 1266 | **/ |
| 1267 | UINT64 CpuPmCoreDisableBitmask0; |
| 1268 | |
| 1269 | /** Offset 0x02B0 - Socket 1 Core Disable Bitmask |
| 1270 | Set bit(s) to Disable or clear bit(s) to Enable core(s) on Socket 1. NOTE: Any core |
| 1271 | disabled by user will force static SST-PP. |
| 1272 | **/ |
| 1273 | UINT64 CpuPmCoreDisableBitmask1; |
| 1274 | |
| 1275 | /** Offset 0x02B8 |
| 1276 | **/ |
| 1277 | UINT8 ReservedMemoryInitUpd[16]; |
| 1278 | |
| 1279 | /** IIO Board settings Hob Ptr |
| 1280 | Pointer to array of IIO_BOARD_SETTINGS_HOB |
| 1281 | **/ |
| 1282 | UINT32 IioBoardSettingsHobPtr; |
| 1283 | |
| 1284 | /** IIO Board Settings Hob length |
| 1285 | The IIO Board Settings Hob Length. |
| 1286 | **/ |
| 1287 | UINT32 IioBoardSettingsHobLength; |
| 1288 | |
| 1289 | /** BIOS Region Base |
| 1290 | Pointer to the location of the BIOS Region |
| 1291 | **/ |
| 1292 | UINT32 BiosRegionBase; |
| 1293 | |
| 1294 | /** BIOS Region Size |
| 1295 | The size of the BIOS Region in bytes |
| 1296 | **/ |
| 1297 | UINT32 BiosRegionSize; |
| 1298 | |
| 1299 | } FSPM_CONFIG; |
| 1300 | |
| 1301 | typedef struct { |
| 1302 | |
| 1303 | /** N/A |
| 1304 | **/ |
| 1305 | FSP_UPD_HEADER FspUpdHeader; |
| 1306 | |
| 1307 | /** N/A |
| 1308 | **/ |
| 1309 | FSPM_ARCH2_UPD FspmArchUpd; |
| 1310 | |
| 1311 | /** N/A |
| 1312 | **/ |
| 1313 | FSPM_CONFIG FspmConfig; |
| 1314 | |
| 1315 | /** N/A |
| 1316 | **/ |
| 1317 | UINT16 UpdTerminator; |
| 1318 | |
| 1319 | } FSPM_UPD; |
| 1320 | |
| 1321 | #pragma pack() |
| 1322 | |
| 1323 | #endif |