| Jincheng Li | 6195357 | 2023-08-01 09:47:48 +0800 | [diff] [blame^] | 1 | /** @file |
| 2 | |
| 3 | Copyright (c) 2019-2023, Intel Corporation. All rights reserved.<BR> |
| 4 | |
| 5 | Redistribution and use in source and binary forms, with or without modification, |
| 6 | are permitted provided that the following conditions are met: |
| 7 | |
| 8 | * Redistributions of source code must retain the above copyright notice, this |
| 9 | list of conditions and the following disclaimer. |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, this |
| 11 | list of conditions and the following disclaimer in the documentation and/or |
| 12 | other materials provided with the distribution. |
| 13 | * Neither the name of Intel Corporation nor the names of its contributors may |
| 14 | be used to endorse or promote products derived from this software without |
| 15 | specific prior written permission. |
| 16 | |
| 17 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 18 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 19 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 20 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
| 21 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 22 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 23 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 24 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 25 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 26 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF |
| 27 | THE POSSIBILITY OF SUCH DAMAGE. |
| 28 | |
| 29 | **/ |
| 30 | |
| 31 | #ifndef _PREV_BOOT_ERR_SRC_HOB_H_ |
| 32 | #define _PREV_BOOT_ERR_SRC_HOB_H_ |
| 33 | |
| 34 | #define FSP_PREV_BOOT_ERR_SRC_HOB_GUID \ |
| 35 | { 0xc5, 0xb5, 0x38, 0x51, 0x69, 0x93, 0xec, 0x48, 0x5b, 0x97, 0x38, 0xa2, 0xf7, 0x09, 0x66, 0x75 } |
| 36 | |
| 37 | #define PREV_BOOT_ERR_SRC_HOB_SIZE 1000 |
| 38 | |
| 39 | #pragma pack(1) |
| 40 | |
| 41 | typedef struct { |
| 42 | UINT16 Length; // Actual size of the error sources used in the HOB |
| 43 | UINT8 HobData[PREV_BOOT_ERR_SRC_HOB_SIZE -2]; // List of Error source structures of format //MCBANK_ERR_INFO or CSR_ERR_INFO |
| 44 | }PREV_BOOT_ERR_SRC_HOB; |
| 45 | |
| 46 | typedef struct{ |
| 47 | UINT8 Type; // McBankType = 1; |
| 48 | UINT8 Segment; |
| 49 | UINT8 Socket; |
| 50 | UINT16 ApicId; // ApicId is Needed only if it a core McBank. |
| 51 | UINT16 McBankNum; |
| 52 | UINT64 McBankStatus; |
| 53 | UINT64 McbankAddr; |
| 54 | UINT64 McBankMisc; |
| 55 | } MCBANK_ERR_INFO; |
| 56 | |
| 57 | typedef struct { |
| 58 | UINT8 Type; // PciExType =2 ; |
| 59 | UINT8 Segment; |
| 60 | UINT8 Bus; |
| 61 | UINT8 Device; |
| 62 | UINT8 Function; |
| 63 | UINT32 AerUncErrSts; |
| 64 | UINT8 AerHdrLogData[16]; |
| 65 | } PCI_EX_ERR_INFO; |
| 66 | |
| 67 | typedef struct { |
| 68 | UINT8 Type; // Other Csr error type =3 ; |
| 69 | UINT8 Segment; |
| 70 | UINT8 Bus; |
| 71 | UINT8 Device; |
| 72 | UINT8 Function; |
| 73 | UINT16 offset; |
| 74 | UINT32 Value; |
| 75 | } CSR_ERR_INFO; |
| 76 | |
| 77 | typedef enum { |
| 78 | McBankType = 1, |
| 79 | PciExType, |
| 80 | CsrOtherType |
| 81 | } ERROR_ACCESS_TYPE; |
| 82 | |
| 83 | #pragma pack() |
| 84 | |
| 85 | #endif //_PREV_BOOT_ERR_SRC_HOB_H_ |