Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 1 | config SOC_INTEL_APOLLOLAKE |
| 2 | bool |
| 3 | help |
| 4 | Intel Apollolake support |
| 5 | |
| 6 | if SOC_INTEL_APOLLOLAKE |
| 7 | |
| 8 | config CPU_SPECIFIC_OPTIONS |
| 9 | def_bool y |
| 10 | select ARCH_BOOTBLOCK_X86_32 |
| 11 | select ARCH_RAMSTAGE_X86_32 |
| 12 | select ARCH_ROMSTAGE_X86_32 |
| 13 | select ARCH_VERSTAGE_X86_32 |
| 14 | # CPU specific options |
| 15 | select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
| 16 | select IOAPIC |
| 17 | select SMP |
| 18 | select SSE2 |
| 19 | select SUPPORT_CPU_UCODE_IN_CBFS |
| 20 | # Misc options |
Alexandru Gagniuc | dfc2b31 | 2015-10-06 17:16:41 -0700 | [diff] [blame] | 21 | select C_ENVIRONMENT_BOOTBLOCK |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 22 | select COLLECT_TIMESTAMPS |
| 23 | select HAVE_INTEL_FIRMWARE |
| 24 | select MMCONF_SUPPORT |
| 25 | select MMCONF_SUPPORT_DEFAULT |
| 26 | select PARALLEL_MP |
| 27 | select PCIEXP_ASPM |
| 28 | select PCIEXP_COMMON_CLOCK |
| 29 | select PCIEXP_CLK_PM |
| 30 | select PCIEXP_L1_SUB_STATE |
| 31 | select REG_SCRIPT |
| 32 | select RELOCATABLE_RAMSTAGE # Build fails if this is not selected |
| 33 | select SOC_INTEL_COMMON |
| 34 | select UDELAY_TSC |
Andrey Petrov | 87fb1a6 | 2016-02-10 17:47:03 -0800 | [diff] [blame] | 35 | select CONSOLE_SERIAL |
| 36 | select BOOTBLOCK_CONSOLE |
| 37 | select TSC_CONSTANT_RATE |
| 38 | select UDELAY_TSC |
| 39 | select TSC_CONSTANT_RATE |
| 40 | select NO_UART_ON_SUPERIO |
| 41 | select DRIVERS_UART_8250MEM_32 |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 42 | |
Alexandru Gagniuc | dfc2b31 | 2015-10-06 17:16:41 -0700 | [diff] [blame] | 43 | config MMCONF_BASE_ADDRESS |
| 44 | hex "PCI MMIO Base Address" |
| 45 | default 0xe0000000 |
| 46 | |
| 47 | config IOSF_BASE_ADDRESS |
| 48 | hex "MMIO Base Address of sideband bus" |
| 49 | default 0xd0000000 |
| 50 | |
| 51 | config DCACHE_RAM_BASE |
| 52 | hex "Base address of cache-as-RAM" |
| 53 | default 0xfef00000 |
| 54 | |
| 55 | config DCACHE_RAM_SIZE |
| 56 | hex "Length in bytes of cache-as-RAM" |
| 57 | default 0x80000 |
| 58 | help |
| 59 | The size of the cache-as-ram region required during bootblock |
| 60 | and/or romstage. |
| 61 | |
| 62 | config DCACHE_BSP_STACK_SIZE |
| 63 | hex |
| 64 | default 0x4000 |
| 65 | help |
| 66 | The amount of anticipated stack usage in CAR by bootblock and |
| 67 | other stages. |
| 68 | |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 69 | config CPU_ADDR_BITS |
| 70 | int |
| 71 | default 36 |
| 72 | |
Andrey Petrov | 87fb1a6 | 2016-02-10 17:47:03 -0800 | [diff] [blame] | 73 | config CONSOLE_UART_BASE_ADDRESS |
| 74 | depends on CONSOLE_SERIAL |
| 75 | hex "MMIO base address for UART" |
| 76 | default 0xde000000 |
| 77 | |
Aaron Durbin | ada13ed | 2016-02-11 14:47:33 -0600 | [diff] [blame] | 78 | # 32KiB bootblock is all that is mapped in by the CSE at top of 4GiB. |
| 79 | config C_ENV_BOOTBLOCK_SIZE |
| 80 | hex |
| 81 | default 0x8000 |
| 82 | |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 83 | endif |